CN201681932U - Encapsulation structure of multi-chip inversion and passive device - Google Patents
Encapsulation structure of multi-chip inversion and passive device Download PDFInfo
- Publication number
- CN201681932U CN201681932U CN2010201777626U CN201020177762U CN201681932U CN 201681932 U CN201681932 U CN 201681932U CN 2010201777626 U CN2010201777626 U CN 2010201777626U CN 201020177762 U CN201020177762 U CN 201020177762U CN 201681932 U CN201681932 U CN 201681932U
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- metal
- metal leg
- feet
- passive device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model relates to an encapsulation structure of a multi-chip inversion and passive device. The encapsulation structure comprises a plurality of metal feet (1), wherein the front surfaces and the back surfaces of the metal feet (1) are respectively provided with a first metal layer (3) and a second metal layer (4); the front surfaces of the metal feet (1) are provided with chips (6) and passive devices (8) by a metal bonding matter (5); and padding plastic package materials (7) are encapsulated at the upper parts of the metal feet (1) and outside the chips (6) and the passive devices (8). The utility model is characterized in that the encapsulation structure is provided with a plurality of pieces of chips (6); packless plastic package materials (2) are embedded at the peripheries of the metal feet (1) and at the area between the metal feet (1) and are used for connecting the lower parts of the metal feet (1); and the size of the back surface of a metal foot (4) is less than that of the front surface of the metal foot (4), so as to form the structure of the metal foot (4) with the upper part being big and the lower part being small. The encapsulation structure has the benefits that the encapsulation cost can be lowered, the optional product category is wide, the chip inversion quality and the product reliability have good stability, and the plastic package bodies and the metal feet have strong restraint ability.
Description
(1) technical field
The utility model relates to upside-down mounting of a kind of multicore sheet and passive device encapsulating structure.Belong to the semiconductor packaging field.
(2) background technology
Traditional flip chip encapsulation structure mainly contains two kinds:
First kind:
After chemical etching and surface electrical coating are carried out in the front of employing metal substrate, stick the resistant to elevated temperatures glued membrane of one deck at the back side of metal substrate and form the leadframe carrier (as shown in Figure 2) that to carry out encapsulation process.
Second kind:
After chemical etching and surface electrical coating are carried out in the front of employing metal substrate, promptly finish the making (as shown in Figure 3) of lead frame.Back etched is then carried out at the back side of lead frame again in encapsulation process.
And the not enough point of two kinds of above-mentioned lead frames below in encapsulation process, having existed:
First kind:
1) but the lead frame of this kind must stick the glued membrane of one deck costliness high temperature resistance because of the back side.So directly increased high cost.
2) but also because the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind, so the load technology in encapsulation process can only be used conduction or nonconducting resin technology, and the technology that can not adopt eutectic technology and slicken solder is fully carried out load, so selectable product category just has bigger limitation.
3) but again because the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind, and in the flip-chip bonding technology in encapsulation process, because but the glued membrane of this high temperature resistance is a soft materials, so caused the instability of flip-chip bonding parameter, seriously influenced the stability of flip-chip quality and production reliability.
4) but again because the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind, and the plastic package process process in encapsulation process, because the high pressure of plastic packaging relation is easy to cause between lead frame and the glued membrane and infiltrates plastic packaging material, be that the kenel of conduction has become insulation pin (as shown in Figure 4) on the contrary because of having infiltrated plastic packaging material and will formerly should belong to metal leg.
Second kind:
The lead frame structure of this kind has carried out etching partially technology in the metal substrate front, though can solve the problem of first kind of lead frame, but because only carried out the work that etches partially in the metal substrate front, and plastic packaging material only envelopes the height of half pin in the plastic packaging process, so the constraint ability of plastic-sealed body and metal leg has just diminished, when if the plastic-sealed body paster is not fine to pcb board, does over again again and heavily paste, with regard to the problem (as shown in Figure 5) that is easy to generate pin.
Especially the kind of plastic packaging material is to adopt when filler is arranged, because material is at the environment and the follow-up surface-pasted stress changing relation of production process, can cause metal and plastic packaging material to produce the crack of vertical-type, its characteristic is the high more then hard more crisp more crack that is easy to generate more of proportion of filler.
(3) summary of the invention
The purpose of this utility model is to overcome above-mentioned deficiency, provides a kind of and reduces that packaging cost, selectable product category are wide, the big upside-down mounting of multicore sheet and the passive device encapsulating structure of constraint ability of good stability, plastic-sealed body and the metal leg of flip-chip quality and production reliability.
The purpose of this utility model is achieved in that upside-down mounting of a kind of multicore sheet and passive device encapsulating structure, comprise the number of metal pin, front and back at described metal leg is respectively arranged with the first metal layer and second metal level, be provided with chip and passive device in the metal leg front by the metal bonding material, outside the top of described metal leg and chip and passive device, be encapsulated with the filler plastic packaging material, described chip is provided with multi-disc, no filler plastic packaging material is set in zone between described metal leg periphery and metal leg and metal leg, described no filler plastic packaging material links into an integrated entity the bottom of metal leg, and make described metal leg back side size less than the positive size of metal leg, form up big and down small metal leg structure.
The beneficial effects of the utility model are:
1) but the glued membrane of one deck costliness high temperature resistance need not sticked in the back side of the lead frame of this kind.So directly reduced high cost.
2) but because the glued membrane of one deck high temperature resistance need not sticked in the back side of the lead frame of this kind yet, so the load technology in encapsulation process is except using conduction or nonconducting resin technology, can also adopt the technology of eutectic technology and slicken solder to carry out load, so selectable product category is just wide.
3) but again because the glued membrane of one deck high temperature resistance need not sticked in the back side of the lead frame of this kind, guaranteed the stability of flip-chip bonding parameter, guaranteed the stability of flip-chip quality and production reliability.
4) but again because the lead frame of this kind need not stick the glued membrane of one deck high temperature resistance, and the plastic package process process in encapsulation process can not cause between lead frame and the glued membrane fully and infiltrate plastic packaging material.
5) because the zone between described metal leg and metal leg is equipped with packless soft gap filler, this packless soft gap filler has the filler plastic packaging material to envelope the height of whole metal leg with the routine in the plastic packaging process, so the constraint ability of plastic-sealed body and metal leg just becomes big, do not have the problem that produces pin again.
(4) description of drawings
Fig. 1 is sheet upside-down mounting of the utility model multicore and passive device encapsulating structure schematic diagram.
Fig. 2 was for sticked the resistant to elevated temperatures glued membrane figure of one deck operation in the past at the back side of metal substrate.
Fig. 3 was for to adopt the front of metal substrate to carry out chemical etching and surface electrical coating flow diagram in the past.
Fig. 4 was for formed insulation pin schematic diagram in the past.
Fig. 5 pin figure for what formed in the past.
Reference numeral among the figure:
(5) embodiment
Fig. 1 is sheet upside-down mounting of the utility model multicore and passive device encapsulating structure schematic diagram.As seen from Figure 1, sheet upside-down mounting of the utility model multicore and passive device encapsulating structure, comprise number of metal pin 1, front and back at described metal leg 1 is respectively arranged with the first metal layer 3 and second metal level 4, be provided with chip 6 and passive device 8 in metal leg 1 front by metal bonding material 5, outside the top of described metal leg 1 and chip 6 and passive device 8, be encapsulated with filler plastic packaging material 7, described chip 6 is provided with multi-disc, no filler plastic packaging material 2 is set in zone between described metal leg 1 periphery and metal leg 1 and metal leg 1, described no filler plastic packaging material 2 links into an integrated entity the bottom of metal leg 1, and make described metal leg 4 back side sizes less than metal leg 4 positive sizes, form up big and down small metal leg 4 structures.Described metal bonding material 5 can adopt tin metal, golden metal, nickel gold metal or titanium nickel gold metal.
Claims (1)
1. multicore sheet upside-down mounting and passive device encapsulating structure, comprise number of metal pin (1), front and back at described metal leg (1) is respectively arranged with the first metal layer (3) and second metal level (4), be provided with chip (6) and passive device (8) in metal leg (1) front by metal bonding material (5), outside the top of described metal leg (1) and chip (6) and passive device (8), be encapsulated with filler plastic packaging material (7), it is characterized in that: described chip (6) is provided with multi-disc, no filler plastic packaging material (2) is set in zone between described metal leg (1) periphery and metal leg (1) and metal leg (1), described no filler plastic packaging material (2) links into an integrated entity the bottom of metal leg (1), and make described metal leg (4) back side size less than the positive size of metal leg (4), form up big and down small metal leg (4) structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010201777626U CN201681932U (en) | 2010-04-26 | 2010-04-26 | Encapsulation structure of multi-chip inversion and passive device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010201777626U CN201681932U (en) | 2010-04-26 | 2010-04-26 | Encapsulation structure of multi-chip inversion and passive device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201681932U true CN201681932U (en) | 2010-12-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010201777626U Expired - Lifetime CN201681932U (en) | 2010-04-26 | 2010-04-26 | Encapsulation structure of multi-chip inversion and passive device |
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| CN (1) | CN201681932U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103325752A (en) * | 2012-03-21 | 2013-09-25 | 英飞凌科技股份有限公司 | Circuit package, electronic circuit package, and method for encapsulating an electronic circuit |
| CN103560121A (en) * | 2013-08-31 | 2014-02-05 | 华天科技（西安）有限公司 | Frame csp package with bumping optimization technology based on chips of different sizes and production process thereof |
-
2010
- 2010-04-26 CN CN2010201777626U patent/CN201681932U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103325752A (en) * | 2012-03-21 | 2013-09-25 | 英飞凌科技股份有限公司 | Circuit package, electronic circuit package, and method for encapsulating an electronic circuit |
| CN103325752B (en) * | 2012-03-21 | 2016-12-28 | 英飞凌科技股份有限公司 | Circuit package, electronic circuit package and the method being used for encapsulating electronic circuit |
| US11189537B2 (en) | 2012-03-21 | 2021-11-30 | Infineon Technologies Ag | Circuit package, an electronic circuit package, and methods for encapsulating an electronic circuit |
| CN103560121A (en) * | 2013-08-31 | 2014-02-05 | 华天科技（西安）有限公司 | Frame csp package with bumping optimization technology based on chips of different sizes and production process thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20101222 |