CN201741061U - Integrated circuit device - Google Patents
Integrated circuit device Download PDFInfo
- Publication number
- CN201741061U CN201741061U CN2010201295587U CN201020129558U CN201741061U CN 201741061 U CN201741061 U CN 201741061U CN 2010201295587 U CN2010201295587 U CN 2010201295587U CN 201020129558 U CN201020129558 U CN 201020129558U CN 201741061 U CN201741061 U CN 201741061U
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- integrated circuit
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Abstract
The utility model discloses an integrated circuit device which comprises a chip (1) and a digital signal processing device, a data caching device (2), a waveform meter (3), a 48 bit phrase accumulator (4), a Burst control unit (4), a trigger control unit (6) and a system reference clock (7), wherein the waveform meter (3) adopts an RAM (random-access memory) rewritable memorizer. The integrated circuit device is provided with an EXT (extension) A/D data processing unit (8), a data control unit (9) and a frequency control character processor (10), wherein one end of the EXT A/D data processing unit (8) is provided with an FM/Sweep processor (11). By adopting the digital frequency synthesis integrated circuit provided by the utility model, the defects of less additional functions, low resolution of frequency and amplitude, and slow transmission are overcome. The integrated circuit device can be widely applied in the production of precise signal generation instruments.
Description
Technical field
The utility model relates to a kind of device of electronic digital signal Processing, refers more particularly to a kind of integrated circuit (IC) apparatus that is used to produce accurate signal generator.
Background technology
At present, integrated circuit (IC) chip generally is used for the product of general usefulness on the market, be mainly the design of phaselocked loop and communication system, if directly apply to produce accurate signal generator, price is very high on the one hand, have influence on frequency and amplitude discrimination in addition, the chip frequency resolution of general general usefulness is lower than the requirement of professional signal generator, digital to analog converter reduces the Bit number because of speed improves, and has influence on amplitude discrimination, and additional function is few on the other hand, use control procedure complexity, the chip product production standard of general usefulness comprises sine wave, two kinds of cosine wave (CW)s mostly are the serial input greatly on the communication interface to counter, speed is slower.
Summary of the invention
The technical problems to be solved in the utility model provides a kind of integrated circuit (IC) apparatus, this device can solve frequency when producing accurate signal generator and amplitude discrimination is low and the few problem of additional function, is a kind of multi-functional Direct Digital frequency synthesis integrated circuit (IC) apparatus.
In order to solve the problems of the technologies described above, the utility model provides a kind of integrated circuit (IC) apparatus, comprise chip and digital signal treating apparatus, comprise data buffer, waveform table and 48 phase accumulators, also comprise the Burst control module, trigger control unit and system's reference clock, this waveform table is the RAM scratch pad memory, 48 phase accumulators are connected with data buffer, waveform table one end is provided with the Burst control module, 48 phase accumulators, Direct Digital frequency synthesis integrated circuit of the common composition of data buffer and waveform table, the Burst control module is clipped in the Direct Digital frequency synthesis integrated circuit.
Integrated circuit (IC) apparatus is provided with EXT A/D data processing unit, DCU data control unit and frequency control character processor; EXT A/D data processing unit one end is provided with the FM/Sweep processor; FM/Sweep processor and frequency control character processor are connection status, and Burst control module and DCU data control unit are connection status; DCU data control unit and trigger control unit and system's reference clock are connection status.
After adopting as above technical scheme, Direct Digital frequency synthesis integrated circuit comprises data buffer, waveform table and 48 phase accumulators, this waveform table is the RAM scratch pad memory, can change the required Wave data of user, and then the frequency size of control system reference clock makes it to produce triangular wave, square wave or other waveforms, makes additional function increase; EXT A/D data processing unit one end is provided with the FM/Sweep processor, digital to analog converter converts analog voltage to the digital signal of variation, by the FM/Sweep processor digital signal is converted to again and connect the frequency control character that changes 48Bits, in the Direct Digital frequency synthesizer circuit, produce frequency change, make frequency and amplitude discrimination improve; Also comprise Burst control module, trigger control unit and system's reference clock in the integrated circuit, integrated circuit (IC) apparatus is provided with EXT A/D data processing unit, DCU data control unit and frequency control character processor, whole mode and the communication of counter interface of adopting and connecting input, thereby inversion frequency or frequency connection speed are easy to control fast.
Description of drawings
Fig. 1 is the working control block schematic diagram of integrated circuit (IC) apparatus of the present utility model.
Embodiment
As shown in Figure 1, a kind of integrated circuit (IC) apparatus, comprise chip 1 and digital signal treating apparatus, this Direct Digital frequency synthesis integrated circuit comprises data buffer 2, waveform table 3 and 48 phase accumulators 4, also comprise Burst control module 5, trigger control unit 6 and system's reference clock 7, this waveform table 3 is the RAM scratch pad memory, integrated circuit (IC) apparatus is provided with EXT A/D data processing unit 8, DCU data control unit 9 and frequency control character processor 10, EXT A/D data processing unit 8 one ends are provided with FM/Sweep processor 11, on integrated circuit (IC) apparatus, be provided with power supply control, start counter, FM/Sweep processor 11 is connection status with frequency control character processor 10, DCU data control unit 9 is sent to FM/Sweep processor 11 with data message, simultaneously, EXT A/D data processing unit 8 carries out data processing, analog voltage is converted to the digital signal of variation, FM/Sweep processor 11 becomes the data-switching that receives the frequency control character of continually varying 48Bits, frequency control character processor 10 is put into 48Bits in the Direct Digital frequency synthesizer circuit in order apace, make this circuit that frequency change be arranged, 48 phase accumulators 4 are connected with data buffer 2,48 phase accumulators 4, data buffer 2 and Direct Digital frequency synthesis integrated circuit that has 214MHz/48bits of waveform table 3 common compositions, waveform table 3 one ends are provided with Burst control module 5, Burst control module 5 is clipped in the Direct Digital frequency synthesis integrated circuit, DCU data control unit 9 is connection status with trigger control unit 6 and system's reference clock 7, the data that transmit are by 48 phase accumulators 4, by data buffer 2 data are sent to Burst control module 5 again, Burst control module 5 and system's reference clock 7 synchronous comparison output signal phase places, and cooperate trigger control unit 6 to send signal, last signal is sent in the waveform table 3, this waveform table 3 is the erasable internal memory of RAM, the required Wave data of waveform table 3 changes, the frequency control character is fixed as " 1 ", the frequency size of waveform table 3 control system reference clocks 7 makes it to produce triangular wave, data are sent to digital to analog converter, carry out next routine processes.
Claims (5)
1. integrated circuit (IC) apparatus, comprise chip (1) and digital signal treating apparatus, it is characterized in that: comprise data buffer (2), waveform table (3) and 48 phase accumulators (4), also comprise Burst control module (5), trigger control unit (6) and system's reference clock (7), this waveform table (3) is the RAM scratch pad memory, 48 phase accumulators (4) are connected with data buffer (2), waveform table (3) one ends are provided with Burst control module (5), 48 phase accumulators (4), data buffer (2) and waveform table (3) are formed a Direct Digital frequency synthesis integrated circuit jointly, and Burst control module (5) is clipped in the Direct Digital frequency synthesis integrated circuit.
2. a kind of integrated circuit (IC) apparatus according to claim 1 is characterized in that: integrated circuit (IC) apparatus is provided with EXT A/D data processing unit (8), DCU data control unit (9) and frequency control character processor (10).
3. a kind of integrated circuit (IC) apparatus according to claim 2 is characterized in that: EXT A/D data processing unit (8) one ends are provided with FM/Sweep processor (11).
4. a kind of integrated circuit (IC) apparatus according to claim 3 is characterized in that: FM/Sweep processor (11) is connection status with frequency control character processor (10), and Burst control module (5) is connection status with DCU data control unit (9).
5. a kind of integrated circuit (IC) apparatus according to claim 4 is characterized in that: DCU data control unit (9) is connection status with trigger control unit (6) and system's reference clock (7).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2010201295587U CN201741061U (en) | 2010-03-12 | 2010-03-12 | Integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2010201295587U CN201741061U (en) | 2010-03-12 | 2010-03-12 | Integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
CN201741061U true CN201741061U (en) | 2011-02-09 |
Family
ID=43556337
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CN2010201295587U Expired - Fee Related CN201741061U (en) | 2010-03-12 | 2010-03-12 | Integrated circuit device |
Country Status (1)
Country | Link |
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CN (1) | CN201741061U (en) |
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2010
- 2010-03-12 CN CN2010201295587U patent/CN201741061U/en not_active Expired - Fee Related
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Date | Code | Title | Description |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110209 Termination date: 20150312 |
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EXPY | Termination of patent right or utility model |