CN201032711Y - Frequency generator of digital direct synthesizer - Google Patents
Frequency generator of digital direct synthesizer Download PDFInfo
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- CN201032711Y CN201032711Y CN 200720031890 CN200720031890U CN201032711Y CN 201032711 Y CN201032711 Y CN 201032711Y CN 200720031890 CN200720031890 CN 200720031890 CN 200720031890 U CN200720031890 U CN 200720031890U CN 201032711 Y CN201032711 Y CN 201032711Y
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Abstract
The utility model relates to a direct synthesizer of frequency generator, which comprises a serial interface electric circuit, a miniature processor of an input terminal serial interface electric circuit, a frequency synthesizer of the miniature processor connected with the input terminal and a low pass filter circuit of the frequency synthesizer connected with the input terminal. The serial interface electric circuit transmits the control signal provided by a host machine to the miniature processor which converts the control signal into a frequency word and a control word. The control frequency synthesizer outputs a corresponding high resolution frequency signal. A low pass filter outputs a spectrum sine wave, after filtering and reshaping the high resolution frequency signal. The utility model achieves the 10-6Hz frequency resolution under the 50MHz reference signal, adopting the direct frequency synthesizer. The frequency control signal controlled by an upper computer terminal generates a frequency speed up to nanosecond magnitude. The utility model has the advantages of simple electric circuit, strong anti-jamming capability, low product cost and convenient large-scale production, being able to be utilized as the frequency generator of the correspondence, electronic measurement, navigation localization and other equipments.
Description
Technical field
The utility model belongs to the frequency generator technical field, is specifically related to the frequency generator frequency generator of digital direct synthesizer.
Background technology
In technical fields such as modern communications, electronic measurements, navigator fix and timing system, frequency generator has become indispensable standarized component.Simultaneously because the fast development of modern communication technology is also more and more to the demand of high resolution frequency generator.
At present, the main means of realization high resolution frequency generator have direct synthesis technique and indirect phase-locked loop synthetic method.Direct synthesis technique is to realize multistage continuous mixing and frequency division by analog circuit, obtains very little frequency step, and because of the simulation circuit structure complexity, not easy of integration and control can not produce high-resolution frequency signal.Indirectly the phase-locked loop synthetic method is to make the stability of output frequency signal and precision near the reference oscillation source by heterogeneous loop technique and fractional frequency division technology, can export high-resolution frequency signal, raising along with frequency resolution, the locking time of phase-locked loop is also just long more, and the change-over time of frequency is also long more.
Existing frequency generator exist the frequency inverted time long, frequency resolution is low and breadboardinization is difficult to shortcomings such as integrated, that volume is big, makes promoting the use of of this frequency generator be restricted.
Summary of the invention
Technical problem to be solved in the utility model is to overcome the shortcoming of said frequencies generator, and the frequency generator of the digital direct synthesizer that a kind of change-over time is short, resolution is high, volume is little is provided.
Solving the problems of the technologies described above the technical scheme that is adopted is that it comprises: serial interface circuit; Microprocessor, the input termination serial interface circuit of this circuit; Frequency synthesizer, the input termination microprocessor of this circuit; Low-pass filter circuit, the input termination frequency synthesizer of this circuit.
Microprocessor of the present utility model is: 21 pin and 22 pin of integrated circuit U1 connect serial interface circuit, the end of 13 pin connecting resistance R4 and an end of capacitor C 1,16 pin connect the oscillating circuit that capacitor C 3 is connected with capacitor C 4 and crystal oscillator Y1 with 17 pin, 47 pin and 51 pin connect the two ends of capacitor C 5 respectively, 11 pin of integrated circuit U1,12 pin, 18 pin, 19 pin, 23 pin, 33 pin, 35 pin, 71 pin connect the 3.3V positive source, 2 pin of integrated circuit U1,14 pin, 15 pin, 20 pin, 24 pin, 34 pin, 36 pin, 42 pin, 52 pin, 72 pin ground connection, the other end ground connection of capacitor C 1 and capacitor C 2, the ADDR0 of integrated circuit U1～ADDR5 end is by the bus interface frequency synthesizer, D0～D7 end is by the bus interface frequency synthesizer, 70 pin and 73～78 pin connect frequency synthesizer.
The model of integrated circuit U1 of the present utility model is AT89C5131A.
By serial interface circuit the control signal that main frame provides is transferred to microprocessor, microprocessor is converted to frequency word and control word with control signal, the control frequency synthesizer is exported corresponding high resolution frequency signal, and by low pass filter it is carried out the pure sine wave of output spectrum behind the filter shape.The utility model is compared with existing frequency generator, adopts direct synthesizer, under the reference signal of 50MHz, can realize 10
-6The frequency resolution of Hz.The control signal of frequency is produced frequency speed and is exceedingly fast by the control of host computer terminal, reaches nanosecond order.The utlity model has that circuit is simple, antijamming capability is strong, product cost is low, be convenient to advantages such as large-scale production, can be used as the frequency generator of equipment such as communication, electronic measurements and navigator fix.
Description of drawings
Fig. 1 is an electrical schematic diagram of the present utility model.
Fig. 2 is the electronic circuit schematic diagram of an embodiment of the utility model.
Embodiment
Below in conjunction with drawings and Examples the utility model is further described, but the utility model is not limited to these embodiment.
Fig. 1 is an electrical principle block diagram of the present utility model, referring to Fig. 1.In Fig. 1, the utility model is to be connected and composed by serial interface circuit, microprocessor, frequency synthesizer, low pass filter.The output termination microprocessor of serial interface circuit, the output termination frequency synthesizer of microprocessor, the low-pass filter of output termination of frequency synthesizer.Frequency control signal outputs to microprocessor by serial interface circuit, and microprocessor is converted into the input port buffer memory of frequency numeral and control figure write frequency synthesizer with frequency control signal, and provides external timing signal to frequency synthesizer.Frequency synthesizer externally writes internal register with frequency numeral and control figure in the input port buffer memory under the clock signal effect, and exports low pass filter to according to frequency numeral and the synthetic high-resolution frequency of control figure.Export and the corresponding sinusoidal frequency signal of control signal behind the notch cuttype frequency signal process shaping filter of low pass filter with frequency synthesizer output.
In Fig. 2, the serial interface circuit of present embodiment is connected and composed by socket 1, resistance R 1, resistance R 2, resistance R 3.1 pin of socket J1 connect 5V positive source, 2 pin connecting resistance R1 an end, 3 pin connecting resistance R2 an end and connect power vd D, 4 pin ground connection, another termination microprocessor of resistance R 1, resistance R 2 by resistance R 3.
The microprocessor of present embodiment is connected and composed by integrated circuit U1, resistance R 4, capacitor C 1～capacitor C 5, crystal oscillator Y1, and the model of integrated circuit U1 is AT89C5131A.The other end of the 21 pin connecting resistance R2 of integrated circuit U1, the other end of 22 pin connecting resistance R1, the end of 13 pin connecting resistance R4 and an end of capacitor C 1,16 pin connect the oscillating circuit that capacitor C 3 is connected with capacitor C 4 and crystal oscillator Y1 with 17 pin, 47 pin and 51 pin connect the two ends of capacitor C 5 respectively, 11 pin of integrated circuit U1,12 pin, 18 pin, 19 pin, 23 pin, 33 pin, 35 pin, 71 pin connect the 3.3V positive source, 2 pin of integrated circuit U1,14 pin, 15 pin, 20 pin, 24 pin, 34 pin, 36 pin, 42 pin, 52 pin, 72 pin ground connection, the other end ground connection of capacitor C 1 and capacitor C 2, the ADDR0 of integrated circuit U1～ADDR5 end is by the bus interface frequency synthesizer, D0～D7 end is by the bus interface frequency synthesizer, 70 pin and 73～78 pin connect frequency synthesizer.
The frequency synthesizer of present embodiment is connected and composed by integrated circuit U2, resistance R 5～resistance R 8, capacitor C 6, capacitor C 7, and the model of integrated circuit U2 is AD9852.The ADDR0 of integrated circuit U2～ADDR5 end is by ADDR0～ADDR5 end of bus interface integrated circuit U1, D0～D7 end is by D0～D7 end of bus interface integrated circuit U1,20 pin are by 78 pin of bus interface U1,21 pin are by 77 pin of bus interface U1,22 pin are by 76 pin of bus interface U1,29 pin are by 75 pin of bus interface U1,30 pin are by 70 pin of bus interface integrated circuit U1,71 pin are by 74 pin of bus interface integrated circuit U1,70 pin are by 73 pin of bus interface integrated circuit U1,61 pin connect an end of capacitor C 6 by resistance R 5,56 pin are by resistance R 6 ground connection, 55 pin connect an end of capacitor C 7,51 pin are by resistance R 7 ground connection, 49 pin are by resistance R 8 ground connection, 80 pin of integrated circuit U2,79 pin, 74 pin, 73 pin, 65 pin, 64 pin, 60 pin, 54 pin, 50 pin, 44 pin, 38 pin, 37 pin, 31 pin, 32 pin, 23 pin, 24 pin, 25 pin, 9 pin, 10 pin connect the 3.3V positive source, 11 pin of integrated circuit U2,12 pin, 26 pin, 27 pin, 28 pin, 33 pin, 34 pin, 39 pin, 40 pin, 41 pin, 45 pin, 46 pin, 47 pin, 59 pin, 62 pin, 66 pin, 67 pin, 72 pin, 77 pin ground connection, another termination 3.3V positive source of capacitor C 6 and capacitor C 7,48 pin and 52 pin of integrated circuit U2 connect low pass filter.
The low pass filter of present embodiment is connected and composed by capacitor C 8～capacitor C 21, coil L1～coil L6, socket J2, socket J3.48 pin of the termination integrated circuit U2 of capacitor C 8 and capacitor C 11 and coil L1, another termination capacitor C 9 of capacitor C 8 and coil L1 and the end of capacitor C 12 and coil L2, another termination capacitor C 10 of capacitor C 9 and coil L2 and the end of capacitor C 13 and coil L3, one termination socket J2 of the other end of capacitor C 10 and coil L3 and capacitor C 14, the other end ground connection of capacitor C 11～capacitor C 14.52 pin of the termination integrated circuit U2 of capacitor C 15 and capacitor C 18 and coil L4, another termination capacitor C 16 of capacitor C 15 and coil L4 and the end of capacitor C 19 and coil L5, another termination capacitor C 17 of capacitor C 16 and coil L5 and the end of capacitor C 20 and coil L6, one termination socket J3 of the other end of capacitor C 17 and coil L6 and capacitor C 21, the other end ground connection of capacitor C 18～capacitor C 21.
Operation principle of the present utility model is as follows:
Frequency control signal is imported by 21 pin and 22 pin of integrated circuit U1 through resistance R 1 and resistance R 2 by socket J1 input, is converted to address value, frequency word, control word and outside refresh clock signal through integrated circuit U1.Address value outputs to ADDR0～ADDR7 end of integrated circuit U2 from ADDR0～ADDR7 end of integrated circuit U1, frequency word outputs to D0～D7 end of integrated circuit U2 from D0～D7 end of integrated circuit U1, control word outputs to 21,22,29,30,56,70 pin of integrated circuit U2 from 73～77 pin of integrated circuit U1, and outside refresh clock signal outputs to 20 pin of integrated circuit U2 from 78 pin of integrated circuit U1.The 10MHz external reference signal is from the 69 pin input of integrated circuit U2, and externally control signal and the frequency word by 21,22,29,30,56,70 pin and D0～D7 end input synthesizes external reference signal the correspondent frequency signal and output to low pass filter by port IOUT1 and IOUT2 under the effect of refresh clock.Export by socket J2 behind the six rank elliptic filters of the frequency signal of the IOUT1 port output of integrated circuit U2 by capacitor C 8～capacitor C 14 and coil L1～coil L3 composition.Export by socket J3 behind the six rank elliptic filters of the frequency signal of the IOUT2 port output of integrated circuit U2 by capacitor C 15～capacitor C 21 and coil L4～coil L6 composition.
Claims (3)
1. the frequency generator of a digital direct synthesizer is characterized in that it comprises:
Serial interface circuit;
Microprocessor, the input termination serial interface circuit of this circuit;
Frequency synthesizer, the input termination microprocessor of this circuit;
Low-pass filter circuit, the input termination frequency synthesizer of this circuit.
2. according to the frequency generator of the described digital direct synthesizer of claim 1, it is characterized in that said microprocessor is: 21 pin and 22 pin of integrated circuit U1 connect serial interface circuit, the end of 13 pin connecting resistance R4 and an end of capacitor C 1,16 pin connect the oscillating circuit that capacitor C 3 is connected with capacitor C 4 and crystal oscillator Y1 with 17 pin, 47 pin and 51 pin connect the two ends of capacitor C 5 respectively, 11 pin of integrated circuit U1,12 pin, 18 pin, 19 pin, 23 pin, 33 pin, 35 pin, 71 pin connect the 3.3V positive source, 2 pin of integrated circuit U1,14 pin, 15 pin, 20 pin, 24 pin, 34 pin, 36 pin, 42 pin, 52 pin, 72 pin ground connection, the other end ground connection of capacitor C 1 and capacitor C 2, the ADDR0 of integrated circuit U1～ADDR5 end is by the bus interface frequency synthesizer, D0～D7 end is by the bus interface frequency synthesizer, 70 pin and 73～78 pin connect frequency synthesizer.
3. according to the frequency generator of the described digital direct synthesizer of claim 2, it is characterized in that: the model of said integrated circuit U1 is AT89C5131A.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200720031890 CN201032711Y (en) | 2007-05-30 | 2007-05-30 | Frequency generator of digital direct synthesizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200720031890 CN201032711Y (en) | 2007-05-30 | 2007-05-30 | Frequency generator of digital direct synthesizer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201032711Y true CN201032711Y (en) | 2008-03-05 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200720031890 Expired - Fee Related CN201032711Y (en) | 2007-05-30 | 2007-05-30 | Frequency generator of digital direct synthesizer |
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| Country | Link |
|---|---|
| CN (1) | CN201032711Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111507054A (en) * | 2019-01-31 | 2020-08-07 | 株式会社村田制作所 | Digital output monitoring circuit and high-frequency front-end circuit |
-
2007
- 2007-05-30 CN CN 200720031890 patent/CN201032711Y/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111507054A (en) * | 2019-01-31 | 2020-08-07 | 株式会社村田制作所 | Digital output monitoring circuit and high-frequency front-end circuit |
| CN111507054B (en) * | 2019-01-31 | 2023-11-03 | 株式会社村田制作所 | Digital output monitoring circuit and high frequency front-end circuit |
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080305 |