CN202841081U - DDS (direct digital synthesis) waveform generator on basis of CORDIC (coordinated rotation digital computer) algorithm - Google Patents

Abstract

The utility model discloses a DDS (direct digital synthesis) waveform generator on the basis of a CORDIC (coordinated rotation digital computer) algorithm. The DDS waveform generator comprises a clock module, an FPGA (field programmable gate array) chip, a digital and analog conversion module, a power chip and a JTAG (joint test action group) interface; the FPGA chip comprises a CORDIC phase accumulation module and a CORDIC phase switching module connected to the rear end of the CORDIC phase accumulation module; the power chip and the JTAG interface are connected onto the FPGA chip; and the clock module is connected with the CORDIC phase accumulation module, the CORDIC phase switching module and the digital and analog conversion module in a signal input manner. The DDS waveform generator has the advantages that the requirement on storage capacity is low, and signals outputted by the DDS waveform generator are wide in frequency range and high in precision.

Description

DDS waveform generator based on cordic algorithm

Technical field

[0001] the utility model belongs to electrical application technology, specifically refers to a kind of DDS waveform generator based on cordic algorithm.

Background technology

[0002] Direct Digital frequency synthesis (Direct Digital Synthesis, DDS) be a kind of directly technology of synthetic required waveform, high, reliable and stable, the easy control of its frequency resolution, phase place are continuous etc., and advantage has obtained increasing attention and application.Some need that frequency resolution is high, phase noise is low, with wide application scenario, especially in communication, radar system, be widely used.Along with the progress of large scale integrated circuit technology, the FPGA technology is improved greatly and is used, and realizes DDS with fpga chip, can design according to user's needs, and can change neatly system configuration in system.But the method that traditional DDS generally is based on storage list realizes that the method requires the storage list capacity very large, is unfavorable for realizing in FPGA.

Summary of the invention

The purpose of this utility model is the shortcoming and defect that exists in order to overcome prior art, and provides a kind of storage capacity requirement low, and the DDS waveform generator based on cordic algorithm that the frequency range of output signal is wide, precision is high.

For achieving the above object, the technical solution of the utility model is to comprise with lower module:

Clock module is used for providing clock signal,

Fpga chip, this fpga chip include the phase-accumulated module of CORDIC and are connected in the CORDIC phase conversion of the phase-accumulated module of CORDIC rear end,

D/A converter module is connected in the output of CORDIC phase conversion,

Be connected in power supply chip and jtag interface on the fpga chip,

Described clock module consists of the signal input with the phase-accumulated module of CORDIC, CORDIC phase conversion and D/A converter module and is connected.

The output that further setting is described D/A converter module also is connected with low-pass filter circuit.

The utility model utilizes the fpga chip based on cordic algorithm, method by iteration, only need a small amount of memory space, and the iteration of every one-level only need to be by simple displacement, add/subtraction and a small amount of table lookup operation, just can calculate numerical value, the frequency range of output signal can reach 0 ~ 10MHz, and the step-length of signal frequency is 0.1Hz.And by the design of flowing structure, can reduce the FPGA resource consumption and do not affect computational accuracy.

Below in conjunction with specification drawings and specific embodiments the utility model is done further introduction.

Description of drawings

Fig. 1 the utility model theory diagram;

Fig. 2 the utility model is based on the DDS waveform generating system block diagram of cordic algorithm.

Embodiment

Below by embodiment the utility model is carried out concrete description; only be used for the utility model is further specified; can not be interpreted as the restriction to the utility model protection range, the technician in this field can make some nonessential improvement and adjustment to the utility model according to the content of above-mentioned utility model.

Embodiment of the present utility model shown in Fig. 1-2 comprises with lower module:

Clock module is used for providing clock signal,

Fpga chip, this fpga chip include the phase-accumulated module of CORDIC and are connected in the CORDIC phase conversion of the phase-accumulated module of CORDIC rear end, and the model of this fpga chip of present embodiment is EP3C40Q240C8.

D/A converter module, it is connected in the output of CORDIC phase conversion,

Be connected in power supply chip and jtag interface on the fpga chip,

Described clock module consists of the signal input with the phase-accumulated module of CORDIC, CORDIC phase conversion and D/A converter module and is connected.

In addition, the output of the described D/A converter module of present embodiment also is connected with low-pass filter circuit.

Claims (2)

1. DDS waveform generator based on cordic algorithm is characterized in that: comprise with lower module:

Clock module is used for providing clock signal;

Fpga chip, this fpga chip include the phase-accumulated module of CORDIC and are connected in the CORDIC phase conversion of the phase-accumulated module of CORDIC rear end;

D/A converter module, it is connected in the output of CORDIC phase conversion;

Be connected in power supply chip and jtag interface on the fpga chip;

Described clock module consists of the signal input with the phase-accumulated module of CORDIC, CORDIC phase conversion and D/A converter module and is connected.

2. a kind of DDS waveform generator based on cordic algorithm according to claim 1 is characterized in that the output of described D/A converter module also is connected with low-pass filter circuit.

Images