CN201364895Y - 高散热性的半导体封装器件 - Google Patents

高散热性的半导体封装器件 Download PDF

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CN201364895Y
CN201364895Y CNU2009200886924U CN200920088692U CN201364895Y CN 201364895 Y CN201364895 Y CN 201364895Y CN U2009200886924 U CNU2009200886924 U CN U2009200886924U CN 200920088692 U CN200920088692 U CN 200920088692U CN 201364895 Y CN201364895 Y CN 201364895Y
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integrated circuit
chip
plastic packaging
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万承钢
吴赟
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Honor Trust Technology Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
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    • HELECTRICITY
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Abstract

本实用新型涉及高散热性的半导体封装器件,以适应发展趋势的需要,有效解决半导体封装器件的散热性能差,承载电流和功率低的问题,其解决的技术方案是,包括塑封料封胶体及其集成电路芯片,集成电路芯片置于塑封料封胶体内,集成电路芯片经导线同集成电路芯片外的管脚相连,塑封料封胶体上部中心处开有梯形沟槽,梯形沟槽内装有成型引线框架,成型引线框架经其下部的导电材料同集成电路芯片相连,梯形沟槽内经散热片底座装有散热器,本实用新型结构新颖独特,散热装置呈拆装式,可实现控制器件与分立器件集成到同一集成电路中,从而提高电路的集成度,使电路结构更简单,产品体积更小,并直接降低了电路用料成本。

Description

高散热性的半导体封装器件
一、技术领域
本实用新型是一种高散热性的半导体封装器件,特别是能根据不同芯片的散热需求可方便的选择标准的散热模块的高散热性的半导体封装器件。
二、背景技术
随着半导体行业的飞速发展,集成电路的元件越来越多、体积越来越小及功能越来越强,对集成电路的功率要求也越来越高。集成电路在运作时,随着电流通过内部电阻等元件便会产生大量的热能,而这些热能若不急时的散发出去,便会缩短集成电路的寿命甚至烧毁元件。因此,集成电路的散热性能直接影响其所能承载的功率。
目前半导体集成电路的封装由于取决于封装的限制,散热问题不能有效的解决,一般集成电路只能是小功率器件。故而在电路应用当中,多采用集成电路控制器件去控制大功率的分立器件,并在分立器件上去加载散热装置以达到散热要求,这种在每个元件上加装散热装置,结构比较复杂也耗费成本,且电路占用空间较大。传统的分立器件往往需要根据器件不同的安装尺寸和散热要求定制不同的散热装置,使得设计和生产过程需要额外地增加采购前置时间。在集成电路快速发展趋势下,这种封装结构必然难以满足需求,其改进与创新势在必行。
三、实用新型内容
针对上述情况,为克服现有技术缺陷,本实用新型之目的就是提供一种可方便拆装散热装置及能达到高效散热的高散热性的半导体封装器件,以适应发展趋势的需要,有效解决半导体封装器件的散热性能差,承载电流和功率低的问题,其解决的技术方案是,采用可方便拆装、散热结构,即在封装前将引线框架的底部设计成梯形卡槽式结构,解决在封装完成后加散热装置时的复杂性;再将散热装置底部也做成梯形形状,与引线框架的底部相配合。散热装置实现标准模块化,集成电路封装体侧面的梯形插槽插装在器件上部,减少不同引脚和尺寸的器件需要定制各种规格的散热装置环节,这样就降低了成本及缩短生产周期;本实用新型的集成电路芯片实行倒装结构,塑封成型后去除多余的载体部分,塑封体包围引线框架周边并露出引线框架底部梯形槽内部及上表面,散热基体暴露在封装体表面。据此,本实用新型的结构是,包括塑封料封胶体及其集成电路芯片,集成电路芯片置于塑封料封胶体内,集成电路芯片经导线同集成电路芯片外的管脚相连,塑封料封胶体上部中心处开有梯形沟槽,梯形沟槽内装有成型引线框架,成型引线框架经其下部的导电材料同集成电路芯片相连,梯形沟槽内经散热片底座装有散热器,本实用新型结构新颖独特,散热装置呈拆装式,可满足不同的散热的需要,具有优良的散热性能,可大大提高器件的承载电流和功率,可实现控制器件与分立器件集成到同一集成电路中,从而提高电路的集成度,使电路结构更简单,产品体积更小,并直接降低了电路用料成本。
四、附图说明
图1为本实用新型的塑封料封胶体部分剖面结构主视图。
图2为本实用新型的散热装置结构立体图。
图3为本实用新型的结构立体图。
五、具体实施方式
以下结合附图对本实用新型的具体实施方式作详细说明。
由图1-图3所示,本实用新型结构是,包括塑封料封胶体及其集成电路芯片,集成电路芯片6置于塑封料封胶体1内,集成电路芯片6经导线8同集成电路芯片外的管脚4相连,塑封料封胶体1上部中心处开有梯形沟槽5,梯形沟槽内装有成型引线框架9,成型引线框架经其下部的导电材料7同集成电路芯片6相连,梯形沟槽内经散热片底座3装有散热器2。
为了保证使用效果,所说的散热器2至少有一组或二组以上的多组散热片构成,可以做成不同尺寸、形状及面积,以满足不同集成电路芯片及封装形式的散热需求,如沟槽式、平行板式或栅栏式,图1中给出有形沟槽结构;所说的散热器2经散热片底座3呈活动式插装在塑封料封胶体1上部中心处的梯形沟槽5内。
引线框架9采用导热良好的金属材料,如铜,所说的引线框架冲击切成与梯形沟槽5相配合的梯形卡槽式结构,此结构可不但可以使散热结构拆卸方便,还可以增加与散热装置的接触面积,达到高散热性的效果;集成电路芯片6是经过晶圆切割加工后的单个集成电路,集成电路芯片底部与引线框架之间用一种具有同时导热性良好的导电材料连接,例如银胶(EPOXY)或焊锡料等;集成电路芯片表面与引线框架管脚之间用金属导线连接,例如金线(Au Wire)或铜线(Cu Wire)等;将塑封料封胶体1以压模方式(molding)填充于集成电路芯片及引线框架周围,通常采用具有一定导热性的塑封料,例如环氧树脂塑封料(epoxy molding compound,EMC)引线框架9的外表面、梯形沟槽5暴露出塑封体之外,以便集成电路芯片能直接与散热装置相连;引线框架的内表面可以制成阵列网格状的凸块,引线框架的边缘可开设多个小槽,以增加与封胶体的连接密封性;接着对塑封好的产品成型,去除多余的载体部分。
由上述结构可以看出,本实用新型提出的集成电路封装结构可实现方便拆装散热装置,每个散热装置的安装尺寸和散热性能是统一的,具有通用性和模块化的特点,可作为标准件在市场流通,且可重复使用,不同的封装尺寸和散热要求只要加装数量不等的散热装置,从而提高了生产效率及器件的流通性,克服了原半导体器件封装后再加散热装置的复杂性和技术操作的难度,大大提了生产效率,而且本实用新型的集成电路采用倒装形式,散热装置与半导体集成电路芯片接触性好,发热源最近距离的贴近散热装置,故而能大大提高散热效率。相对于传统的集成电路将发热源包封在塑封胶体内的方式,即使不加装散热装置,因发热源透过散热基体与外界接触,其散热效率也远高于传统的集成电路。

Claims (7)

1、一种高散热性的半导体封装器件,包括塑封料封胶体及其集成电路芯片,其特征在于,集成电路芯片(6)置于塑封料封胶体(1)内,集成电路芯片(6)经导线(8)同集成电路芯片外的管脚(4)相连,塑封料封胶体(1)上部中心处开有梯形沟槽(5),梯形沟槽内装有成型引线框架(9),成型引线框架经其下部的导电材料(7)同集成电路芯片(6)相连,梯形沟槽内经散热片底座(3)装有散热器(2)。
2、根据权利要求1所述的高散热性的半导体封装器件,其特征在于,所说的散热器(2)至少有一组或二组以上的多组散热片构成。
3、根据权利要求2所述的高散热性的半导体封装器件,其特征在于,所说的散热器(2)为沟槽式、平行板式或栅栏式。
3、根据权利要求1所述的高散热性的半导体封装器件,其特征在于,所说的引线框架(9)是由导热的金属材料冲击切成与梯形沟槽(5)相配合的梯形卡槽式结构。
4、根据权利要求3所述的高散热性的半导体封装器件,其特征在于,所说的引线框架的内表面成阵列网格状的凸块,或边缘开设多个小槽。
5、根据权利要求1所述的高散热性的半导体封装器件,其特征在于,所说的集成电路芯片(6)在塑封料封胶体(1)内呈倒装式。
6、根据权利要求1所述的高散热性的半导体封装器件,其特征在于,所说的散热器(2)经散热片底座(3)呈活动式插装在塑封料封胶体(1)上部中心处的梯形沟槽(5)内。
CNU2009200886924U 2009-02-26 2009-02-26 高散热性的半导体封装器件 Expired - Fee Related CN201364895Y (zh)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107275295A (zh) * 2017-06-05 2017-10-20 深圳市力生美半导体股份有限公司 一种功率集成器件、封装方法及电源装置
CN109616462A (zh) * 2018-12-04 2019-04-12 四川金湾电子有限责任公司 一种全封闭对称封装引线框架
CN111128980A (zh) * 2019-12-04 2020-05-08 珠海欧比特宇航科技股份有限公司 一种三维立体封装内部器件的散热处理方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107275295A (zh) * 2017-06-05 2017-10-20 深圳市力生美半导体股份有限公司 一种功率集成器件、封装方法及电源装置
CN109616462A (zh) * 2018-12-04 2019-04-12 四川金湾电子有限责任公司 一种全封闭对称封装引线框架
CN111128980A (zh) * 2019-12-04 2020-05-08 珠海欧比特宇航科技股份有限公司 一种三维立体封装内部器件的散热处理方法

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