CN109616462A - 一种全封闭对称封装引线框架 - Google Patents

一种全封闭对称封装引线框架 Download PDF

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CN109616462A
CN109616462A CN201811474687.7A CN201811474687A CN109616462A CN 109616462 A CN109616462 A CN 109616462A CN 201811474687 A CN201811474687 A CN 201811474687A CN 109616462 A CN109616462 A CN 109616462A
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lead frame
chip
plastic packaging
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黄斌
王锋涛
谢锐
宋佳骏
雷洋
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SICHUAN JINWAN ELECTRONIC CO Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49568Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135Double encapsulation or coating and encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/4952Additional leads the additional leads being a bump or a wire
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

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Abstract

本发明提出了封装引线框架式的半导体器件,可有效解决现有半导体器件散热效果差、体积大、成本高、提高使用寿命的问题,其结构是,承载基片向下有矩形凹槽,矩形凹槽内放置有集成电路芯片,承载基片的引线框架外表面与导线引脚保持在同一水平面,引线框架的导线引脚向上弯曲,构成阶梯状结构,集成电路芯片底部与承载基片之间经结合剂粘接在一起,集成电路芯片经金属导线分别接伸出塑封塑料胶体外部的引线框架的导线引脚,集成电路芯片表面有一种导热、绝缘的保护膜,塑封塑料胶体填充于集成电路芯片及引线框架周围,承载基片底面露出塑封塑料胶体,构成全封闭的封装结构。

Description

一种全封闭对称封装引线框架
技术领域
本发明涉及电子技术领域,特别是涉及一种全封闭对称封装引线框架。
背景技术
目前,传统的SOP/SOIC和TSOP系列封装通常采用全包封的封装形式,即用塑封料把集成电路的发热源和承载基片全部包封起来。首先,这种传统的封装散热途径是一方面通过连接导线、管脚传导出去;另一方面通过本体塑封料向周围散热。由于该种封装的管脚体积小、本体塑封料的热传导率又较小且封装体大,所以集成电路工作产生的热能不能实现良好的传导,主要集中在封装体的内部,散热效果不够理想,使用寿命短。据统计,集成电路的失效多数是由热量不能及时有效的传导出去所造成的。随着半导体朝向微型化的发展,集成度越来越高,集成电路中集成的晶体管的数目就越来越多,这样集成电路在运作时,发热量就越来越大,过高的温度会造成集成电路的可靠性降低及性能下降,电路应用中存在不稳定因素,严重时甚至烧毁集成电路。有人提出直接将承载集成电路的散热基片暴露在塑封体外的想法,这样虽可实现良好的传热效果,但因此种封装也容易出现一些问题。比如,封装体由于不是全包封的封装,塑封料和承载集成电路的散热基片之间容易出现间隙、分层现象,导致集成电路在应用时,湿气更容易浸入,湿气渗入是影响其气密性导致失效的重要原因之一。当湿气到达集成电路芯片表面时,会在其表面形成一层导电水膜,并将塑封料本身的Na+、Cl-也随之带入,集成电路在工作时,加速了对芯片表面铝布线的化学腐蚀,最终影响集成电路的寿命。故而这种直接将承载集成电路的散热基片暴露在塑封体外的封装方法虽然导热良好,却一直未能得到实用。也曾有人提出类似的封装体装置,但未解决相关的问题,不具实用效果,也未得到很好的应用。
其次,采用全包封的封装形式,封装的体积较大,不仅占用电路板的空间、不利于向轻、薄型化的发展,还增加的用料的成本。
如何能够合理的减小封装体积、及时有效传导集成电路工作时产生的热量,提高热效率,封装成型是必须考虑的一个不可缺少的环节。
发明内容
为解决上述技术问题,本发明采用的一个技术方案是:
提供一种全封闭对称封装引线框架,承载基片(1)向下有矩形凹槽,矩形凹槽内放置有集成电路芯片(2),承载基片(1)的引线框架外表面与导线引脚(3a、3b)保持在同一水平面,引线框架的导线引脚向上弯曲,构成阶梯状结构,集成电路芯片(2)底部与承载基片(1)之间经结合剂(7)粘接在一起,集成电路芯片(2)经金属导线(4a、4b)分别接伸出塑封塑料胶体(6)外部的引线框架的导线引脚(3a、3b),集成电路芯片表面有一种导热、绝缘的保护膜,塑封塑料胶体填充于集成电路芯片及引线框架周围,承载基片底面露出塑封塑料胶体,构成全封闭的封装结构
优选地,所述的的集成电路芯片(2)表面上封装有导热绝缘弹性材料体(5)。
优选地。所述的结合剂(7)为银胶或焊锡或绝缘硅胶。
优选地,所述的金属导线为银线或铜线。
优选地,芯片在所述的塑封塑料胶体(6)中水平方或垂直方向成对称分布。
优选地,所述的承载基片贴芯片的凹槽的位置设置阻胶槽,防止导电胶的过度溢出,同时,在基岛和引脚的地方设置锁胶孔,增加塑封胶与引线框架的结合面积。。
区别于现有技术的情况,本发明的有益效果是:可有效解决现有半导体器件散热效果差、体积大、成本高、提高使用寿命的问题,其解决的技术方案是,让集成电路的承载基片直接暴露出封装体外,由于发热源直接接触承载基片,集成电路工作产生的热量经由承载基片直接传导到空气中,或经过电路板的散热片传导,故而能够达到良好的散热效果,改进引线框架的结构,改散塑封料与集成电路的承载基片之间气密性,在塑封工序前对芯片表面点上一种导热、绝缘的弹性材料(由高分子材料和一些无机材料组成的复合材料,如硅胶等),再经过烘烤工序后,在芯片表面形成一种有弹性的、密封的保护膜,能有效阻止水气的浸入到芯片表面,也很好的解决了此种封装引起的封装气密性差的问题,其封装由全包封的封装形式改成半包封的封装形式,不仅减小了封装体的体积,还节省了用料的成本,据此,本发明的结构是,承载基片向下有矩形凹槽,矩形凹槽内放置有集成电路芯片,承载基片的引线框架外表面与导线引脚保持在同一水平面,引线框架的导线引脚向上弯曲,构成阶梯状结构,集成电路芯片底部与承载基片之间经结合剂粘接在一起,集成电路芯片经金属导线分别接伸出塑封塑料胶体外部的引线框架的导线引脚,集成电路芯片表面有一种导热、绝缘的保护膜,塑封塑料胶体填充于集成电路芯片及引线框架周围,承载基片底面露出塑封塑料胶体,构成全封闭的封装结构,本发明结构简单,散热效果好,成本低,使用寿命长,经济和社会效益显著。
附图说明
图1本发明结构剖面主视图。
图2是本发明引线框架的阻胶槽结构平面图示意图。
具体实施方式
下面将结合本发明实施例及附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅是本发明的一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
由附图1所示,本发明承载基片1向下有矩形凹槽,矩形凹槽内放置有集成电路芯片2,承载基片1的引线框架外表面与导线引脚3a、3b保持在同一水平面,引线框架的导线引脚向上弯曲,构成阶梯状结构,集成电路芯片2底部与承载基片1之间经结合剂7粘接在一起,集成电路芯片2经金属导线4a、4b分别接伸出塑封塑料胶体6外部的引线框架的导线引脚3a、3b,集成电路芯片表面有一种导热、绝缘的保护膜,塑封塑料胶体填充于集成电路芯片及引线框架周围,承载基片底面露出塑封塑料胶体,构成全封闭的封装结构。
为了保证使用效果,所说的集成电路芯片2表面上封装有导热绝缘弹性材料体5;所说的结合剂7为银胶或焊锡等,考虑到有些集成电路需要与外界绝缘,也可选用导热性能良好但不导电的绝缘硅胶连接;所说的金属导线为金线(AuWire)或铜线(Cu Wire),以达到与外界的电性连接;所说的导热绝缘弹性材料体5为高分子材料和无机材料组成的复合材料,如硅胶等,经烘烤后,在芯片表面形成一种有弹性的、密封的保护膜,能有效阻止水气的浸入到芯片表面,很好的解决了此种封装引起的封装气密性差的问题,因此也具有很好的弹性,能较好的保护芯片,防止某些集成电路在塑封的过程中,由于塑封料、银胶、引线框架、硅晶体等不同材质的热膨胀系数不同,在高温下产生不同的应力所引起的芯片碎裂的问题,也可提高封装制程的良品率;然后将塑封料封胶体以压模方式(molding)填充于集成电路芯片及引线框架周围,将弯脚部分都包封在塑封体内,引线框架的导线引脚露出一部分在塑封体外,以利于电路板的焊接。通常采用具有一定导热性的塑封料,例如环氧树脂塑封料(epoxy moldingcompound,EMC)。引线框架的外表面,即引线框架承载基片的矩形的底面暴露出塑封体之外,塑封成型后类似于SOT 89贴装式的半封装的封装形式,以便集成电路芯片能直接经过引线框架承载基片向外界实现良好的传导;接着对塑封好的产品成型,去除多余的载体部分。
增大塑封胶的结合面积,也是提高可靠性的重要步骤,由附图2所示,所述的承载基片贴芯片的凹槽的位置设置阻胶槽,防止导电胶的过度溢出,同时,在基岛和引脚的地方设置锁胶孔,增加塑封胶与引线框架的结合面积,另外,对于背面露出的散热片产品,往往不能使用凹槽和开孔,可以在基片正面使用凹坑设计,增加表面积,使塑封胶更好的与引线框架结合。
芯片在所述的塑封塑料胶体(6)中水平方或垂直方向成对称分布,都在塑封体内的对称设计,这些结构能够影响到产品不同方向上的塑封料分布,哥哥方向分布一致的产品内应力相互对称,产品的整体应力比较小;各方向不对称的产品应力不对称,产品整体受到的应力比较大,影响产品的可靠性。
通过本发明改进引线框架引线导脚,更好的解决了将承载散热基片暴露出封装体外可能出现的其塑封料环氧树脂与承载散热基片之间结合不良的问题,使其之间达到牢固的结合,从而达到封装成型后密封性能良好。在封装成型后可降低封装体的体积,利于半导体向小、薄型化的发展。
本发明好处在于将集成电路由全封装形式改为半封装的形式后减小了封装体的体积,节省了用料的成本;在满足应用要求的前提下还有效提高了散热效率及提升产品的良品率.因本发明省去了传统封装引脚弯曲成型的工序,还可节省定制成型设备的成本及省去了引脚弯曲成型这道工序。
以上所述仅为本发明的实施例,并非因此限制本发明的专利范围,凡是利用本发明说明书内容所作的等效结构或等效流程变换,或直接或间接运用在其他相关的技术领域,均同理包括在本发明的专利保护范围内。

Claims (7)

1.一种全封闭对称封装引线框架,承载基片(1)向下有矩形凹槽,矩形凹槽内放置有集成电路芯片(2),承载基片(1)的引线框架外表面与导线引脚(3a、3b)保持在同一水平面,引线框架的导线引脚向上弯曲,构成阶梯状结构,集成电路芯片(2)底部与承载基片(1)之间经结合剂(7)粘接在一起,集成电路芯片(2)经金属导线(4a、4b)分别接伸出塑封塑料胶体(6)外部的引线框架的导线引脚(3a、3b),集成电路芯片表面有一种导热、绝缘的保护膜,塑封塑料胶体填充于集成电路芯片及引线框架周围,承载基片底面露出塑封塑料胶体,构成全封闭的封装结构。
2.根据权利要求1所述的全封闭对称封装引线框架,其特征在于:所述的的集成电路芯片(2)表面上封装有导热绝缘弹性材料体(5)。
3.根据权利要求1所述的全封闭对称封装引线框架,其特征在于:所述的结合剂(7)为银胶或焊锡或绝缘硅胶。
4.根据权利要求1所述的全封闭对称封装引线框架,其特征在于:所述的金属导线为银线、铜线或铝线。
5.根据权利要求1所述的全封闭对称封装引线框架,其特征在于:芯片在所述的塑封塑料胶体(6)中水平方或垂直方向成对称分布。
6.根据权利要求1所述的全封闭对称封装引线框架,其特征在于:所述的承载基片(1)贴芯片的凹槽的位置设置阻胶槽,防止导电胶的过度溢出。
7.根据权利要求1所述的全封闭对称封装引线框架,其特征在于:在基岛和引脚的地方设置锁胶孔,增加塑封胶与引线框架的结合面积并在塑封胶进入锁胶孔内形成锁紧柱。
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Publication number Priority date Publication date Assignee Title
CN201364895Y (zh) * 2009-02-26 2009-12-16 晶诚(郑州)科技有限公司 高散热性的半导体封装器件
CN201466021U (zh) * 2009-04-03 2010-05-12 晶诚(郑州)科技有限公司 一种封装引线框架式的半导体器件
CN102891129A (zh) * 2012-08-30 2013-01-23 无锡永阳电子科技有限公司 预塑封引线框架及其封装工艺
CN206806329U (zh) * 2017-05-10 2017-12-26 深圳市三联盛科技股份有限公司 一种半导体封装电路的新型高密度框架结构

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CN201364895Y (zh) * 2009-02-26 2009-12-16 晶诚(郑州)科技有限公司 高散热性的半导体封装器件
CN201466021U (zh) * 2009-04-03 2010-05-12 晶诚(郑州)科技有限公司 一种封装引线框架式的半导体器件
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Application publication date: 20190412