CN201285764Y - Semi-finished product structure for integrated circuit semiconductor device mass production - Google Patents
Semi-finished product structure for integrated circuit semiconductor device mass production Download PDFInfo
- Publication number
- CN201285764Y CN201285764Y CNU2008201462243U CN200820146224U CN201285764Y CN 201285764 Y CN201285764 Y CN 201285764Y CN U2008201462243 U CNU2008201462243 U CN U2008201462243U CN 200820146224 U CN200820146224 U CN 200820146224U CN 201285764 Y CN201285764 Y CN 201285764Y
- Authority
- CN
- China
- Prior art keywords
- lead
- chip
- plate
- electroplax
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model relates to a semi-finished structure for the batch production of integrated circuit semiconductor devices, comprising a conduction forming sheet. The semi-finished structure is characterized in that the conduction forming sheet is provided with a column of punching sheet forming structures along the length direction at intervals and is also provided with lead frames at two sides and a chip electroplate lead plate in the middle along the width direction; bulge connecting plates for juxtaposedly and symmetrically installing two semiconductor chips are connected between the lead frames and the chip electroplate lead plate; a chip locating sheet at one side of the lead frames is in abutting joint with a group of forming electroplates on the lead frames; each locating plate is respectively provided with a semiconductor chip coated with a plastic body; and a lead welding point on each semiconductor chip is respectively correspondingly jointed with a lead on the corresponding position of the conduction forming sheet. The semi-finished structure is favorable for processing and producing integrated circuit semiconductor devices, improves the production efficiency of the integrated circuit semiconductor devices, saves metal materials and lowers the production cost.
Description
Technical field
The utility model relates to the mass-producted semi-finished product structure of a kind of integrated circuit semiconductor apparatus.
Technical background
The manufacturing of integrated circuit semiconductor apparatus generally is to adopt to weld to encapsulate on lead frame to realize.Therefore the design of lead frame and manufacturing are just most important.The manufacture method of lead frame is divided into two kinds substantially, and a kind of is to make lead frame by etching, and another kind is to make lead frame by punching press.It is fast that the method for making lead frame by punching press has process velocity, the advantage that efficient is high, but the existing lead frame of making generally can only process single-row lead-in wire, on it single-row semiconductor device can only be installed, so not only cause the waste of metal material, and increased production cost.
Summary of the invention
The purpose of this utility model provides the mass-producted semi-finished product structure of a kind of integrated circuit semiconductor apparatus, this structure not only helps the processing of integrated circuit semiconductor apparatus, improve the production efficiency of integrated-semiconductor device, and save metal material, reduce production costs.
The technical solution of the utility model is achieved in that it comprises the conduction formed sheet, it is characterized in that: described conduction formed sheet is laid with a row punching molding structure along its length at interval, described punching molding structure broad ways is provided with the lead-in wire frame that is positioned at both sides and is positioned at the chip electroplax lead plate at middle part, be connected with the protruding connecting plate that two semiconductor chips are installed in order to symmetry side by side between described lead-in wire frame and the lead plate, be provided with between two chip spacers on the described protruding connecting plate in order to the gap that disconnects, composing type electroplax on the chip spacer of described lead-in wire frame one side and the lead-in wire frame connects, described chip electroplax lead plate broad ways is provided with two composing type electroplaxs, described moulding electroplax respectively and on the close with it protruding connecting plate chip spacer near chip electroplax lead plate connect, described every composing type electroplax comprises three lead-in wires, its lead-in wire that is positioned at the middle part is connected with the end of location-plate, offer the installing and locating hole on the described lead-in wire frame, be separately installed with the semiconductor chip that is coated with plastic body on described each location-plate, three wire bonds points on described each semiconductor chip respectively with the conduction formed sheet on corresponding connections of three lead-in wires on the relevant position.
The utility model has the advantages that layout designs is reasonable, not only help processing, improve the production efficiency of semiconductor device, and save metal material, reduce production cost.
Description of drawings
Fig. 1 is the front view of the utility model embodiment.
Fig. 2 is the partial schematic diagram of Fig. 1.
Fig. 3 is the A-A cutaway view among Fig. 1.
Embodiment
Below, in conjunction with the accompanying drawings embodiment of the present utility model is further elaborated.
As Fig. 1, Fig. 2 and shown in Figure 3, this lead frame comprises conduction formed sheet (19), it is characterized in that: described conduction formed sheet is laid with a row punching molding structure (18) along its length at interval, described punching molding structure broad ways is provided with the lead-in wire frame (2) that is positioned at both sides, (14) and be positioned at the middle part chip electroplax lead plate (8), be connected with protruding connecting plate (20) and (21) of two semiconductor chips being installed between described lead-in wire frame and the lead plate in order to symmetry side by side, two chip spacers (4) on the described protruding connecting plate, (6), (10), (11) be provided with between in order to the gap (5) that disconnects, composing type electroplax on the chip spacer of described lead-in wire frame one side and the lead-in wire frame connects, being respectively spacer (4) connects with moulding electroplax (3), spacer (11) connects with moulding electroplax (13), described chip electroplax lead plate broad ways is provided with two composing type electroplaxs (7), (9), described moulding electroplax respectively and on the close with it protruding connecting plate near the chip spacer (6) of chip electroplax lead plate, (10) connect, be that moulding electroplax (7) connects with chip spacer (6), moulding electroplax (9) connects with chip spacer (10), described every composing type electroplax comprises three lead-in wires, its lead-in wire (12) that is positioned at the middle part is connected with the end of location-plate, offer installing and locating hole (1) on the described lead-in wire frame, be separately installed with the semiconductor chip (15) that is coated with plastic body (17) on described each location-plate, three the wire bonds points (16) on described each semiconductor chip respectively with the conduction formed sheet on corresponding connections of three lead-in wires on the relevant position.
When making integrated circuit semiconductor apparatus, at first stamp out the integrated circuit semiconductor apparatus sheet material of lead wire frame, and then it is the sheet material of lead wire frame installing and locating is good, the welding integrated circuit (IC) chip then is installed thereon, after integrated circuit (IC) chip has been welded in installation plastic body is encapsulated up, can obtain the mass-producted semi-finished product structure of integrated circuit semiconductor apparatus.At last integrated circuit semiconductor apparatus is cut apart mutually and held back three lead-in wires and can produce in batch integrated circuit semiconductor apparatus.
Claims (1)
1. mass-producted semi-finished product structure of integrated circuit semiconductor apparatus, comprise the conduction formed sheet, it is characterized in that: described conduction formed sheet is laid with a row punching molding structure along its length at interval, described punching molding structure broad ways is provided with the lead-in wire frame that is positioned at both sides and is positioned at the chip electroplax lead plate at middle part, be connected with the protruding connecting plate that two semiconductor chips are installed in order to symmetry side by side between described lead-in wire frame and the lead plate, be provided with between two chip spacers on the described protruding connecting plate in order to the gap that disconnects, composing type electroplax on the chip spacer of described lead-in wire frame one side and the lead-in wire frame connects, described chip electroplax lead plate broad ways is provided with two composing type electroplaxs, described moulding electroplax respectively and on the close with it protruding connecting plate chip spacer near chip electroplax lead plate connect, described every composing type electroplax comprises three lead-in wires, its lead-in wire that is positioned at the middle part is connected with the end of location-plate, offer the installing and locating hole on the described lead-in wire frame, be separately installed with the semiconductor chip that is coated with plastic body on described each location-plate, three wire bonds points on described each semiconductor chip respectively with the conduction formed sheet on corresponding connections of three lead-in wires on the relevant position.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008201462243U CN201285764Y (en) | 2008-11-10 | 2008-11-10 | Semi-finished product structure for integrated circuit semiconductor device mass production |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008201462243U CN201285764Y (en) | 2008-11-10 | 2008-11-10 | Semi-finished product structure for integrated circuit semiconductor device mass production |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201285764Y true CN201285764Y (en) | 2009-08-05 |
Family
ID=40950745
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU2008201462243U Expired - Fee Related CN201285764Y (en) | 2008-11-10 | 2008-11-10 | Semi-finished product structure for integrated circuit semiconductor device mass production |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201285764Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102368485A (en) * | 2011-10-25 | 2012-03-07 | 张轩 | Improved semiconductor element lead framework |
-
2008
- 2008-11-10 CN CNU2008201462243U patent/CN201285764Y/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102368485A (en) * | 2011-10-25 | 2012-03-07 | 张轩 | Improved semiconductor element lead framework |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090805 Termination date: 20171110 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |