CN100424847C - Method for preparing transistor and combined improved structure obtained thereby - Google Patents
Method for preparing transistor and combined improved structure obtained thereby Download PDFInfo
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- CN100424847C CN100424847C CNB2006100264664A CN200610026466A CN100424847C CN 100424847 C CN100424847 C CN 100424847C CN B2006100264664 A CNB2006100264664 A CN B2006100264664A CN 200610026466 A CN200610026466 A CN 200610026466A CN 100424847 C CN100424847 C CN 100424847C
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Abstract
The present invention relates to a method for making transistors and a combined and improved structure obtained by the method. At least one side edge of a metal plate is provided with a wider joint face formed by punching, one pole of each of a plurality of wafers is welded to the joint face of the metal plate, one end of each of a plurality of electric pins is a punched and formed into a bended flat joint part, a part of electric pins can be welded with the other exposed pole of each of the wafers through the joint part, and the other parts of electric pins and the joint part are welded on the joint face of the metal plate through the joint part so that the metal plate and the electric pins can form a composite construction which is easy to assemble. During assembly, the metal plate provided with the wafers is upright arrayed, a part of electric pins are welded on the outward exposed pole of each of the wafers through the joint part, the other part of the electric pins is welded on the joint face of the metal plate through the joint part, and all the electric pins extend upwards. Working space is saved, and test work can be well carried out.
Description
Technical field
The present invention relates to relevant for transistorized preparation method and structure, be meant a kind of combined improved structure that reduces waste material, improves packaging efficiency and increase the transistorized preparation method of production acceptance rate and comply with this method acquisition especially.
Background technology
Present transistorized combining structure, just like Fig. 1, shown in Figure 1A and Figure 1B, its transistor 4 is made up of the side line electric pin 42 that a metallic plate 41 and three with suitable thickness is rectangular sheet, wherein this metallic plate 41 when moulding in the lateral edges conductive connecting pin 411 (having akin width and thickness) in the middle of that stretches out with side conductive connecting pin 42, and be provided with two in addition in a side and be connected protuberance 412 with the edge, and side conductive connecting pin 42 1 ends are provided with the kink 421 of U type bending, and be connected a thin wire 422 that extends in parallel with side conductive connecting pin 42 in this kink 421 other ends, and these thin wire 422 sides are in conjunction with a convergence part 423; During assembling, be welded in two wafers 3 on the linking protuberance 412 of this metallic plate 41 respectively with a utmost point, and make two side conductive connecting pins 42 be welded in another utmost point of wafer 3 respectively with convergence part 423, the transistor basic structure that nationality extends in parallel with the middle conductive connecting pin 411 that forms a metallic plate 41 and two side conductive connecting pins 42.
Yet, the structure of this kind form, it is because this side conductive connecting pin 42 is the edge sides that are welded in metallic plate 41, therefore, when welding processing, this metallic plate 41 must be horizontal and be made progress with the welding position, simultaneously, this side conductive connecting pin 42 also needs horizontal, so that this convergence part 423 and wafer 3 welding, the not only wasteful quantity space of this kind processing modes of emplacement, and be difficult for construction, cause production efficiency not good, and the sheet material 4 of its raw material ' be to be arranging and punch forming as the mode of Fig. 1 D figure, and it is separated into after punch forming as the metallic plate 41 of Fig. 1 C and element such as the side conductive connecting pin 42 of moulding ' wait not again, therefore, in its whole punch forming course of processing, can produce the waste material up to 45%, the utmost point does not meet economic benefit.
In addition just like the transistor combining structure shown in Fig. 2, Fig. 2 A, its transistor 5 is made up of the conductive connecting pin 52 that the metallic plate 51 and three of a tool suitable thickness is rectangular sheet, wherein at least one side of this metallic plate 51 in an edge is provided with two linking protuberances 511, and is provided with convergence part 521 in an end of three conductive connecting pins 52; During assembling, be welded in two wafers 3 on the linking protuberance 511 of this metallic plate 51 respectively with a utmost point, and make three conductive connecting pins 52 be welded in another utmost point of wafer respectively with convergence part 521, directly be welded in this edge side of metallic plate 51 in addition with an end with a conductive connecting pin 52, nationality is to form the transistor basic structure that a metallic plate 51 combines with three road electric pins 52; Yet, the structure of above-mentioned this kind form, it is because this electric pin 52 is the edge sides that are welded in metallic plate 51, therefore, still have wasting space same as described above, be difficult for every shortcomings such as construction and production efficiency is not good, and the sheet material 5 of its raw material ' be to be arranging and punch forming as the mode of Fig. 2 F, Fig. 2 G, and makes it after punch forming, as Fig. 2 D and Fig. 2 E; Be separated into elements such as metallic plate 51 as Fig. 2 B, Fig. 2 C, conductive connecting pin 52 again, therefore, in its whole punch forming course of processing, 25% waste material can take place, still do not meet economic benefit.
Summary of the invention
Technical problem to be solved by this invention mainly is to provide a kind of transistorized preparation method, this preparation method adopts the separation punching press with metallic plate and each conductive connecting pin, and utilize the mode of dense arrangement, can effectively reduce waste material and produce, and then reduce production costs.Metallic plate uprightly can be arranged during its assembling, make each conductive connecting pin be welded in this metallic plate side edge again, therefore its not only simpler and easy facility of weld job, assembling quality percentage height, and can effectively save the required space of assembling operation, the sheet metal elements that can process a greater number simultaneously in unit are is to improve packaging efficiency.
Another technical problem to be solved by this invention is to provide a kind of transistorized combined improved structure.
A kind of transistorized preparation method as first aspect present invention comprises the steps:
1, sheet metal forming
Earlier with mode die-cut needed metallic plate on laths of metal of dense arrangement, then at least on the composition surface of a lateral edges punch forming one broad;
2, with following two kinds of method moulding conductive connecting pins
2.1 elder generation is with the conductive connecting pin blank of mode die-cut needed rectangular sheet on metal band of dense arrangement, then with the conductive connecting pin blank one end punch forming one curved flat convergence part of person;
2.2 earlier with on the rectangular column metal wire rod one by one severing become the conductive connecting pin blank of rectangular column, then with the flat convergence part of conductive connecting pin blank one end punch forming, one bending;
3, wafer welding
One utmost point of wafer is welded on the composition surface of described metallic plate, and make this wafer another is extremely exposed outside;
4, assembling
The metallic plate that wafer is housed is uprightly arranged, then described a part of conductive connecting pin is welded on outwards exposed that of wafer with its convergence part and extremely goes up, and described other parts conductive connecting pin is welded in the composition surface of described metallic plate with the convergence part; All conductive connecting pins all extend upward.
As a kind of transistorized combined improved structure of second aspect present invention, the technological means that it adopted is;
A kind of transistorized combined improved structure comprises:
One metallic plate, at least one lateral edges are the composition surface of a broad through punch forming;
A plurality of wafers are located on the composition surface of this metallic plate with utmost point weldering respectively;
A plurality of conductive connecting pins, an end is the flat convergence part of a bending through punch forming, and makes the partially conductive pin weld another outwards exposed utmost point of this wafer in this convergence part, and is welded in the composition surface of this metallic plate with the convergence part with the conductive connecting pin of other parts.
The present invention is because when assembling, and metallic plate is upright arrangement, and each conductive connecting pin is to be welded in this metallic plate side edge, so the integral solder operation is comparatively easy, can save the required space of assembling operation, is beneficial to promote assembling speed and efficient; Moreover because each conductive connecting pin is to be welded in metal-sheet edges and to extend upward, it also helps the carrying out of test jobs.From the above mentioned as can be known, transistorized combined improved structure of the present invention has the reduction waste material really, promotes the effect of packaging efficiency and increase production acceptance rate.
Description of drawings
Further specify the present invention below in conjunction with the drawings and specific embodiments.
Fig. 1 is existing transistorized structural representation.
Figure 1A is the left view of Fig. 1.
Figure 1B is that the A-A of Fig. 1 cuts open and shows schematic diagram.
Fig. 1 C is the semi-finished product figure after the composition element punching press of Fig. 1 separates.
View when Fig. 1 D is the composition element punching press of Fig. 1.
Fig. 2 is another existing transistorized structural representation.
Fig. 2 A is Fig. 2 left view.
Fig. 2 B is the semi-finished product figure of the metallic plate after the composition element punching press of Fig. 2 separates.
Fig. 2 C is the semi-finished product figure of the conductive connecting pin after the composition element punching press of Fig. 2 separates.
Fig. 2 D arranges schematic diagram when being the metallic plate punch forming of composition element of Fig. 2.
Fig. 2 E arranges schematic diagram when being the conductive connecting pin punch forming of composition element of Fig. 2.
Arrangement schematic diagram when Fig. 2 F is the metallic plate punching press of composition element of Fig. 2.
Arrangement schematic diagram when Fig. 2 G is the conductive connecting pin punching press of composition element of Fig. 2.
Fig. 3 is the structure decomposition map of first embodiment of the invention.
Fig. 3 A is the combination schematic diagram of first embodiment of the invention.
Fig. 3 B is the column conductive connecting pin shaping schematic view of first embodiment of the invention.
Fig. 3 C is that schematic diagram is arranged in the metallic plate punch forming of first embodiment of the invention.
Schematic diagram when Fig. 3 D is the combination operation of first embodiment of the invention.
Fig. 4 is the structure decomposition map of second embodiment of the invention.
Fig. 4 A is the combination schematic diagram of second embodiment of the invention.
Fig. 4 B is the stamping forming semi-finished product schematic diagram of the sheet conductive connecting pin of second embodiment of the invention.
Arrangement schematic diagram when Fig. 4 C is the sheet conductive connecting pin punching press of second embodiment of the invention.
Fig. 4 D is that schematic diagram is arranged in the metallic plate punch forming of second embodiment of the invention.
Schematic diagram when Fig. 4 E is the combination operation of second embodiment of the invention.
Fig. 5 is the combination schematic diagram of third embodiment of the invention.
Among the figure: 1,10,10 ', 41,51 be metallic plate, 11,101,101 ' 412,511 for being connected protuberance, 2 is the sheet conductive connecting pin, 20 is strip sheet column conductive connecting pin, 20 ' be rectangular column conductive connecting pin, 21,201,201 ', 423,521 be the convergence part, 3 is wafer, and 4,5,6 is transistor, and 411 is middle conductive connecting pin, 42 is the side conductive connecting pin, 421 is kink, and 422 is thin wire, 42 ' be the side conductive connecting pin of not moulding, 4 ', 51 ', 52 ' be sheet material, 52 is conductive connecting pin.
Embodiment
For technological means, creation characteristic that the present invention is realized, reach purpose and effect is easy to understand, below in conjunction with specific embodiments and the drawings, further set forth the present invention.
Shown in Fig. 1 to Fig. 1 D and each figure of Fig. 2 to Fig. 2 G, it is various existing transistorized structural representations and the stamping forming arrangement schematic diagrames of element thereof, its main composition with and shortcoming, as previously mentioned, herein not at repeated description.
Fig. 3 is the structure decomposition map of first embodiment of the invention, by its combination schematic diagram and Fig. 3 B with reference to Fig. 3 A, schematic diagram is arranged in each element punch forming of Fig. 3 C, can clearly find out, the present invention mainly comprises: metallic plate 1, parts such as conductive connecting pin 2 and wafer 3, wherein this metallic plate 1 at least one lateral edges is that the composition surface of one-sided vertical bending and broad is provided with two and is connected protuberances 11 through punch forming, and making two wafers 3 be located at two with utmost point weldering respectively is connected on the protuberance 11, three conductive connecting pins 2 are to be the strip sheet column, and the one end is the flat convergence part 21 of a bending through punch forming; During assembling, can be welded in another outwards exposed utmost point of wafer 3 with convergence part 21 by two conductive connecting pins 2, convergence part 21 with a conductive connecting pin 2 directly is welded on the composition surface of 11 of 1 two linkings of this metallic plate protuberances in addition, during above-mentioned again metallic plate 1 moulding is with punching press shown in Fig. 3 C and intensive arrangement mode, 2 of conductive connecting pins be with as Fig. 3 B one rectangular column one by one severing again through being stamped to form, therefore, in the punch forming course of processing of integral body, 2% waste material is only arranged, have very high economic benefit.
Shown in Fig. 3 D.This metallic plate 1 is upright arrangement during assembling, and each conductive connecting pin 2 is to be welded in this metallic plate 1 side edge, so the integral solder operation is comparatively easy, can save the required space of assembling operation, is beneficial to promote assembling speed and efficient; Moreover because each conductive connecting pin 2 is to be welded in metallic plate 1 edge and to extend upward, it also helps the carrying out of test jobs.
Fig. 4 is the structure decomposition map of second embodiment of the invention, arrange schematic diagram by it with reference to the combination schematic diagram of Fig. 4 A and the metallic plate punch forming of Fig. 4 D, can clearly find out, the present invention mainly comprises metallic plate 10, parts such as conductive connecting pin 20 and wafer 3, wherein these metallic plate 10 at least one lateral edges are the composition surface that is to two sides expansion bending through punch forming, be provided with two in this composition surface and be connected protuberance 101, make two wafers 3 respectively utmost point weldering be located at these two and be connected on the protuberances 101, conductive connecting pin 20 is to be rectangular sheet, and the one end is the convergence part 201 of a flat expansion through punch forming; During assembling, two conductive connecting pins 20 are welded in another outwards exposed utmost point of this wafer 3 with convergence part 201, convergence part 201 with a conductive connecting pin 20 directly is welded on the composition surface of 101 of 10 two linkings of this metallic plate protuberances in addition, and for example shown in Fig. 4 D and Fig. 4 C, above-mentioned metallic plate 10 and conductive connecting pin 20 are to separate moulding with intensive arrangement mode, half-finished structure after conductive connecting pin 20 moulding is shown in Fig. 4 B, therefore, in the punch forming course of processing of integral body, 2% waste material is only arranged, and is one to have the processing mode and the structure of high economic benefit.
In the second embodiment of the invention structure, itself since when assembling this metallic plate 10 are upright arrangements, and each conductive connecting pin 20 is to be welded in this metallic plate 10 side edges, so the integral solder operation is comparatively easy, the required space of assembling operation be can save, assembling speed and efficient are beneficial to promote; Moreover because each conductive connecting pin 20 is to be welded in metallic plate 10 edges and to extend upward, it also helps the carrying out of test jobs.
Fig. 5 is second embodiment of the invention combination schematic diagram, can clearly find out, the present invention mainly comprise metallic plate 10 ', conductive connecting pin 20 ' and part such as wafer 3, wherein this metallic plate 10 ' at least one lateral edges is the composition surface that is to two sides expansion bending through punch forming, be provided with in this composition surface two be connected convex surfaces 101 ', make two wafers 3 respectively utmost point weldering be located at these two be connected protuberances 101 ' on, conductive connecting pin 20 ' be to be rectangular column, the one end through punch forming be a flat expansion convergence part 201 '; During assembling, two conductive connecting pins 20 ' with another outwards exposed utmost points of this wafer 3 of convergence part 201 ' be welded in, in addition with a conductive connecting pin 20 ' 10 ' two of this metallic plates in convergence part 201 ' directly be welded in be connected protuberance 101 ' the composition surface on.Metallic plate 10 ' process for stamping with second embodiment, conductive connecting pin 20 ' with first embodiment.Therefore, in the punch forming course of processing of integral body, 2% waste material only being arranged, is one to have the processing mode and the structure of high economic benefit.
In the third embodiment of the invention structure, itself since when assembling this metallic plate 10 ' be upright arrangement, and each conductive connecting pin 20 ' be to be welded in this metallic plate 10 ' side edge, so the integral solder operation is comparatively easy, the required space of assembling operation be can save, assembling speed and efficient are beneficial to promote; Moreover, because each conductive connecting pin 20 ' and be to be welded in metallic plate 10 ' edge and to extend upward, it also helps the carrying out of test jobs.
From the above mentioned as can be known, transistorized combined improved structure of the present invention has the reduction waste material really, promotes the effect of packaging efficiency and increase production acceptance rate, has met novelty of patent and creative important document.
More than show and described basic principle of the present invention and principal character and advantage of the present invention.The technical staff of the industry should understand; the present invention is not restricted to the described embodiments; that describes in the foregoing description and the specification just illustrates principle of the present invention; without departing from the spirit and scope of the present invention; the present invention also has various changes and modifications, and these changes and improvements all fall in the claimed scope of the invention.The claimed scope of the present invention is defined by appending claims and equivalent thereof.
Claims (8)
1. a transistorized preparation method is characterized in that, comprises the steps:
1], sheet metal forming
Earlier with mode die-cut needed metallic plate on laths of metal of dense arrangement, then at least on the composition surface of a lateral edges punch forming one broad;
2], with following two kinds of method moulding conductive connecting pins
2.1] earlier with the conductive connecting pin blank of mode die-cut needed rectangular sheet on metal band of dense arrangement, then with the conductive connecting pin blank one end punch forming one curved flat convergence part of person;
2.2] earlier with on the rectangular column metal wire rod one by one severing become the conductive connecting pin blank of rectangular column, then with the flat convergence part of conductive connecting pin blank one end punch forming, one bending;
3], wafer welding
One utmost point of wafer is welded on the composition surface of described metallic plate, and make this wafer another is extremely exposed outside;
4], assembling
The metallic plate that wafer is housed is uprightly arranged, then described a part of conductive connecting pin is welded on outwards exposed that of wafer with its convergence part and extremely goes up, and described other parts conductive connecting pin is welded in the composition surface of described metallic plate with the convergence part; All conductive connecting pins all extend upward.
2. a transistorized combined improved structure is characterized in that, comprises at least:
One metallic plate, at least one lateral edges are the composition surface of a broad through punch forming;
A plurality of wafers are located on the composition surface of this metallic plate with utmost point weldering respectively;
A plurality of conductive connecting pins, an end is the flat convergence part of a bending through punch forming, and makes the partially conductive pin can weld another outwards exposed utmost point of this wafer in this convergence part, and is welded in the composition surface of this metallic plate with the convergence part with the conductive connecting pin of other parts.
3. transistorized combined improved structure as claimed in claim 2 is characterized in that, is provided with between the composition surface of described metallic plate and a plurality of wafers to be connected protuberance.
4. as claim 2 or 3 described transistorized combined improved structures, it is characterized in that described conductive connecting pin is to be the strip sheet column.
5. as claim 2 or 3 described transistorized combined improved structures, it is characterized in that described conductive connecting pin is to be rectangular sheet.
6. as claim 2 or 3 described transistorized combined improved structures, it is characterized in that described conductive connecting pin is to be rectangular column.
7. as claim 2 or 3 described transistorized combined improved structures, it is characterized in that the composition surface of described metallic plate is to be one-sided vertical bending.
8. as claim 2 or 3 described transistorized combined improved structures, it is characterized in that the composition surface of described metallic plate is to be to two sides expansion bending.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100264664A CN100424847C (en) | 2006-05-11 | 2006-05-11 | Method for preparing transistor and combined improved structure obtained thereby |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100264664A CN100424847C (en) | 2006-05-11 | 2006-05-11 | Method for preparing transistor and combined improved structure obtained thereby |
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| Publication Number | Publication Date |
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| CN1862783A CN1862783A (en) | 2006-11-15 |
| CN100424847C true CN100424847C (en) | 2008-10-08 |
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| CNB2006100264664A Active CN100424847C (en) | 2006-05-11 | 2006-05-11 | Method for preparing transistor and combined improved structure obtained thereby |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106571342B (en) * | 2016-08-15 | 2020-01-17 | 林茂昌 | Combined rectifying element and preparation method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1109218A (en) * | 1993-09-21 | 1995-09-27 | 罗姆股份有限公司 | Electronic units with semiconductor slugs |
| US5877555A (en) * | 1996-12-20 | 1999-03-02 | Ericsson, Inc. | Direct contact die attach |
| CN2370569Y (en) * | 1999-04-06 | 2000-03-22 | 林茂昌 | Diode |
| CN1434507A (en) * | 2002-01-25 | 2003-08-06 | 华瑞股份有限公司 | Wire solder free semiconductor device and package method thereof |
| CN1731576A (en) * | 2004-08-06 | 2006-02-08 | 美丽微半导体股份有限公司 | Power semiconductor composed by duplex-metal and china and its manufacturing method |
| CN2927320Y (en) * | 2006-05-11 | 2007-07-25 | 林茂昌 | Combined improved structure of transistor |
-
2006
- 2006-05-11 CN CNB2006100264664A patent/CN100424847C/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1109218A (en) * | 1993-09-21 | 1995-09-27 | 罗姆股份有限公司 | Electronic units with semiconductor slugs |
| US5877555A (en) * | 1996-12-20 | 1999-03-02 | Ericsson, Inc. | Direct contact die attach |
| CN2370569Y (en) * | 1999-04-06 | 2000-03-22 | 林茂昌 | Diode |
| CN1434507A (en) * | 2002-01-25 | 2003-08-06 | 华瑞股份有限公司 | Wire solder free semiconductor device and package method thereof |
| CN1731576A (en) * | 2004-08-06 | 2006-02-08 | 美丽微半导体股份有限公司 | Power semiconductor composed by duplex-metal and china and its manufacturing method |
| CN2927320Y (en) * | 2006-05-11 | 2007-07-25 | 林茂昌 | Combined improved structure of transistor |
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| Publication number | Publication date |
|---|---|
| CN1862783A (en) | 2006-11-15 |
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Owner name: SHANGHAI JINKE SEMICONDUCTOR + EQUIPMENT CO., LTD. Free format text: FORMER OWNER: LIN MAOCHANG Effective date: 20110705 |
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Free format text: CORRECT: ADDRESS; FROM: 200000 NO. 280, TANGGUANG GARDEN, CHANGXI ROAD, SONGJIANG DISTRICT, SHANGHAI TO: 201108 NO. 135 (AREA B, BUILDING 1), LANE 1421, ZHUANXING ROAD, MINHANG DISTRICT, SHANGHAI |
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Effective date of registration: 20110705 Address after: 201108 Shanghai city Minhang District Zhuan Hing Road 1421 Lane 135 (1 B) Patentee after: Shanghai Jinke Semiconductor & Equipment Co.,Ltd. Address before: 200000 No. 280 garden light, Garden Road, Songjiang District, Shanghai Patentee before: Lin Maochang |