CN201054348Y - 一种芯片框架式封装的芯片载片台 - Google Patents

一种芯片框架式封装的芯片载片台 Download PDF

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CN201054348Y
CN201054348Y CNU200720072247XU CN200720072247U CN201054348Y CN 201054348 Y CN201054348 Y CN 201054348Y CN U200720072247X U CNU200720072247X U CN U200720072247XU CN 200720072247 U CN200720072247 U CN 200720072247U CN 201054348 Y CN201054348 Y CN 201054348Y
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chip
slide holder
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utility
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陈金华
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ASE Assembly & Test (Shanghai) Limited
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WEIYU TECH TEST PACKING Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

本实用新型涉及一种芯片框架式封装的芯片载片台。在封装芯片时，考虑到粘接剂的溢出问题，限制了封装体尺寸的减小，影响了一种框架对不同尺寸芯片的通用性。本实用新型提供一种芯片载片台包括一台面，在其固定芯片的位置周围开设有一圈环形凹槽，为粘接芯片提供了外溢粘接剂的容置空间，可以有效地控制载片台的大小。

Description

一种芯片框架式封装的芯片载片台
技术领域
本实用新型涉及集成电路领域，具体地说，涉及集成电路的芯片的框架式封装技术，尤其涉及其中的芯片载片台。
背景技术
半导体封装在新技术和工艺开发方面取得了稳步的进展，封装尺寸显著缩小，一直在向“芯片尺寸”封装发展。框架式封装因受限于框架本身加工工艺及封装工艺，整个封装体尺寸要大于芯片尺寸数倍。其中因考虑粘接剂的溢出，框架的芯片载片台一般要比芯片尺寸大1毫米，这在很大程度上限制了封装体尺寸的减小，且影响一种框架对不同尺寸芯片的通用性，增加生产线品种更换的频率。对一些载片台上有键合金线要求的设计，因粘接剂溢出大小和形状的不确定性，往往要选用有更大载片台的框架以便预留足够的空间给键合，这种常规的方法，限制了封装尺寸的减小，影响产品的良率，增加了材料和工序成本。
为便于理解，这里参照图1和图2描述一个传统的框架封装的结构和工艺。如图所示，在框架式封装中，包括芯片载片台15、芯片13、内引脚11和金线12等。芯片13通过粘接剂14等材料固定到载片台15上。然后通过金线12将芯片12与内引脚11进行电连接，最后，利用塑封体(图中未示出)，将内引脚11、金线12、芯片13、载片台15等封装成一体，成为一块集成电路。
如图1和图2所示，由于粘接剂14的流动性，在将芯片13粘接到载片台15上时，粘接剂14会有相当部分的溢出于芯片13之外。这种溢出所带来的问题在前面已作了描述。
因此，有必要对这种载片台进行改进。
实用新型内容
因此，本实用新型的目的在于，对传统的载片台进行改进，设计一种新颖的结构，以消除上述粘接剂溢出的现象，从而可以使封装尺寸更小型。
根据上述目的，本实用新型的芯片载片台包括一台面，在其固定芯片的位置周围开设有一圈环形凹槽。
在上述述的芯片载片台中，所述凹槽的截面为U型，也可以采用V型或半圆型。
在上述的芯片载片台中，所述环形凹槽呈方形环状，也可以呈圆形或不规则形状。
在上述的芯片载片台中，所述环形凹槽略大于所述芯片的大小。
由于本实用新型提供的芯片载片台设置了环形凹槽，为粘接芯片提供了外溢粘接剂的容置空间，因此，在将芯片粘接到载片台上后，粘接剂的溢出被控制在环形凹槽形成的区域内，因此，可以有效地控制载片台的大小，进而控制封装后的集成电路的大小。
下面将结合附图详细描述本实用新型实施例，本实用新型的上述和其它目的、结构和优点通过下面对实施例的详细描述将更为明了。
附图说明
图1是传统的框架式封装结构的侧视图；
图2是传统的框架式封装结构的俯视图；
图3是本实用新型的框架式封装结构的侧视图；
图4是本实用新型的框架式封装结构的俯视图。
具体实施方式
如图3和4所示，本实用新型所提供的芯片载片台的封装过程与传统的一样，本实用新型的改进点在于，为了防止背景技术部分所述的粘接剂溢出的现象发生，本实用新型在载片台35上固定芯片33的位置周围开设了一圈环形的凹槽36。
由于该环形凹槽36的存在，在粘接芯片33时外溢的粘接剂34可以流入到该凹槽36中，并被其阻挡。
对于该环形凹槽36的形状，在图3和图4所示的实施例中，凹槽的截面采用U型，也可以采用V型、半圆型等其它形状。环形可以是方形环状，也可以圆形环状，甚至根据需要也可以使用不规则的环形，只要该环形略大于封装的芯片的大小即可。
环形凹槽的加工，可以采用模具冲压或化学蚀刻等方式。

Claims (7)

1.一种芯片载片台包括一台面，其特征在于，在其固定芯片的位置周围开设有一圈环形凹槽。
2.如权利要求1所述的芯片载片台，其特征在于，所述凹槽的截面为U型。
3.如权利要求1所述的芯片载片台，其特征在于，所述凹槽的截面为V型。
4.如权利要求1所述的芯片载片台，其特征在于，所述凹槽的截面为半圆型。
5.如权利要求1至4之一所述的芯片载片台，其特征在于，所述环形凹槽呈方形环状。
6.如权利要求1至4之一所述的芯片载片台，其特征在于，所述环形凹槽呈圆形环状。
7.如权利要求1至4之一所述的芯片载片台，所述环形凹槽略大于所述芯片的大小。
CNU200720072247XU 2007-07-06 2007-07-06 一种芯片框架式封装的芯片载片台 Expired - Fee Related CN201054348Y (zh)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102623371A (zh) * 2012-02-28 2012-08-01 苏州市易德龙电器有限公司 Csp芯片贴装载具及贴装方法
CN106711319A (zh) * 2016-12-23 2017-05-24 无锡市好达电子有限公司 Csp封装的声表面波滤波器芯片隔离槽
CN111277102A (zh) * 2018-12-04 2020-06-12 日本电产三协株式会社 致动器

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102623371A (zh) * 2012-02-28 2012-08-01 苏州市易德龙电器有限公司 Csp芯片贴装载具及贴装方法
CN102623371B (zh) * 2012-02-28 2015-05-27 苏州市易德龙电器有限公司 Csp芯片贴装载具及贴装方法
CN106711319A (zh) * 2016-12-23 2017-05-24 无锡市好达电子有限公司 Csp封装的声表面波滤波器芯片隔离槽
CN111277102A (zh) * 2018-12-04 2020-06-12 日本电产三协株式会社 致动器

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Address after: Jing Shanghai Zhangjiang High Tech Park of Pudong New Area No. 669, zip code: 201203

Patentee after: ASE Assembly & Test (Shanghai) Limited

Address before: Jing Shanghai Zhangjiang High Tech Park of Pudong New Area No. 669, zip code: 201203

Patentee before: Weiyu Tech Test Packing Co., Ltd.

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Owner name: RIYUEGUANG ENCAPSULATION TESTING ( SHANGHAI ) CO.,

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