CN204464270U - 半导体封装体 - Google Patents
半导体封装体 Download PDFInfo
- Publication number
- CN204464270U CN204464270U CN201420836083.3U CN201420836083U CN204464270U CN 204464270 U CN204464270 U CN 204464270U CN 201420836083 U CN201420836083 U CN 201420836083U CN 204464270 U CN204464270 U CN 204464270U
- Authority
- CN
- China
- Prior art keywords
- pin
- chip
- package body
- semiconductor package
- glued membrane
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
Claims (7)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201420836083.3U CN204464270U (zh) | 2014-12-19 | 2014-12-19 | 半导体封装体 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201420836083.3U CN204464270U (zh) | 2014-12-19 | 2014-12-19 | 半导体封装体 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN204464270U true CN204464270U (zh) | 2015-07-08 |
Family
ID=53671118
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201420836083.3U Active CN204464270U (zh) | 2014-12-19 | 2014-12-19 | 半导体封装体 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN204464270U (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104505380A (zh) * | 2014-12-19 | 2015-04-08 | 日月光封装测试(上海)有限公司 | 半导体封装体及其制造方法 |
CN106881826A (zh) * | 2017-02-24 | 2017-06-23 | 日月光封装测试(上海)有限公司 | 封装模具和使用该封装模具的注塑方法 |
-
2014
- 2014-12-19 CN CN201420836083.3U patent/CN204464270U/zh active Active
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104505380A (zh) * | 2014-12-19 | 2015-04-08 | 日月光封装测试(上海)有限公司 | 半导体封装体及其制造方法 |
CN106881826A (zh) * | 2017-02-24 | 2017-06-23 | 日月光封装测试(上海)有限公司 | 封装模具和使用该封装模具的注塑方法 |
CN106881826B (zh) * | 2017-02-24 | 2022-11-11 | 日荣半导体(上海)有限公司 | 封装模具和使用该封装模具的注塑方法 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20170117 Address after: 201201 room T3-100201, No. 5001 East Road, Shanghai, Pudong New Area Patentee after: Advanced integrated circuit manufacturing (Chinese) Co. Ltd. Patentee after: ASE Assembly & Test (Shanghai) Ltd. Address before: Guo Shou Jing Road, Pudong Zhangjiang hi tech park Shanghai city Pudong New Area No. 669 201203 Patentee before: ASE Assembly & Test (Shanghai) Ltd. |
|
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20170401 Address after: 201203 Shanghai city Chinese (Shanghai) free trade zone 669 GuoShouJing Road No. six building Patentee after: ASE Assembly & Test (Shanghai) Limited Address before: 201201 room T3-100201, No. 5001 East Road, Shanghai, Pudong New Area Patentee before: Advanced integrated circuit manufacturing (Chinese) Co. Ltd. Patentee before: ASE Assembly & Test (Shanghai) Limited |