CN204375737U - 利用框架封装重布线再包封的打线封装结构 - Google Patents

利用框架封装重布线再包封的打线封装结构 Download PDF

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CN204375737U
CN204375737U CN201420839374.8U CN201420839374U CN204375737U CN 204375737 U CN204375737 U CN 204375737U CN 201420839374 U CN201420839374 U CN 201420839374U CN 204375737 U CN204375737 U CN 204375737U
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郭小伟
龚臻
于睿
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

本实用新型涉及一种利用框架封装重布线再包封的打线封装结构，它包括基板（1），所述基板（1）背面设置有第一锡球（2），所述基板（1）正面通过第二锡球（4）设置有封装体（3），所述封装体（3）包括基岛（5）和引脚（6），所述基岛（5）正面设置有芯片（7），所述芯片（7）正面与引脚（6）正面之间通过金属线（8）相连接，所述基岛（5）、引脚（6）和芯片（7）周围包封有塑封料（9），所述基岛（5）和引脚（6）背面与塑封料（9）背面齐平，所述封装体（3）和第二锡球（4）周围包封有第二塑封料（10）。本实用新型一种利用框架封装重布线再包封的打线封装结构及其制造方法，它能够利用框架实现芯片的重布线。

Description

利用框架封装重布线再包封的打线封装结构
技术领域
本实用新型涉及一种利用框架封装重布线再包封的打线封装结构，属于集成电路或分立元件封装技术领域。
背景技术
1、常规打线基板封装在IO数较多，2层基板无法满足布线空间时，通常的解决办法是改用4层基板。但相比2层基板，4层基板有工艺复杂、成本高、良率低、设计、制造周期长的缺点。或者是利用4层基板代替良率更低、成本更高的6层基板；
2、一些特殊设计的芯片与常规框架不匹配，无法实现封装，则需要进行芯片的线路重布线。这部分工艺需要在FAB厂完成，普通封装厂无法独立进行，且成本很高，业界产能低。
发明内容
本实用新型的目的在于克服上述不足，提供一种利用框架封装重布线再包封的打线封装结构，它能够利用框架实现芯片的重布线。
本实用新型的目的是这样实现的：一种利用框架封装重布线再包封的打线封装结构，它包括基板，所述基板背面设置有第一锡球，所述基板正面通过第二锡球设置有封装体，所述封装体包括基岛和引脚，所述基岛正面设置有芯片，所述芯片正面与引脚正面之间通过金属线相连接，所述基岛、引脚和芯片周围包封有第一塑封料，所述基岛和引脚背面与第一塑封料背面齐平，所述封装体和第二锡球周围包封有第二塑封料。
与现有技术相比，本实用新型具有以下有益效果：
1、利用框架金属线路，提供RDL（Redistribution Layer）层来实现基板的多层绕线或规避短路的功能，节约基板设计空间，使其用2层基板即达到4层基板的布线效果，不仅可以简化基板制作工艺，提高基板的良率，而且节省基板成本；
2、利用框架封装制程实现线路的RDL制作，使一些特殊设计的芯片利用常规框架亦可以实现封装，可以完成需要在特殊供应商才能提供的重布线工艺；
3、外层包封，可得到更好的可靠性。
附图说明
图1为本实用新型一种利用框架封装重布线再包封的打线封装结构的示意图。
图2~图13为本实用新型一种利用框架封装重布线再包封的打线封装结构制造方法的各工序示意图。
其中：
基板1
第一锡球2
封装体3
第二锡球4
基岛5
引脚6
芯片7
金属线8
第一塑封料9
第二塑封料10。
具体实施方式
参见图1，本实用新型一种利用框架封装重布线再包封的打线封装结构，它包括基板1，所述基板1背面设置有第一锡球2，所述基板1正面通过第二锡球4设置有封装体3，所述封装体3包括基岛5和引脚6，所述基岛5正面设置有芯片7，所述芯片7正面与引脚6正面之间通过金属线8相连接，所述基岛5、引脚6和芯片7周围包封有第一塑封料9，所述基岛5和引脚6背面与第一塑封料9背面齐平，所述封装体3和第二锡球4周围包封有第二塑封料10。
其制作方法如下：
步骤一、参见图2或图3，取一金属框架，框架上层为线路层，下层为支撑层，上层的线路层可提供绕线或短路功能，
步骤二、参见图4，在步骤一的框架上进行装片；
步骤三、参见图5，在已装片的框架上进行打线，如果金属框架的线路端子如图3所示，则需在露出的线路层表面部分涂覆阻焊层（将线路层覆盖绿漆），只留出需要焊锡的开窗（如图13所示），以防止锡膏延线路溢出；如果金属框架线路端子为图2所示的圆型，则不覆盖绿漆，亦能起到防止锡膏延线路溢出的效果；
步骤四、参见图6，将已打线产品进行包封；
步骤五、参见图7，将已包封产品去除框架下层支撑层，露出线路层；
步骤六、参见图8，将整条减薄产品切割成独立的单元；
步骤七、参见图9，将切割的独立单元贴装到基板上；
步骤八、参见图10，整条基板进行包封；
步骤九、参见图11，在基板背面进行植球；
步骤十、参见图12，将已植球的基板冲切得到独立的封装单元。

Claims (1)

1.一种利用框架封装重布线再包封的打线封装结构，其特征在于：它包括基板（1），所述基板（1）背面设置有第一锡球（2），所述基板（1）正面通过第二锡球（4）设置有封装体（3），所述封装体（3）包括基岛（5）和引脚（6），所述基岛（5）正面设置有芯片（7），所述芯片（7）正面与引脚（6）正面之间通过金属线（8）相连接，所述基岛（5）、引脚（6）和芯片（7）周围包封有第一塑封料（9），所述基岛（5）和引脚（6）背面与第一塑封料（9）背面齐平，所述封装体（3）和第二锡球（4）周围包封有第二塑封料（10）。
CN201420839374.8U 2014-12-26 2014-12-26 利用框架封装重布线再包封的打线封装结构 Active CN204375737U (zh)

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