CN204375730U - 一种圆片级封装结构 - Google Patents

一种圆片级封装结构 Download PDF

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Publication number
CN204375730U
CN204375730U CN201420845142.3U CN201420845142U CN204375730U CN 204375730 U CN204375730 U CN 204375730U CN 201420845142 U CN201420845142 U CN 201420845142U CN 204375730 U CN204375730 U CN 204375730U
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lead frame
wafer
salient point
disk
chip
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王亚琴
梁志忠
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

本实用新型涉及一种圆片级封装结构，它包括引线框（1），所述引线框（1）上倒装有芯片（2），所述芯片（2）正面设置有金属凸点（3），所述金属凸点（3）与引线框（1）之间通过锡球（4）相连接，所述引线框（1）、金属凸点（3）和锡球（4）周围包封有塑封料（5），所述引线框（1）背面电镀有金属层（6）。本实用新型一种圆片级封装结构，圆片上的图面设计与引线框的图面完全对应，实现整片圆片倒装于引线框，再进行圆片的切割分离以及封装，实现单颗芯片尺寸等同于引线框单颗Unit的晶圆级封装。

Description

一种圆片级封装结构
技术领域
本实用新型涉及一种圆片级封装结构，属于半导体封装技术领域。
背景技术
现有的圆片级封装，先对圆片进行划片，将完成划片后分离的芯片正面粘贴在载板上，再对载板粘贴芯片的一侧进行塑封，去除载板，露出芯片正面，对芯片正面电极进行Fanout 重布线制作金属线路与产品电性的输出。圆片划片后单颗芯片排列粘贴在载板上进行包封、制作Fanout金属线路，一方面芯片排列对位的效率低，而且分离芯片排列对位容易产生位移偏差，这将造成后续芯片正面Fanout金属线路的偏移；由于圆片Fanout封装在封装厂进行，但是对于封装厂进行Fanout工艺涉及的密间距线路制作，难度比较高，容易出现线路短路、线路剥离的问题，良率偏低。
实用新型内容
本实用新型的目的在于克服上述不足，提供一种圆片级封装结构，圆片上的图面设计与引线框的图面完全对应，实现整片圆片倒装于引线框，再进行圆片的切割分离以及封装，实现单颗芯片尺寸等同于引线框单颗Unit的晶圆级封装。
本实用新型的目的是这样实现的：一种圆片级封装结构，它包括引线框，所述引线框上倒装有芯片，所述芯片正面设置有金属凸点，所述金属凸点与引线框之间通过锡球相连接，所述引线框、金属凸点和锡球周围包封有塑封料，所述引线框背面电镀有金属层。
与现有技术相比，本实用新型具有以下有益效果：
1、芯片重布线制作与封装分别由各自擅长的晶圆FAB厂与封装厂完成，产品良率比较高；
2、引线框单颗Unit尺寸等同于单独的芯片尺寸，不仅最大化地利用了金属引线框，而且可以缩小产品尺寸，提高引线框的利用率，降低材料成本；
3、整片圆片一次倒装完成、大大提高了生产效率，降低了生产成本。
附图说明
图1为本实用新型一种圆片级封装结构的结构示意图。
图2~图11为本实用新型一种圆片级封装结构工艺方法的各工序示意图。
其中：
引线框1
芯片2
金属凸点3
锡球4
塑封料5
金属层6。
具体实施方式
参见图1，本实用新型一种圆片级封装结构，它包括引线框1，所述引线框1上倒装有芯片2，所述芯片2正面设置有金属凸点3，所述金属凸点3与引线框1之间通过锡球4相连接，所述引线框1、金属凸点3和锡球4周围包封有塑封料5，所述引线框1背面电镀有金属层6。
其工艺方法如下：
步骤一、参见图2，取一圆片，圆片正面线路设计完全对应于引线框图面，单颗芯片尺寸等同于封装尺寸；
步骤二、参见图3，在圆片正面电极上制作金属凸点；
步骤三、参见图4，在金属凸点上制作锡球；
步骤四、参见图5，将圆片通过金属凸点上的锡球倒装于引线框，引线框单颗产品尺寸等同于单颗芯片尺寸；
步骤五、参见图6，将完成倒装的圆片与引线框放入回流焊设备进行回流焊；
步骤六、参见图7，对完成回流焊的产品进行包封；
步骤七、参见图8，对完成包封的产品进行引线框背面电镀；
步骤八、参见图9，对完成电镀产品的芯片背面被覆UV膜；
步骤九、参见图10，对完成电镀的产品进行切割，分离单个产品；
步骤十、参见图11，去除芯片背面被覆的UV膜。
所述圆片正面线路可以根据引线框图面进行Fanout设计；所述引线框图面可以根据圆片正面线路进行匹配设计。

Claims (1)

1.一种圆片级封装结构，其特征在于：它包括引线框（1），所述引线框（1）上倒装有芯片（2），所述芯片（2）正面设置有金属凸点（3），所述金属凸点（3）与引线框（1）之间通过锡球（4）相连接，所述引线框（1）、金属凸点（3）和锡球（4）周围包封有塑封料（5），所述引线框（1）背面电镀有金属层（6）。
CN201420845142.3U 2014-12-26 2014-12-26 一种圆片级封装结构 Active CN204375730U (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104538378A (zh) * 2014-12-26 2015-04-22 江苏长电科技股份有限公司 一种圆片级封装结构及其工艺方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104538378A (zh) * 2014-12-26 2015-04-22 江苏长电科技股份有限公司 一种圆片级封装结构及其工艺方法

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