CN104505380A - 半导体封装体及其制造方法 - Google Patents

半导体封装体及其制造方法 Download PDF

Info

Publication number
CN104505380A
CN104505380A CN201410812420.XA CN201410812420A CN104505380A CN 104505380 A CN104505380 A CN 104505380A CN 201410812420 A CN201410812420 A CN 201410812420A CN 104505380 A CN104505380 A CN 104505380A
Authority
CN
China
Prior art keywords
pin
chip
glued membrane
packaging body
coated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410812420.XA
Other languages
English (en)
Inventor
李文显
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ase Assembly & Test (shanghai) Ltd
Original Assignee
Ase Assembly & Test (shanghai) Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ase Assembly & Test (shanghai) Ltd filed Critical Ase Assembly & Test (shanghai) Ltd
Priority to CN201410812420.XA priority Critical patent/CN104505380A/zh
Publication of CN104505380A publication Critical patent/CN104505380A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

本发明是关于半导体封装体及其制造方法。根据本发明的一实施例，一无芯片座型封装体包含若干引脚及芯片。该若干引脚中的至少一引脚具有半蚀刻部分。芯片具有设有集成电路单元的上表面及与该上表面相对的下表面，该下表面贴有非导电胶膜且该胶膜用于将该芯片固定于该若干引脚上。其中该胶膜向下包覆该至少一引脚各侧面，且向下包覆长度大于该至少一引脚的半蚀刻部分厚度的1/4但不超过该引脚底面。本发明的半导体封装体及其制造方法使得胶膜向下包覆引脚的各侧面，可加强引脚的支撑力，降低受外力作用时的影响，从而保证封装产品的质量。

Description

半导体封装体及其制造方法
技术领域
本发明涉及半导体封装技术，特别是半导体封装体及其制造方法。
背景技术
随着电子技术的发展，消费者对电子产品的期待日趋小型化。相应的，半导体封装体的尺寸也需缩减。无芯片底座型封装体即顺应这一需求产生。
对于无芯片底座型封装体而言，芯片直接固定于引脚上。而支撑芯片的引脚部分通常是经过半蚀刻处理的，相应的支撑力变弱。在打线机进行打线作业时，引脚极易发生晃动而导致其上附接的焊垫变形，进而影响产品的质量。对于小尺寸的封装体而言，焊垫的变形甚至可能引起短路，导致产品报废。
因而，现有的半导体封装体及其制造方法需进一步改进。
发明内容
本发明的目的之一在于提供一半导体封装体及其制造方法，其可增加引脚的支撑力而不影响产品的尺寸。
本发明的一实施例提供一无芯片座型封装体，包含若干引脚及芯片。该若干引脚中的至少一引脚具有半蚀刻部分。芯片具有设有集成电路单元的上表面及与该上表面相对的下表面，该下表面贴有非导电胶膜且该胶膜用于将该芯片固定于该若干引脚上，其中该胶膜向下包覆该至少一引脚各侧面，且向下包覆长度大于该至少一引脚的半蚀刻部分厚度的1/4但不超过该引脚底面。
在本发明的一实施例中，该向下包覆长度大于该至少一引脚的半蚀刻部分厚度的1/3。而在本发明的一实施例中，该向下包覆长度大于该至少一引脚的半蚀刻部分厚度的1/2。该胶膜可向上包覆该芯片至少一侧面，且向上包覆长度大于该芯片厚度的1/3但小于该芯片厚度的4/5。该无芯片座型封装体是单边尺寸不大于5mm小尺寸封装体。该若干引脚中每一者的底面附接球形焊垫。该胶膜向下包覆该至少一引脚各侧面是经由粘附操作得到，其中该粘附操作温度为100℃至150℃，压力为1N至5N，时间为300至700ms。
本发明的一实施例还提供了一制造无芯片座型封装体的方法，包含：获取一芯片，该芯片具有设有集成电路单元的上表面及与该上表面相对的下表面，该下表面贴有厚度为40-80um的非导电胶膜；藉由该胶膜将该芯片的下表面粘附至若干引脚上，使得该胶膜向下包覆该若干引脚中的至少一引脚各侧面，该至少一引脚具有半蚀刻部分，且向下包覆长度大于该至少一引脚的半蚀刻部分厚度的1/4但不超过该引脚底面；以及使用导线连接该芯片上的集成电路单元与该若干引脚。
根据本发明的另一实施例，获取该芯片进一步包含将该胶膜贴至包含该芯片在内的晶圆下表面，及以芯片单元为单位切割该晶圆以得到该芯片。
本发明的半导体封装体及其制造方法使得胶膜向下包覆引脚的各侧面，加强引脚的支撑力，降低受外力作用时的影响，从而有效保证封装产品的质量。
附图说明
图1是根据本发明一实施例的半导体封装体的剖面示意图。
图2所示是根据本发明另一实施例的半导体封装体的剖面示意图。
具体实施方式
为更好的理解本发明的精神，以下结合本发明的部分优选实施例对其作进一步说明。
对无芯片座型的封装体而言，如果引脚经过半蚀刻，其对芯片的承托力必然降低。本发明实施例提供的半导体封装体及其制造方法可解决引脚承托力降低所带来的一系列问题，其特别适用单边尺寸不大于5mm小尺寸封装体，如3mm*3mm或3mm*5mm等。
图1是根据本发明一实施例的半导体封装体10的剖面示意图。
如图1所示，该半导体封装体10是一无芯片座型封装体，其包含若干引脚20、芯片30，及遮蔽该引脚20和芯片30的塑封壳体40。尽管在其它实施例中，引脚20中至少一者具有半蚀刻部分22，图1中所有引脚20具有半蚀刻部分22。如本领域技术人员所理解的，“半蚀刻”仅是一种蚀刻处理，并不意味着必须蚀刻一半的厚度。在其它实施例中，未经蚀刻处理的引脚20同样适用。芯片30具有设有集成电路单元(未示出)的上表面32及与该上表面32相对的下表面34，该下表面34贴有非导电胶膜12并藉由该胶膜12将该芯片30固定于该若干引脚20上。芯片30上的集成电路单元藉由导线14与各引脚20连接。各引脚20的底面24可进一步附接焊垫(未图示)，如球形焊垫，从而进一步将芯片20连接至外部电路(未图示)。胶膜12向下包覆至少一引脚20(本实施例中为所有引脚20)各侧面26(仅示出一个侧面)，且向下包覆长度d1大于引脚20的半蚀刻部分22厚度的1/2但不超过该引脚20的底面24。在本发明的另一实施例中，该向下包覆长度d1可大于引脚20的半蚀刻部分22厚度的1/3；而在其它实施例中，该向下包覆长度d1大于该引脚20的半蚀刻部分22厚度的1/4即可。
本发明实施例通过使胶膜12包覆引脚20，引脚20与芯片30之间的咬合能力得以加强。承托芯片30的部分的截面积加大，从而可达到减轻打线机打线带来的晃动,避免发生焊垫，特别是球形焊垫的变形。
本发明一实施例提供了制造无芯片座型封装体10的方法。该方法包含：获取一芯片30，该芯片30具有设有集成电路单元的上表面32及与该上表面32相对的下表面34，该下表面34贴有厚度为40-80um的非导电胶膜12；藉由该胶膜12将该芯片30的下表面34粘附至若干引脚20上，使得该胶膜12向下包覆该若干引脚20中的至少一引脚各侧面，该至少一引脚20具有半蚀刻部分22，且向下包覆长度d1大于该引脚20的半蚀刻部分22厚度的1/4但不超过该引脚20的底面24；以及使用导线14连接该芯片30上的集成电路单元与该若干引脚20。
获取该芯片30可进一步包含将胶膜12贴至包含该芯片30在内的晶圆下表面(未图示)，及以芯片单元为单位切割该晶圆以得到该芯片30。如本领域技术人员所了解的，不同的封装厂使用的胶膜12根据其实际的生产环境不同。故胶膜12并无固定的选择，较佳的，本领域技术人员可选择其所熟悉的可流动性较好的型号。此外，该方法还可包含附接焊垫，如附接球形焊垫至每一引脚20的底面24从而可使得该芯片30与外部电路连接。
根据本发明的一实施例，为使该胶膜12向下包覆引脚20的各侧面26，可选择粘附操作温度为100℃至150℃，压力为1N至5N，时间为300至700ms。
图2所示是根据本发明另一实施例的半导体封装体10的剖面示意图。
类似的，如图2所示，该半导体封装体10是一无芯片座型封装体，其包含若干引脚20、芯片30，及遮蔽该引脚20和芯片30的塑封壳体40。胶膜12向下包覆引脚20各侧面26(仅示出一个侧面)，且向下包覆长度d1大于引脚20的半蚀刻部分22厚度的1/3但不超过该引脚20的底面24。同时，在本实施例中，胶膜12可向上包覆该芯片30的至少一侧面36，且向上包覆长度d2大于该芯片30厚度的1/3但小于该芯片30厚度的4/5。
本发明的技术内容及技术特点已揭示如上，然而熟悉本领域的技术人员仍可能基于本发明的教示及揭示而作种种不背离本发明精神的替换及修饰。因此，本发明的保护范围应不限于实施例所揭示的内容，而应包括各种不背离本发明的替换及修饰，并为本专利申请权利要求书所涵盖。

Claims (14)

1.一种无芯片座型封装体，包含：
若干引脚，该若干引脚中的至少一引脚具有半蚀刻部分；及
芯片，具有设有集成电路单元的上表面及与该上表面相对的下表面，该下表面贴有非导电胶膜且该胶膜用于将该芯片固定于该若干引脚上；
其中该胶膜向下包覆该至少一引脚各侧面，且向下包覆长度大于该至少一引脚的半蚀刻部分厚度的1/4但不超过该引脚底面。
2.如权利要求1所述的无芯片座型封装体，其中该向下包覆长度大于该至少一引脚的半蚀刻部分厚度的1/3。
3.如权利要求1所述的无芯片座型封装体，其中该向下包覆长度大于该至少一引脚的半蚀刻部分厚度的1/2。
4.如权利要求1所述的无芯片座型封装体，其中该胶膜向上包覆该芯片至少一侧面且向上包覆长度大于该芯片厚度的1/3但小于该芯片厚度的4/5。
5.如权利要求1所述的无芯片座型封装体，其是单边尺寸不大于5mm的小尺寸封装体。
6.如权利要求1所述的无芯片座型封装体，其中该若干引脚中每一者的底面附接球形焊垫。
7.如权利要求1所述的无芯片座型封装体，其中该胶膜向下包覆该至少一引脚各侧面是经由粘附操作得到，其中该粘附操作温度为100℃至150℃，压力为1N至5N，时间为300至700ms。
8.一种制造无芯片座型封装体的方法，包含：
获取一芯片，该芯片具有设有集成电路单元的上表面及与该上表面相对的下表面，该下表面贴有厚度为40-80um的非导电胶膜；
藉由该胶膜将该芯片的下表面粘附至若干引脚上，使得该胶膜向下包覆该若干引脚中的至少一引脚各侧面，该至少一引脚具有半蚀刻部分，且向下包覆长度大于该至少一引脚的半蚀刻部分厚度的1/4但不超过该引脚底面；及
使用导线连接该芯片上的集成电路单元与该若干引脚。
9.如权利要求8所述的方法，其中获取该芯片进一步包含：
将该胶膜贴至包含该芯片在内的晶圆下表面；及
以芯片单元为单位切割该晶圆以得到该芯片。
10.如权利要求8所述的方法，其中该向下包覆长度大于该至少一引脚的半蚀刻部分厚度的1/3。
11.如权利要求8所述的方法，其中该向下包覆长度大于该至少一引脚的半蚀刻部分厚度的1/2。
12.如权利要求8所述的方法，其中将该芯片的下表面粘附至若干引脚上使得该胶膜向上包覆该芯片至少一侧面，且向上包覆长度大于该芯片厚度的1/3但小于该芯片厚度的4/5。
13.如权利要求8所述的方法，其进一步包含附接球形焊垫至该若干引脚中每一者的底面。
14.如权利要求8所述的方法，其中该粘附操作温度为100℃至150℃，压力为1N至5N，时间为300至700ms。
CN201410812420.XA 2014-12-19 2014-12-19 半导体封装体及其制造方法 Pending CN104505380A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410812420.XA CN104505380A (zh) 2014-12-19 2014-12-19 半导体封装体及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410812420.XA CN104505380A (zh) 2014-12-19 2014-12-19 半导体封装体及其制造方法

Publications (1)

Publication Number Publication Date
CN104505380A true CN104505380A (zh) 2015-04-08

Family

ID=52947117

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410812420.XA Pending CN104505380A (zh) 2014-12-19 2014-12-19 半导体封装体及其制造方法

Country Status (1)

Country Link
CN (1) CN104505380A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106373935A (zh) * 2016-10-20 2017-02-01 江苏长电科技股份有限公司 一种无基岛框架封装工艺及其封装结构
WO2019227918A1 (zh) * 2018-05-31 2019-12-05 江苏长电科技股份有限公司 一种无基岛框架封装结构及其工艺方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5969412A (en) * 1997-04-09 1999-10-19 Nec Corporation Tape-fixed leadframe
JP2003086453A (ja) * 2001-09-13 2003-03-20 Denso Corp 電気素子の実装構造
CN101533817A (zh) * 2008-03-10 2009-09-16 力成科技股份有限公司 引脚在承座上的半导体封装构造
CN201752004U (zh) * 2010-04-30 2011-02-23 江苏长电科技股份有限公司 芯片直接置放封装结构
CN204464270U (zh) * 2014-12-19 2015-07-08 日月光封装测试(上海)有限公司 半导体封装体

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5969412A (en) * 1997-04-09 1999-10-19 Nec Corporation Tape-fixed leadframe
JP2003086453A (ja) * 2001-09-13 2003-03-20 Denso Corp 電気素子の実装構造
CN101533817A (zh) * 2008-03-10 2009-09-16 力成科技股份有限公司 引脚在承座上的半导体封装构造
CN201752004U (zh) * 2010-04-30 2011-02-23 江苏长电科技股份有限公司 芯片直接置放封装结构
CN204464270U (zh) * 2014-12-19 2015-07-08 日月光封装测试(上海)有限公司 半导体封装体

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106373935A (zh) * 2016-10-20 2017-02-01 江苏长电科技股份有限公司 一种无基岛框架封装工艺及其封装结构
CN106373935B (zh) * 2016-10-20 2019-04-16 江苏长电科技股份有限公司 一种无基岛框架封装工艺及其封装结构
WO2019227918A1 (zh) * 2018-05-31 2019-12-05 江苏长电科技股份有限公司 一种无基岛框架封装结构及其工艺方法

Similar Documents

Publication Publication Date Title
CN101086972B (zh) 用于mlp高密度包装的多排暴露引线
CN109390310B (zh) 图案化的引线框架
CN105161431A (zh) 晶圆级芯片封装方法
US9768091B2 (en) Method of forming an electronic package and structure
CN204464270U (zh) 半导体封装体
CN104505380A (zh) 半导体封装体及其制造方法
US8785254B2 (en) Method of manufacturing high-capacity semiconductor package
US20130048351A1 (en) Electronic package structure and method for manufacturing same
CN105161465A (zh) 晶圆级芯片封装方法
US20100096711A1 (en) Microelectromechanical system microphone package
US8299587B2 (en) Lead frame package structure for side-by-side disposed chips
US20140134805A1 (en) Method of fabricating a semiconductor package
US9748163B1 (en) Die support for enlarging die size
US8736038B2 (en) Lead frame having increased stability due to reinforced die pads and packaging method using such lead frame
US9905498B2 (en) Electronic package
CN204550044U (zh) 含有传感器单元的模组的封装结构
CN204375739U (zh) 利用框架封装重布线的倒装pip封装结构
US10433042B2 (en) MEMS multi-module assembly, manufacturing method and electronics apparatus
TW201937664A (zh) 壓力感測器封裝結構
CN104347570B (zh) 无引线型半导体封装及其组装方法
US9337240B1 (en) Integrated circuit package with a universal lead frame
CN103130173B (zh) 用于mems芯片封装的无小岛引线框、引线框阵列及封装结构
CN104465600A (zh) 利用框架封装重布线再包封的打线封装结构及其制造方法
US9177834B2 (en) Power bar design for lead frame-based packages
CN207320101U (zh) Qsop 24l的半导体封装框架

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20150408