CN1977206B - 具有薄膜晶体管的干涉式调制器 - Google Patents
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Abstract
本发明揭示一种调制器，其具有一带有一第一表面的透明衬底。至少一个干涉式调制器元件驻留于所述第一表面上。至少一个电连接至所述元件的薄膜电路组件驻留于所述表面上。当多于一个干涉式元件驻留于所述第一表面上时，有至少一个薄膜电路组件对应于驻留于所述第一表面上的每一元件。
Description
技术领域
本申请涉及一种干涉式调制器，尤其涉及一种具有半导体电路组件的干涉式调制器。
背景技术
干涉式调制器(例如iMoDTM)通过控制射到调制器正面上的光的自干涉来调制光。这些类型的调制器通常采用一具有至少一个可移动或可偏转的壁的空腔。所述可偏转的壁移动经过平行于所述空腔的前壁的平面，所述空腔的前壁是射到调制器正面上的光所首先遇到的壁。当通常至少部分地由金属构成且具有高度反射性的所述可移动的壁朝所述空腔的正面移动时，会在所述空腔内发射光的自干涉，且所述正面与所述可移动的壁之间的变化的距离会影响在所述正面处射出所述空腔的光的颜色。由于干涉式调制器通常是直视式装置，因而所述正面通常是显现由观察者所看到的图像的表面。
所述可移动的壁响应于一由寻址电路所产生的激励信号而移动，所述寻址电路将所述信号发送至可移动元件。所述寻址电路通常制造于离开可移动元件阵列的芯片外。这部分地是因为在上面制造干涉式调制器的衬底是透明的，例如为塑料或玻璃。
可在透明衬底上制造薄膜晶体管。将薄膜晶体管与干涉式调制器相集成可提供一具有扩展的功能度的干涉式调制器。
发明内容
根据本发明的一个方面，一种显示器，其包括：一具有一第一表面的透明衬底；
一位于所述第一表面上的干涉式调制器元件阵列；及至少一个薄膜晶体管，其电连接至所述干涉式调制器元件中的每一者并与所述阵列集成在同一衬底上，其中所述薄膜晶体管定位于所述衬底的所述第一表面上，其中所述薄膜晶体管和所述干涉式调制器元件进一步满足下列情况(a)至(e)中的至少一种：(a)所述干涉式调制元件的光学堆叠含有与所述薄膜晶体管的栅电极相同的材料，(b)所述干涉式调制器元件的光学堆叠电介质含有与所述薄膜晶体管的栅极氧化物相同的材料，(c)所述干涉式调制元件的牺牲层含有与所述薄膜晶体管中的非晶硅层和参杂的非晶硅层相同的非晶硅和参杂的非晶硅，(d)所述干涉式调制元件的一个或多个支柱含有与所述薄膜晶体管的平坦化层相同的聚合物材料，及(e)所述干涉式调制元件的镜元件含有与所述薄膜晶体管的源极及漏极电极相同的材料。
根据本发明的再一个方面，一种制造一具有至少一个薄膜晶体管的干涉式调制器的方法，所述方法包括：在一透明衬底上制造至少一干涉式调制器；及在所述透明衬底上制造至少一个薄膜晶体管，其中所述制造所述干涉式调制器及所述薄膜晶体管包括一个或多个如下步骤：同时形成所述薄膜晶体管的一栅电极及所述干涉式调制器的一光学堆叠，沉积氧化物以同时为所述薄膜晶体管形成一栅极氧化物及为所述干涉式调制器形成一光学堆叠电介质，沉积非晶硅和参杂的非晶硅以形成所述干涉式调制器的一牺牲层及同时形成所述薄膜晶体管中的的非晶硅层和参杂的非晶硅层，沉积聚合物材料以形成所述干涉式调制器的支柱及同时形成所述薄膜晶体管的一平坦化层，及
同时形成所述干涉式调制器的一镜元件及所述薄膜晶体管的源极及漏极电极。。
附图说明
通过参照附图来阅读本揭示内容，可最好地理解本发明，在附图中：
图1a及1b显示一干涉式调制器的若干实施例；
图2显示一具有集成的薄膜晶体管的干涉式调制器的侧视图；
图3a-31显示一种用于薄膜晶体管的集成工艺流程的实施例；
图4a-4h显示一种用于具有薄膜晶体管的干涉式调制器的集成工艺流程的实施例；
图5a-5r显示一种具有低温多晶硅顶部栅极晶体管的干涉式调制器的集成工艺流程的实施例；
图6a-6n显示一种用于具有低温多晶硅底部栅极晶体管的干涉式调制器的集成工艺流程的实施例；
图7显示一种用于与制造多晶硅顶部栅极晶体管串联地制造干涉式调制器的方法的一实施例的流程图。
具体实施方式
图1a及1b显示一干涉式调制器的替代实施例。如前面所述，干涉式调制器采用一具有至少一个可移动或可偏转的壁的空腔。当通常至少部分地由金属构成的图1a所示的壁20朝所述空腔的一正面12移动时，会发生干涉，此种干涉会影响在所述正面处观看到的光的颜色。由于iMOD是直视式装置，因而所述正面通常是显现由观察者所看到的图像的表面。正面12可具有一形成光学堆叠14(也称作第一镜)的材料堆叠。可移动的壁20偏离开所述光学堆叠一个支柱16。
在图1a所示的实施例中，可移动元件20是一覆盖支柱16的薄膜的一部分，其中所述薄膜18的一部分略微高起。在图1b所示的一替代实施例中，可移动元件24通过也形成支柱的支撑件22悬置于空腔上方。本文所述发明的各实施例适用于这两种架构、以及通过薄膜工艺制成的诸多其他类型的MEMS装置。
在单色显示器(例如一在黑色与白色之间切换的显示器)中，一个iMoD元件可对应于一个像素。在彩色显示器中，三个iMoD元件可构成每一像素-红色、绿色及蓝色各一个。分别控制各单独iMoD元件来产生所需的像素反射率。通常，对空腔的可移动的壁或元件施加一电压，从而使其被静电吸引至所述正面，此又会影响观察者所看到的像素的颜色。
寻址电路及驱动器决定对哪些元件施加电压以使其朝所述正面移动。寻址电路将一般包括晶体管，其中一个或多个晶体管对应于调制器阵列上的每一元件。当前，所述晶体管制造于离开调制器元件的芯片外。然而，通过使用薄膜晶体管，便可在衬底上制造所述晶体管。此外，由于大多数MEMS装置均可自薄膜制成，因而可将薄膜晶体管的制造与MEMS装置的制造相集成。
图2显示一干涉式调制器装置的一侧视图。所述调制器具有一制造于透明衬底10上的可分别控制的可移动元件(例如30)阵列。作为封装工艺的一部分，使用一背板28来封闭所述调制器阵列。如在此处可看到，透明衬底10具有数个部分可用于制造将不会被观察者26所看到的薄膜晶体管。
区域32a及32d位于调制器“以外”，其中用语“以外”是指位于背板或其他封装结构的与调制器阵列相对置的侧上。这将通常不是晶体管将处于的位置。因背板安装工艺而损坏调制器元件与晶体管之间的晶体管引线的可能性可能非常大。通常，将直接毗邻调制器阵列制造晶体管，其中直接毗邻意味着其制造于衬底的不用于调制器阵列、但位于背板内侧的部分上。区域32b及32c即为此种部署的实例。此外，晶体管可与调制器元件并排地制造，例如靠近每一元件一个晶体管。
如前面所述，可使用与MEMS装置(例如上面所述的干涉式调制器)的制造非常兼容的材料及工艺来制造薄膜晶体管。参见图2，可以看到，调制器阵列制造于透明衬底10的“背面”上。在图3a-31所示的工艺流程图中，显示透明衬底相对于图2所示视图“上下倒置”。调制器的制造将看起来处于衬底的顶部上。
此外，可与调制器制造工艺流程相集成地或者与其相串联地制造其他半导体薄膜电路组件。除晶体管以外的组件的一实例将是薄膜二极管。尽管下文的各实例论述薄膜晶体管的制造，然而也可使用任何薄膜半导体电路组件。
在图3a中，已在衬底40上沉积了一第一材料层42。该材料可用于形成薄膜晶体管的栅极及干涉式调制器的光学堆叠(如在图4a中所示)。所述第一材料可以是多晶硅。在图3b中，已对所述第一材料进行了图案化及蚀刻，以移除所述材料中的所选部分，例如44。此可形成晶体管的栅极。调制器的光学堆叠可如在图4b中所示形成为若干行。
在图3c中，已沉积了一第一氧化物层46。所述氧化物所用的材料可为用于形成图4c中所示调制器的光学堆叠电介质及晶体管的栅极氧化物的同一材料。可针对调制器的运行及与用于形成所述元件的进一步工艺的兼容性二者来调整对所述氧化物的材料的选择。例如，如果所用氧化物材料在光学上透明，则将适用于在调制器中的应用。
在图3d中，为调制器沉积一第一牺牲层48。在调制器其他部分的形成完成之后，将对该层进行蚀刻以形成空腔。图4d中的牺牲层48可实际上由两个层形成：一第一非晶硅层及随后的一经掺杂的非晶硅层，如在图3d中的48a及48b处所示。将非晶硅及经掺杂的非晶硅用作牺牲层是与对调制器的处理兼容的，并用于对薄膜晶体管的处理中。如上文所述，介电层46可经选择以与进一步的处理兼容，因此电介质/氧化物将选择成与非晶硅兼容。
在图3e中，对所述牺牲层进行图案化及蚀刻，以形成类似于如图4e中所示调制器元件中的50的支柱孔。由于在一实施例中所述牺牲层是非晶硅及经掺杂的非晶硅，因而此也作为晶体管形成工艺的一部分来图案化及蚀刻。支柱可由用于将薄膜晶体管结构平坦化的同一材料(例如图3f及4f中的聚合物52)形成。当前，调制器的支柱是由一金属层(图1a中的薄膜的金属或者图1b中的支撑件的金属)制成。然而，并不要求必须对支柱使用金属。通过使用一聚合物，能够与支柱的形成并行地实施晶体管的平坦化。一聚合物的实例是聚酰亚胺。
图3g看起来类似于图3f，因为通过侧视图看不到所执行的处理。在图3g中，将对平坦化层进行图案化及蚀刻以清理晶体管引线。这为要在图3h及4g中通过沉积金属层54制成金属触点扫清了道路。该金属形成图1a中的镜层20及图1b中的镜元件24。其还将形成晶体管的源极及漏极电极。必须注意，在图1a所示的架构中，金属层54是镜层及机械层-移动的层。而在图1b所示的架构中，层54是镜层且支柱层52是机械层。
对金属层54进行图案化及蚀刻，以形成源极及漏极电极以及形成图3i中的调制器的各个可移动元件。通过对所述金属层实施蚀刻工艺来形成间隙56。然后，使用所述源极/漏极电极金属作为一遮罩在图3j中再次蚀刻经掺杂的非晶硅层48a，以形成晶体管的沟道。该晶体管工艺或其余晶体管工艺对于调制器元件而言不存在等价的工艺。
用于形成晶体管的最后两个工艺显示于图3k及31中。在3k中，为晶体管沉积一钝化层60。在图31中，蚀刻所述钝化层以清理引线，例如通过在62处所示的间隙。在一实施例中，所述钝化层为氧化物。随后，晶体管处理便告结束，随即实施一释放蚀刻以形成图4h中的间隙57，从而使调制器元件能够自由地移动。通过此种方式，与薄膜干涉式空间光调制器的制造几乎并行地完成薄膜晶体管的制造。
对于图1b所示的调制器架构而言，将沉积一第二牺牲层，随后是一第二金属层。在形成薄膜晶体管之后，可实施对金属层的图案化及蚀刻以形成支撑支柱并随后实施对牺牲层的蚀刻以释放所述元件。在2003年8月19日提出申请的第10/644,312号美国专利申请案“可分离的调制器架构(Separable Modulator Architecture)”中更清楚地阐述了图1b所示架构的处理的改动方式。制造薄膜晶体管的工艺与这两种干涉式调制器阵列架构中任一种的制造兼容。
此外，在顶部栅极或底部栅极结构中，晶体管的制造可使用低温多晶硅。这些工艺将通过图1b所示的可分离的调制器架构来展示，但也可适用于图1a所示的架构。对调制器架构的选择与对所用晶体管的类型的选择无关，且所述集成工艺可适用于不同的可能的组合。
图5a-5r显示一种与用于干涉式调制器的工艺流程相集成的用于顶部栅极、低温多晶硅晶体管的工艺流程的实施例。图中将晶体管流程与调制器流程并排地显示于看起来为衬底的同一部分的区域上，但这只是为了便于展示起见而非旨在隐含着调制器阵列相对于晶体管阵列的任一特定位置。
在图5a中，在衬底40上沉积光学堆叠42。在图5b中，沉积、遮罩及蚀刻氧化物46及第一牺牲层48的第一部分48a。在图5c中，沉积第二部分48b。在图5d中，对这些层进行图案化及蚀刻以形成调制器以及晶体管的基本结构。图中右侧的结构是用于显示这两个工艺流程的集成的一干涉式调制器阵列中的一个元件。
在图5d中，沉积晶体管的n沟道遮罩以便能够进行n沟道掺杂。然后沉积一栅极氧化物60。然后对所述氧化物进行图案化及蚀刻以获得图5f中所得到的结构。在图5g中，已对所述牺牲层的第二部分48b进行了图案化及蚀刻，以形成调制器元件的下伏结构。在图5h中，在66处沉积栅极钼。对其进行图案化及蚀刻以形成例如图5i中的66a及66b的结构。
在图5j中，使用一遮罩来掺杂p源极及漏极，从而得到经掺杂的p源极及漏极68。在图5k中对n源极及漏极70实施一类似的工艺。在图51中，在所述晶体管结构上沉积层间电介质72。此时未对调制器元件实施相当的工艺。
在图5m中，沉积镜层54以由晶体管用作源极/漏极触点、及由调制器用作镜54a、54b及54c。此会重新开始所述集成处理流程。在图5n中，沉积一将为镜支撑件提供支撑的牺牲层74，并随后将其移除以允许镜元件自由地移动。牺牲层74将不由任何晶体管工艺使用，但晶体管可能需要所述材料保持与晶体管流程中的工艺兼容。
在图5o中，已自晶体管区域中清除了牺牲层74并已对牺牲层74进行了图案化及蚀刻以形成支柱孔50a、50b及50c。在图5p中沉积一平坦化层76。然后，在图5q中沉积机械层52，以为所述镜形成支撑支柱。然后在图5r中，晶体管区域接纳一钝化层78。
图6a-6n显示类似于图5a-5r的工艺，但是针对一底部栅极、低温多晶硅晶体管阵列来显示。为易于比较，在这两种工艺中，类似的结构及层使用相同的参考编号。在图6a中，在衬底40上沉积调制器的光学堆叠42。在图6b中沉积、图案化及蚀刻第一牺牲层48的这两个部分，以形成调制器的下伏结构。在图6c中，沉积、图案化及蚀刻栅极金属80，并随后形成氧化层82。在图6d中沉积栅极氧化物60。
在图6e中，沉积、图案化及蚀刻镜层54，以形成镜，形成调制器元件、镜54a、54b及54c。在图6f中，沉积牺牲层74，且在图6g中，形成支柱孔(例如50a)，其中在晶体管结构上留有牺牲层74的岛状物。在图6h中，沉积一个氧化物层并随后对其进行图案化及蚀刻，以形成晶体管结构的氧化物覆盖层84。
在图6i中，如70所示掺杂n型源极及漏极，并在图6j中如68所示掺杂p型源极及漏极。在图6k中，沉积层间电介质72。在图61中沉积平坦化层76。在图6m中，沉积机械层52，机械层52在支柱孔中形成支柱，并提供晶体管的源极/漏极触点金属。在图6n中，沉积钝化层78。
通过此种方式，可提供一种将晶体管与干涉式调制器的制造集成于一个衬底上的工艺流程。该集成的工艺流程节约处理步骤，从而降低成本，并能够对装置进行更快的处理。对装置进行更快的处理会增加装置的产量，从而也降低成本。
此外，可能希望串联地实施处理。在一实例中，首先实施电路组件处理，然后实施对干涉式调制器的处理。在另一实例中，则切换所述顺序。在图7中显示首先制造电路组件的一实例。该工艺始于透明衬底。
在90处，通过沉积、图案化及蚀刻电极层、光学层及电介质来形成光学堆叠。在92处，使用一保护性氧化物层覆盖所形成的结构。此时，所述工艺流程集中于薄膜电路组件的制造。在该特定实例中，所述组件为一顶部栅极、低温多晶硅晶体管。
在94处沉积非晶硅，在96处进行p沟道掺杂，并在98处进行n沟道掺杂。在100处沉积栅极氧化物及金属，并在102处遮罩及蚀刻所述栅极。必须注意，为易于论述起见，已扼要叙述了几种工艺。关于这些工艺的更详细的说明可参见参照图3-6所作的论述。在104处形成p型源极及漏极，并在106处形成对应的n型源极及漏极。
在108处沉积层间电介质，并在110处对触点进行遮罩及蚀刻以清理所述触点。在120处沉积及蚀刻源极及漏极金属。在122处进行电路组件的钝化，及在124处清除触点上的钝化材料。此时，电路组件处理已基本结束。在126处，清除先前所沉积的保护性氧化物并在128处开始干涉式调制器制造工艺。
如上面所述，这只是一串联式工艺流程的一个实例。可首先制造调制器并随后制造电路组件。将对所述电路组件进行一类似的流程，无论所述电路组件是顶部或底部栅极、低温多晶硅型还是其他类型的薄膜晶体管或薄膜二极管。
因此，虽然本文至此已阐述了一种用于在与干涉式调制器相同的衬底上制造薄膜电路组件的方法及设备的一特定实施例，但除非在下文权利要求书中提及外，并不打算将这些特定说明视为对本发明范围的限制。
Claims (9)
1.一种显示器，其包括：
一具有一第一表面的透明衬底；
一位于所述第一表面上的干涉式调制器元件阵列；及
至少一个薄膜晶体管，其电连接至所述干涉式调制器元件中的每一者并与所述阵列集成在同一衬底上，其中所述薄膜晶体管定位于所述衬底的所述第一表面上，
其中所述薄膜晶体管和所述干涉式调制器元件进一步满足下列情况(a)至(e)中的至少一种：
(a)所述干涉式调制元件的光学堆叠含有与所述薄膜晶体管的栅电极相同的材料，
(b)所述干涉式调制器元件的光学堆叠电介质含有与所述薄膜晶体管的栅极氧化物相同的材料，
(c)所述干涉式调制元件的牺牲层含有与所述薄膜晶体管中的非晶硅层和参杂的非晶硅层相同的非晶硅和参杂的非晶硅，
(d)所述干涉式调制元件的一个或多个支柱含有与所述薄膜晶体管的平坦化层相同的聚合物材料，及
(e)所述干涉式调制元件的镜元件含有与所述薄膜晶体管的源极及漏极电极相同的材料。
2.如权利要求1所述的显示器，其包括对应于每一元件的至少一个薄膜晶体管。
3.如权利要求1所述的显示器，其中每一薄膜晶体管均直接毗邻一对应的干涉式调制器元件定位。
4.一种制造一具有至少一个薄膜晶体管的干涉式调制器的方法，所述方法包括：
在一透明衬底上制造至少一干涉式调制器；及
在所述透明衬底上制造至少一个薄膜晶体管，其中所述制造所述干涉式调制器及所述薄膜晶体管包括一个或多个如下步骤：
同时形成所述薄膜晶体管的一栅电极及所述干涉式调制器的一光学堆叠，沉积氧化物以同时为所述薄膜晶体管形成一栅极氧化物及为所述干涉式调制器形成一光学堆叠电介质，
沉积非晶硅和参杂的非晶硅以形成所述干涉式调制器的一牺牲层及同时形成所述薄膜晶体管中的的非晶硅层和参杂的非晶硅层，
沉积聚合物材料以形成所述干涉式调制器的支柱及同时形成所述薄膜晶体管的一平坦化层，及
同时形成所述干涉式调制器的一镜元件及所述薄膜晶体管的源极及漏极电极。
5.如权利要求4所述的方法，其中薄膜晶体管包括使用低温多晶硅来制造薄膜晶体管。
6.如权利要求4所述的方法，其中使用低温多晶硅来制造晶体管包括制造顶部栅极低温多晶硅晶体管。
7.如权利要求4所述的方法，其中使用低温多晶硅来制造晶体管包括制造底部栅极低温多晶硅晶体管。
8.如权利要求4所述的方法，其中在所述薄膜晶体管的所述制造之后实施所述干涉式调制器的所述制造。
9.如权利要求4所述的方法，其中在所述薄膜晶体管的所述制造之前实施所述干涉式调制器的所述制造。
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| JP特开2002-62493A 2002.02.28 |
| JP特开2004-4553A 2004.01.08 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20060001942A1 (en) | 2006-01-05 |
| US7601571B2 (en) | 2009-10-13 |
| WO2006014247A2 (en) | 2006-02-09 |
| CN1977206A (zh) | 2007-06-06 |
| US7256922B2 (en) | 2007-08-14 |
| EP1774393A2 (en) | 2007-04-18 |
| TWI279919B (en) | 2007-04-21 |
| TW200612562A (en) | 2006-04-16 |
| EP2533094A1 (en) | 2012-12-12 |
| WO2006014247A3 (en) | 2006-05-18 |
| BRPI0512810A (pt) | 2008-04-08 |
| AU2005270186A1 (en) | 2006-02-09 |
| US20070275491A1 (en) | 2007-11-29 |
| IL179983A0 (en) | 2007-05-15 |
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