CN1976023B - 输出匹配晶体管 - Google Patents

输出匹配晶体管 Download PDF

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CN1976023B
CN1976023B CN2006101363991A CN200610136399A CN1976023B CN 1976023 B CN1976023 B CN 1976023B CN 2006101363991 A CN2006101363991 A CN 2006101363991A CN 200610136399 A CN200610136399 A CN 200610136399A CN 1976023 B CN1976023 B CN 1976023B
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coupled
transistor
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CN1976023A (zh
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C·布莱尔
N·V·迪克西特
T·W·莫勒
T·法姆
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Infineon Technologies AG
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Abstract

一种功率晶体管，具有形成在其上的电极的半导体，其中电极包括至少一个具有输入和输出端的晶体管；第一输出阻塞电容器，具有电耦合到半导体交指型晶体管输出端子的第一端子和电耦合到地的第二端子；及第二输出阻塞电容器，包括电耦合到第一输出阻塞电容器第一端子的第一端子和电耦合到地的第二端子。一种用于放大信号的方法，该方法具有：在半导体上形成功率晶体管，其中功率晶体管包括多个交指型晶体管；分流来自多个交指型晶体管的输出信号；以及双分流来自多个交指型晶体管的输出信号，其中分流和双分流在功率晶体管的管芯平面上产生第一和第二谐波终结。

Description

输出匹配晶体管
技术领域
本发明一般而言涉及射频(RF)功率晶体管器件的领域，尤其涉及内部匹配的射频功率晶体管。
背景技术
通常知道采用射频功率晶体管器件作为无线通信设备中的信号放大器。随着无线通信设备需求的增加，用于无线网络的工作频率也增加。目前的工作频率恰好处于千兆赫范围内。
各个晶体管元件中的自然变化使得大批量制造射频功率晶体管出现问题。晶体管器件随着输入电容、增益和相位转移自然地改变。在预期的工作频率和电压的范围内对特定晶体管器件进行预先表征。然后利用相似材料制造器件以试图使这些器件在该表征的范围内工作。由于晶体管和其他各种元件在同样工作频率和电压上发生变化，限制了在大规模制造基础上成功调试晶体管器件的能力。
射频功率晶体管器件通常具有多个在硅管芯(silicon die)上形成的电极，每个电极具有多个交指型晶体管。每个电极的各个晶体管连接到各自的用于每个电极的公共输入(栅极)和输出(漏极)引线。如已知的，该管芯通常由在金属(源极)衬底顶部的共晶管芯连接工艺来进行连接。该衬底被设置在金属凸缘，该金属凸缘起散热片和接地参考的作用。输入(栅极)和输出(漏极)引线框被连接到凸缘的侧面。引线框与金属(源极)衬底电绝缘并且由多条线在硅管芯上分别连接到电极输入和输出端(即接合到各自端子和引线框)。
在高工作频率下，输入和输出电极端阻抗与所希望的工作频率范围相匹配是非常重要的。在低频(即：＜1GHz)的高功率设备中，支路匹配元件的所需要的电感可以使线变长和变短来处理工作功率。在某些情况下，解决这个问题的现有方法可以解决输入的和输出网络之间过量的串音，但引起不稳定。
可采用的现有技术关于射频功率晶体管器件的例子在美国专利号6,177,834和美国专利号6,614,308中进行了说明，在此引入作为参照。
发明内容
本发明通常涉及射频功率晶体管器件领域，更具体而言涉及具有与管芯平面上的第二谐波终结相匹配的内部输出的射频功率晶体管。
根据本发明的一个方面，提供一种功率晶体管，该功率晶体管包含：半导体，该半导体具有形成在其上的电极，其中该电极包括至少一个包括输入和输出端子的晶体管，其中半导体的输出端子通过承载输出电感的第一多个输出导体耦合到输出匹配网络；第一输出阻塞电容器，其包括通过承载输出电感的第二多个输出导体耦合到半导体输出端子的第一端子以及耦合到地的第二端子；以及第二输出阻塞电容器，其包括通过承载输出电感的第三多个输出导体耦合到第一输出阻塞电容器第一端子的第一端子以及耦合到地的第二端子。
本发明的另一方面，提供一种宽带射频(射频)信号放大器，具有：连接到具有参考地的基架表面的功率晶体管，其中功率晶体管包括至少一个电连接到射频输入和射频输出偏置输入和偏置输出的晶体管器件，其中至少一个晶体管器件包括栅极调谐网络和双支路漏极调谐网络；射频输入路径，电连接到至少一个晶体管器件，输入匹配网络被配置成以输入阻抗将输入信号耦合到晶体管输入，并且栅极偏置网络被配置成将偏置晶体管的输入偏置到输入工作点；以及电连接到晶体管输出的射频输出路径，输出匹配网络被配置成以输出阻抗上将各自分量输出信号耦合到晶体管输出，并且漏极偏置网络被配置成把晶体管输出偏置到输出工作点。
根据本发明另一方面，提供一种功率晶体管，具有：在其上形成电极的半导体，其中电极包括多个交指型晶体管，每个交指型晶体管具有输入和输出端子；第一输出阻塞电容器，具有电耦合到半导体的交指型晶体管输出端子的第一端子和电耦合到地的第二端子；以及第二输出阻塞电容器，具有耦合到第一输出阻塞电容器第一端子的第一端子和电耦合到地的第二端子。
本发明的再一方面提供一种用于放大信号的方法，该方法具有下面的步骤：在半导体上形成功率晶体管，其中功率晶体管包括多个交指型晶体管；分流来自多个交指型晶体管的输出信号；以及双分流来自多个交指型晶体管的输出信号，其中分流和双分流在功率晶体管的管芯平面上产生第一和第二谐波终结。
通过阅读下面优选实施例的描述，本发明的目的、特征和优点对于本领域的技术人员来说是显而易见的。
附图说明
通过阅读下面参考相关附图的非限定的实施例描述，可以更好的理解本发明，其中多个附图中的各附图相同元件表述相同的参考标记，并且下面简要的进行描述。
图1是示意性说明本发明一个实施例的宽带放大器放大器部分的物理设置和接合线连接的俯视图。
图2是说明本发明的LDMOS射频功率晶体管器件的实施例的俯视图。
图3是图2所示的范例的LDMOS射频功率晶体管器件的示意性电路图。
图4是说明对于本发明第一实施例的第一和第二谐波频率的曲线图。
然而，应当指出附图仅说明是本发明某些实施例的一些方面，并且因此并不构成对其范围的限定，本发明包括相等有效附加或等同实施例。
具体实施方式
本发明一般而言涉及射频功率晶体管器件的领域，并且涉及内部匹配射频功率晶体管。
图1说明根据本发明一个方面的放大器部分1。放大器部分1具有印刷电路板(PCB)7和功率晶体管基架(pedestal)11。PCB 7具有用于接收射频输入信号的射频功率输入(未示出)和用于输出放大的射频输出信号的射频功率输出(未示出)。基架11具有连接其上的功率晶体管4。功率晶体管4放大射频输入信号的相位分量信号从而将来自射频功率输入的功率电压升到如本领域已知的射频功率输出。基架11提供对功率晶体管4的电路组件的支承；提供用于传送公共电流的高电导率；并且提供用于制冷的高热导率。基架11可以由在放大器部分1的工作频率上的热传导率和电导率为最佳性质的铜和铜合金制成。基架11可以由本领域技术人员所知的具有相似电和热特性的任何材料制成。
功率晶体管4具有场效应晶体管，该场效应晶体管具有形成在连接基架11的半导体管芯上的输入(栅极)、输出(漏极)和公共元件(源极)端子。在一个实施例中，该晶体管为横向扩散金属氧化物半导体(LDMOS)晶体管，具有直接形成在管芯的底部上并直接连接到基架11的源极端子。PCB7为多层模块，如这里用作参照的由Logothetis等人的美国专利号6,099,677所教导的。
图1说明本发明射频功率晶体管4的放大器部分1的物理设置和接合线连接的俯视图。放大器部分1包括输入匹配网络2、栅极偏置网络3、功率晶体管4、输出匹配网络5、和漏极偏置网络6。当所说明的放大器部分1由六个放大器部分实现时，可替换的实施例可以根据这里的教导和描述的发明方面具有两个或多个放大器部分来实现。
在放大器部分1中，输入匹配网络2接收射频功率以形成来自分离器相应输出的标明为“RF馈入”的分量输入信号来激励功率晶体管4中的晶体管器件10的栅极。栅极偏置网络3接收来自输入偏置源极标明为“栅极偏置馈入”的直流偏置电压，这用于设置晶体管器件10的工作点。功率晶体管4接收来自输入匹配网络2的功率射频输入分量信号并且接收来自栅极偏置网络3的直流偏置。功率晶体管4产生驱动输出匹配网络5的高功率射频输出分量信号。标明为“RF驱动”的组合器接收来自输出匹配网络5的高功率射频输出分量信号。标明为“漏极偏置馈入”用于高功率输出分量信号的功率源极由漏极偏置网络6所提供。
功率晶体管4具有在公共源极结构中耦合到基架11的射频功率晶体管器件10。晶体管器件10是其上形成有电极的半导体，其中电极具有每个具有输入和输出端子的多个交指型晶体管。功率晶体管4具有输入12、输出13、栅极调谐网络14、和漏极调谐网络15。功率晶体管输入12接收来自输入匹配网络2的射频输入功率来激励功率晶体管4。由功率晶体管4产生的射频输出功率传送到功率晶体管输出13的输出匹配网络5。偏置输入8传送来自栅极偏置网络3的信号到输入匹配网络2。偏置输出9传送来自输出匹配网络5的信号到漏极偏置网络6。
用来连接功率晶体管4到PCB 7的外部节点，并用来相互连接基架11上设置的功率晶体管4元件的接合线，具有在典型工作频率上不能忽略的自感。多个阻抗变化和调谐网络有效地耦合来自射频馈入的射频功率到晶体管器件10的栅极。相似的阻抗变化和调谐网络也有效地耦合来自晶体管器件10的漏极的射频功率到射频驱动。栅极调谐网络14补偿接合线电感器和与晶体管器件10的栅极相关的输入电容，漏极调谐网络15补偿接合线电感器和与晶体管器件10的漏极相关的电容。
尽管输入12和输出13被描述成最小长度的单个导体，本领域的技术人员应当意识到每个导体路径可以以一个或多个接合线来形成。选择并行使用的接合线数量和接合线的长度，允许传导路径的电感被控制和调节到合适的值。图2说明利用输入12和输出13的多个接合线的本发明的技术方案。
根据本方面的实施例，宽带射频信号放大器具有连接到基架11表面的多个功率晶体管器件10。信号放大器也具有射频输入路径，该射频输入路径具有被配置成将射频输入信号分离为多个分量输入信号的分离器。分离器、输入匹配网络2和栅极偏置网络3至少部分地被实施在印刷电路板上。信号放大器也具有射频输出路径，该射频输出路径具有被配置成将在晶体管输出上接收的分量输出信号和射频输出信号组合的组合器。组合器、输出匹配网络5和漏极偏置网络6至少部分地被实施在印刷电路板上。其他实施例中，信号放大器具有射频输入和射频输出路径12和13，其具有被实施在印刷电路板上的各自输入和输出参考接地架。根据具体的应用，基架11和印刷电路板被配置成使输入和输出参考接地架接近基架表面。
参考图2，说明了本发明的LDMOS射频功率晶体管10的实施例的俯视图。功率晶体管4通过输入(14和相关的接合线电感)和经由(15和相关接合线电感)位于输入引线2和输出引线5之间。在本发明实施例中，输入和输出匹配网络2和5通过陶瓷衬底17连接但与导体16电隔离。一对晶体管器件(半导体管芯)10连接到导体(地)16。通过超声擦洗和/或温度上的热处理连接晶体管器件10。每个晶体管器件10具有多个交指型电极，其中每个电极具有输入(栅极)端子和输出(漏极)端子。
栅极调谐网络14包括“T-网络”。在本发明的一个实施例中，T-网络转换基准频率上晶体管输入端的阻抗“观察(looking)”到适合匹配晶体管器件的的低阻抗。具有T-网络的晶体管器件10的输入匹配由输入匹配电容19实施。通过临近输入匹配网络2的导体16定位输入匹配电容19。输入匹配电容19具有通过第一组输入接合线21耦合到输入匹配网络2的第一组端子20。第一组输入接合线21将一端接合到输入匹配网络2而将另一端接合到输入匹配电容19的第一组端子20。输入匹配电容19具有耦合到导体(地)16的第二端子(未示出)。第二组输入接合线22耦合输入匹配电容19的第一组端子20到晶体管器件10的交指型电极的各自输入端子。特别地，第二组输入接合线22将一端接合到第一组端子20而将另一端接合到晶体管器件10的各自交指型电极输入端子。从而通过选择输入匹配电容19的所希望电容值以及第一和第二组输入接合线21和22的电感来实施晶体管器件10的输入匹配。
具有漏极调谐网络15的发明实施例包括双分流网络和串联电感。串联电感是连接晶体管器件10的交指型电极输出端子的漏极到输出匹配网络5的第一组输出接合线23的结果。双分流网络包括耦合到第一输出匹配电容26的第二组输出接合线24。第一输出匹配电容26具有耦合到导体(地)16的第二终端(未示出)。第二组输出接合线24也耦合到晶体管器件10的交指型电极漏极端。双分流网络也包括耦合到第二输出匹配电容27的第三组输出接合线25。第二输出匹配电容27具有耦合到导体(地)16的第二端子(未示出)。第三组输出接合线25也耦合到第一输出匹配电容26。在本发明某些实施例中，第一输出匹配电容26和第二输出匹配电容27的值是频率电感的并且对于工作方面的谐波终结是重要的。第一输出匹配电容26提供频率(f)的高阻抗和2f的低阻抗。第二输出匹配电容27提供f的低阻抗(直流阻塞)。
尽管所说明的功率晶体管10以额定分量值实施，本领域的技术人员应当理解为了得到用于来自功率晶体管10的最佳性能的调谐，元件19到27的值可以被调节。
如上所述，本发明实施例具有包括双分流网络的漏极调谐网络。第二回路允许900MHz装置来建立足够数量的电感来允许在管芯平面上的分流匹配。该方法缩短漏极线到其通常长度的1/2。本发明的双分流网络也提供管芯平面上的第二谐波终结。参考图4，所示的曲线图说明了由双分流网络产生的第一和第二谐波频率。第一谐波(900MHz)通过第二组输出接合线24、第三组输出接合线25、和第二输出匹配电容27(图3所示)匹配。第二谐波(2GHz-需要调节上限(cap)值)通过第二组输出接合线24和第一输出匹配电容26(图3所示)进行匹配。从而，根据本发明的其他实施例，在管芯平面上添加第二谐波终结(来自使用作为阻塞上限的管芯的接合回路)。在工作频率上，双回路调谐允许调谐网络中任何耗散的功率在2个回路之间被共享。这有效地加速允许的射频耗散。
因此，完全可以修改本发明的技术方案以实施并获得这里所提及的主题和优点及其固有的优点。而本领域的技术人员应当能够进行各种改变，这种改变涵盖在由所附权利要求所限定的本发明的构思范围内。

Claims (5)

1.一种输出匹配晶体管(4)，包括：
半导体(10)，具有形成在该半导体上的电极，其中所述电极拥有至少一个包含输入端子和输出端子的晶体管，其中所述半导体的输出端子通过承载输出电感的第一多个输出导体(23)耦合到输出匹配网络(5)，其中所述半导体是LDMOS晶体管器件(10)；
第一输出阻塞电容器(26)，包括通过承载输出电感的第二多个输出导体(24)耦合到所述半导体的输出端子的第一端子和耦合到地(16)的第二端子；
第二输出阻塞电容器(27)，包括通过承载输出电感的第三多个输出导体(25)耦合到第一输出阻塞电容器(26)的第一端子的第一端子和耦合到地(16)的第二端子，
其中所述第一输出阻塞电容器(26)的第一端子依次通过承载输出电感的第二多个输出导体(24)、承载输出电感的第一多个输出导体(23)耦合到所述输出匹配网络(5)，第二输出阻塞电容器(27)的第一端子依次通过承载输出电感的第三多个输出导体(25)、承载输出电感的第二多个输出导体(24)、承载输出电感的第一多个输出导体(23)耦合到所述输出匹配网络(5)，其中第一谐波频率通过第二多个输出导体(24)、第三多个输出导体(25)和第二输出阻塞电容器(27)进行匹配，并且其中第二谐波频率通过第二多个输出导体(24)和第一输出阻塞电容器(26)进行匹配，使得第二谐波终结被添加到管芯平面。
2.如权利要求1所述的输出匹配晶体管(4)，进一步包括输入匹配电容器(19)，该输入匹配电容器(19)包括通过承载输入电感的第一多个输入导体(21)而耦合到输入匹配网络(2)的第一端子以及耦合到地(16)的第二端子，其中所述第一端子还通过承载输入电感的第二多个输入导体(22)耦合到半导体的输入端子。
3.如权利要求2所述的输出匹配晶体管(4)，其中输入匹配电容器(19)位于输入匹配网络(2)和电极之间。
4.如权利要求1所述的输出匹配晶体管(4)，其中第一输出阻塞电容器(26)提供频率f处的高阻抗和频率2f处的低阻抗。
5.如权利要求4所述的输出匹配晶体管(4)，其中第二输出阻塞电容器(27)提供频率f处的低阻抗。
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CN1976023A (zh) 2007-06-06
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US7372334B2 (en) 2008-05-13

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