CN1976020A - 互连结构及其形成方法 - Google Patents

互连结构及其形成方法 Download PDF

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CN1976020A
CN1976020A CNA2006101485185A CN200610148518A CN1976020A CN 1976020 A CN1976020 A CN 1976020A CN A2006101485185 A CNA2006101485185 A CN A2006101485185A CN 200610148518 A CN200610148518 A CN 200610148518A CN 1976020 A CN1976020 A CN 1976020A
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layer
interconnection structure
cap layer
conductor
atom
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H·L·巴克斯
刘晃
J·T·凯利赫尔
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GlobalFoundries Singapore Pte Ltd
International Business Machines Corp
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International Business Machines Corp
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Abstract

一种后段制程(BEOL)互连结构和一种形成互连结构的方法。所述互连结构包括嵌入介电层的导体例如铜，以及在所述导体上用作扩散阻挡层的低k介电帽层。公开了一种形成BEOL互连结构的方法，其中所述帽层是利用等离子体增强化学气相沉积(PECVD)沉积而成，且由Si、C、H和N构成。所述互连结构提供了改善的氧扩散阻抗和改善的阻挡质量，允许膜厚度的减小。

Description

互连结构及其形成方法
技术领域
本发明一般涉及高速半导体微处理器、专用集成电路(ASIC)和其它高速集成电路器件的制造。更具体地说，本发明涉及包括具有低k介电常数并由非晶的氢化碳化硅(Si-C-H)构成的帽层的半导体器件的先进制造方法。
背景技术
超大规模集成(VLSI)或特大规模集成(ULSI)电路中的金属互连典型地由包括金属布线构图层的互连结构构成。典型的集成电路(IC)器件包括三至十五个金属布线层。随着特征尺寸减小以及器件密度增加，预期互连层的数量会增加。
这些互连结构的材料和布局优选地选择为使信号传输延迟最小，从而使总的电路速度最大。互连结构中的信号传输延迟表示为各金属布线层的RC时间常数，其中R为布线电阻，C为多层互连结构中的选定信号线(即导体)与周围导体之间的有效电容。通过降低布线材料的电阻可以减小RC时间常数。因为其相对低的电阻，Cu因此是IC互连的优选材料。通过采用具有较低介电常数k的介电材料，也可以减小RC时间常数。
D.Edelstein等在Proceedings of the IEEE 2004 InternationalInterconnect Technology Conference，pp.214-216的“Reliability，Yield，and Performance of a 90nm SOI/Cu/SiCOH”中说明了包括低k介电材料和铜互连的现有技术状态的双镶嵌互连结构。图1示出了一种采用低k介电材料和铜互连的典型互连结构。该互连结构包括下衬底10，其可包括逻辑电路元件，例如晶体管。介电层12，公知为层间电介质(ILD)，覆盖在衬底10上方。在衬底10与ILD层12之间可以设置附着促进剂层11。在ILD层12上可以设置硬掩模层13。该硬掩模层13典型地由氮化硅构成，但也可以由氧化硅或碳化硅构成。硬掩模层13可以用作构图层以辅助稍后对ILD层12的蚀刻，而且它还可以用作在随后的化学机械抛光(CMP)步骤以去除多余的金属期间的抛光停止层。
在ILD层12中嵌入至少一个导体15。导体15在先进互连结构中典型地为铜，但是可以可选地为铝或其它导电材料。可以在ILD层12与导体15之间设置扩散阻挡衬里(liner)14。扩散阻挡衬里14典型地由钽、钛、钨或这些金属的氮化物构成。通常通过化学机械抛光(CMP)步骤，使导体15的顶面与硬掩模层13的顶面共面。在导体15和硬掩模层13上设置同样典型地由氮化硅构成的帽层16。该帽层也可以由碳化硅或二氧化硅构成。帽层16用作扩散阻挡层，以防止来自导体15的铜扩散到周围的介电材料中。帽层16还在进一步处理期间保护铜不被氧化。
第一互连级由图1中示出的互连结构中的附着促进剂层11、ILD层12、硬掩模层13、扩散阻挡衬里14、导体15和帽层16限定。在图1中第一互连级上方示出的第二互连级包括附着促进剂层17、ILD层18、硬掩模层19、扩散阻挡衬里20、导体21和帽层22。各互连级中的互连线以及连接级和级的过孔可以通过本领域的技术人员已知的常规单或双镶嵌工艺形成。
第二互连级的形成从沉积附着促进剂层17开始。接着，在附着促进剂层17上沉积ILD层18。可以通过等离子体增强化学气相沉积(PECVD)或通过旋涂来沉积ILD材料18。PECVD ILD的实例包括掺氟和掺碳的氧化硅，旋涂ILD的实例是聚合热固性材料，例如SiLKTM。接着，在ILD上沉积硬掩模层19。选定的ILD和集成方案指示是否采用附着和硬掩模层以及这些层由哪类材料构成。然后采用常规光刻和蚀刻工艺，构图硬掩模层19、ILD层18、附着促进剂层17和帽层16，以形成至少一个沟槽和过孔。沟槽和过孔典型地衬有扩散阻挡衬里20。然后，在常规双镶嵌工艺中，用例如铜的金属填充沟槽和过孔，以形成导体21。通过CMP工艺去除多余的金属。最后，在铜导体21和硬掩模层19上沉积帽层22。
重点在于帽层材料，氮化硅具有约6至7的相对高的介电常数。已知在其中存在较高k的帽/扩散阻挡膜例如氮化硅的铜区域中，在铜导体之间存在边缘电场。当具有约2至3的低介电常数的材料用于ILD时，通过采用较高k的氮化硅帽/扩散阻挡层，金属导体的有效电容增加，导致总的互连速度降低。有效电容还可以通过采用较高k的氮化硅抛光停止层而增加。
帽层16和22的可选材料是非晶的氢化碳化硅材料(SixCyHz)，一个实例是已知为BlokTM的材料。(一种由硅、碳和氢构成的非晶膜，从Applied Materials，Inc.可得)。SixCyHz的介电常数小于5，比氮化硅的介电常数低。因此，在采用SixCyHz作为帽层的互连结构中，金属导体的有效电容降低，总的互连速度增加。
然而，已经发现，Si-C-H不是良好的氧阻挡，这导致相对高的电迁移速率。这些高电迁移速率不利地影响IC芯片的可靠性。
作为另一选择，可以将氮添加到Si-C-H材料，形成非晶氮化氢化碳化硅材料(Si-C-N-H)。尽管在特定环境下，Si-C-N-H是优于Si-C-H的氧阻挡，但Si-C-N-H仍然不具有希望的氮化硅所拥有的氧阻挡特性。而且，在大多数常规半导体制造条件下，Si-C-N-H具有比Si-C-H略高的介电常数。在典型的半导体制造条件下，Si-C-H的介电常数为4.5，而Si-C-N-H的介电常数为5.0-5.5。Si-C-N-H的氧阻挡特性可以通过提高沉积温度改善，然而，这导致帽层的更高的介电常数。例如，当沉积温度从350℃提高到400℃时，介电常数从5.0增加到5.5。另外，较高的沉积温度可以造成在铜金属化(metallization)中形成小丘，这可造成级间短路。
因此，尽管采用Si-C-H和Si-C-N-H材料作为帽层具有一些优点，本领域中仍然需要这样的互连结构，该互连结构利用铜或铝导体、其介电常数约为2至3的低k ILD、以及具有最优阻挡特性同时使其介电常数最小的帽层。
发明内容
本发明的一个目的是提供一种改善的半导体互连结构。
本发明的另一目的是提供一种具有帽层的互连结构，该帽层具有约5.0至5.5的介电常数且提供有效的氧阻挡特性。这通过优化帽膜的密度实现。
采用互连结构和形成互连结构的方法实现这些和其它目的。所述互连结构包括嵌入介电层中的导体例如铜；以及在所述导体上的低k介电帽层，所述帽层包括Si、C、H和可选的N。
根据参考附图给出的下面的详细说明的考虑，本发明的其它好处和优点将变得明显，附图详细说明和示出了本发明的优选实施例。
附图说明
图1是部分制造的集成电路器件的示意性截面图，示出了现有技术的互连结构。
图2是部分制造的集成电路器件的示意性截面图，示出了根据本发明的优选实施例的互连结构。
图3(a)-3(i)示出了形成图2的互连结构的优选方法。
图4是具有与现有技术一致的密度的350℃空气退火的Si-C-N-H膜的元素俄歇深度分布图，示出了氧渗透该膜进入下伏的Cu。
图5是具有比图4中的膜增加了的膜密度的400℃空气退火的Si-C-N-H膜的元素俄歇深度分布图，示出了氧渗入该膜厚度的50％。这表明阻挡膜抗氧的特性改善，防止氧到达下伏的Cu。
图6是具有与图5的膜类似的膜密度的改善的350℃空气退火的Si-C-N-H膜的元素俄歇深度分布图，示出了与图5中的膜等效的氧阻挡性能。
图7示出了与400℃膜相比改善的350℃膜的小丘的显著减少，这是采用在下一处理级的ILD沉积和蚀刻之后的暗场晶片检测由缺陷密度探测到的。插图示出了小丘缺陷的自顶向下的SEM图像，该小丘缺陷被在下一级的ILD沉积覆盖，直接在上一级上的Cu线上方。
具体实施方式
现在将参考附图说明本发明。在附图中，以简化方式示出和示意性表示了结构的不同方面，以更清楚地说明和示出本发明。例如，附图不旨在按比例绘制。另外，结构的不同方面的垂直截面示出为矩形形状。然而，本领域的技术人员将认识到，对于实际结构，这些方面将很可能包括更多锥形(tapered)的技术特征。此外，本发明不限于任何特定形状的构造。
尽管将关于包括Cu的结构说明本发明的特定方面，本发明不局限于此。尽管铜是优选导电材料，本发明的结构可以包括任何合适的导电材料，例如铝。
参考图2，本发明的互连结构的一个优选实施例包括下衬底110，该衬底110可以包括特定的逻辑电路单元，例如晶体管。公知为层间电介质(ILD)的介电层112覆盖在衬底110上。在衬底110与ILD层112之间可以设置附着促进剂层111。在ILD层112中嵌入至少一个导体115。在ILD层112与导体115之间可以设置扩散阻挡衬里114。通常通过化学机械抛光(CMP)步骤，使导体115的顶面与ILD层112的顶面共面。在导体115上设置帽层116。
第一互连级由图2中示出的互连结构中的附着促进剂层111、ILD层112、扩散阻挡衬里114、导体115和帽层116限定。在图2中的第一互连级上方示出的第二互连级包括附着促进剂层117、ILD层118、扩散阻挡衬里120、导体121和帽层122。
虽然优选低k介电材料，ILD层112和118可以由任何合适的介电材料形成。合适的介电材料包括：掺碳的二氧化硅(也称为氧碳化硅或SiCOH电介质)；掺氟的氧化硅(也称为氟硅酸盐玻璃，或FSG)；旋涂玻璃；硅倍半氧烷(silsesquioxane)，包括氢硅倍半氧烷(HSQ)、甲基硅倍半氧烷(MSQ)以及HSQ与MSQ的混合物或共聚物；以及任何含硅的低k电介质。具有利用硅倍半氧烷化学的SiCOH型组分的旋涂低k膜的实例包括HOSPTM(从Honeywell可得)、JSR 5109和5108(从Japan SyntheticRubber可得)、ZirkonTM(从Shipley Microelectronics可得)，以及多孔低k(ELk)材料(从Applied Materials可得)。具有有机组分的旋涂低k膜是聚合热固性材料，主要包含碳、氧和氢。优选的有机介电材料包括已知为SiLKTM的低k聚亚芳基醚聚合材料(从The Dow ChemicalCompany可得)，以及已知为FLARETM的低k聚合材料(从Honeywell可得)。
对于本实施例，优选的介电材料是通过PECVD沉积的掺碳的氧化硅(SiCOH)。对于该特定的ILD，采用了原位附着层(也称为过渡层)。在ILD材料的顶上沉积牺牲硬掩模(图2中未示出)，以辅助RIE构图并在处理期间保护ILD材料；该牺牲硬掩模在CMP平面化期间被去除。ILD层112和118均可以为约100nm至约1000nm厚，但是这些层均优选约600nm厚。ILD层112和118的介电常数优选为约1.8至约3.5，更优选为约2.5至约2.9。
可选地，ILD层112和118可以由包含孔的具有硅倍半氧烷型组分的材料或有机聚合热固性材料形成。如果ILD层112和118由这样的多孔介电材料形成，这些层的介电常数优选小于约2.6，更优选约1.5至2.5。特别优选采用介电常数为约1.8至2.2的多孔介电材料。
附着促进剂的选择取决于选定的特定ILD材料。在美国专利申请公开20050059258中，将薄的PECVD沉积的过渡层用于SiCOH ILD。当正在沉积的膜的前体被引入反应室的同时，在反应室中表面预处理步骤的等离子体仍然存在并起作用时，形成由图2中的层111和117表示的过渡层。在这种情况下，采用硅氧烷或其它含氧的有机硅前体，形成厚度为5-20nm的过渡层。
本实施例采用牺牲硬掩模层113和119(稍后将结合图3说明)，以辅助RIE构图并在RIE处理期间保护ILD材料。硬掩模材料的选择取决于ILD的选择，硬掩模材料可以是以下任何一种或它们的多个层：氧化硅、氮化硅、氧氮化硅、碳化硅、氮化碳化硅、碳氧化硅或改性的SiCOH。硬掩模层113和119应该分别与ILD层112和118形成强有力的附着接触。硬掩模层113和119优选在约20至约100nm厚的范围内，更优选在约25至约70nm厚的范围内。
尽管我们对优选的ILD SiCOH的附着层和牺牲硬掩模层的采用进行了说明，但本发明不限于该特定集成方案。附着和硬掩模层的材料的采用和选择由ILD和对该ILD合适的集成方案的选择来确定，无论是否利用附着层或硬掩模层，都保持本发明的精神。
导体115和121可以由任何合适的导电材料例如铜或铝形成。由于其相对低的电阻，特别优选铜作为导电材料。铜导体115和121可以包含低浓度的其它元素。扩散阻挡衬里114和120可以包括以下材料中的一种或多种：钽、钛、钨和这些金属的氮化物。帽层116和122优选由包括硅、碳、氮和氢的非晶氮化氢化碳化硅材料(Si-C-N-H)形成。
更具体地说，这些帽层优选由约20至34原子％的硅、约12至34原子％的碳、约5至30原子％的氮以及约20至50原子％的氢构成。换言之，帽层116和122优选具有组分SixCyNwHz，其中x为约0.2至约0.34，y为约0.12至约0.34，w为约0.05至约0.3，以及z为约0.2至约0.5。
帽层116和122的特别优选的组分为约22至30原子％的硅、约15至30原子％的碳、约10至25原子％的氮以及约30至45原子％的氢。该特别优选的组分可以表示为SixCyNwHz，其中x为约2.2至约3，y为约1.5至约3，w为约1至约2.5，以及z为约3至约4.5。帽层116和122应该分别与导体115和121及ILD层112和118形成强有力的附着接触。帽层116和122优选在约5至约120nm厚的范围内，更优选在约20至约70nm厚的范围内。
本发明的帽层，例如帽层116和122，提供了改善的对从铜导体迁移出的铜原子或离子的阻挡，还提供了改善的对移动到导体中的氧物类(例如O2和H2)的扩散的阻挡。相信后一种氧化物类是互连结构在加速应力条件下失效的主要来源。
在帽层与导体之间例如帽层116与导体115之间的界面处，帽层优选包含小于约1原子％的氧。例如，通过俄歇电子光谱(AES)或通过透射电子显微镜(TEM)中的电子能量损耗光谱，可以测得该界面处的氧浓度。互连结构在加速应力条件下的可靠性可以通过使该界面处的氧含量保持在小于约1原子％而得到显著改善。这可以通过对导体表面进行氨等离子体预清洗步骤而实现，这将在下面更详细说明。
可选地，在帽层与导体之间例如帽层116与导体115之间的界面处，帽层可以包含比存在于帽层的其它部分的氮浓度高的氮浓度。换言之，帽层的底面，即帽层与导体接触的那个表面，可以比帽层本体富有氮。优选该界面处的氮浓度在约5至20原子％的范围内，更优选在约10至15原子％的范围内。该界面处的富氮是由氨等离子体预清洗步骤导致的，这将在下面更详细说明。通过俄歇电子光谱(AES)深度分布图，其中由卢瑟福反向散射光谱(RBS)校准信号，可以测得该界面处的氮浓度。
图2的互连结构可以通过单或双镶嵌工艺例如图3(a)-3(i)中示出的工艺形成。该工艺优选从在衬底110上沉积附着促进剂层111开始，随后在附着促进剂层111上沉积ILD层112，如图3(a)所示。根据所采用的ILD，附着促进层111和ILD层112可以通过任何合适的方法沉积。
然后在ILD层112上沉积牺牲硬掩模层113，如图3(a)所示。牺牲硬掩模层可以通过任何合适的方法沉积，但优选通过等离子体增强化学气相沉积(PECVD)直接沉积在ILD层112上。
在图3(b)中，采用常规光刻构图和蚀刻工艺形成至少一个沟槽115a。在典型的光刻工艺中，在牺牲硬掩模层113上沉积光致抗蚀剂材料(未示出)。光刻材料通过掩模被暴露至紫外(UV)辐照，然后显影光致抗蚀剂材料。根据采用的光致抗蚀剂材料的类型，可以使光致抗蚀剂的曝光部分在显影期间可溶解或不可溶解。然后去除光致抗蚀剂的这些可溶解部分，留下与希望的沟槽图形匹配的光致抗蚀剂图形。然后，在未被光致抗蚀剂保护的区域中，通过例如反应离子蚀刻(RIE)去除牺牲硬掩模层113和部分ILD层112，形成沟槽115a。牺牲硬掩模层113可以如下地辅助该蚀刻步骤。牺牲硬掩模层113可以首先在未被抗蚀剂的覆盖区域中被蚀刻，然后抗蚀剂可以被去除，留下与光致抗蚀剂图形匹配的已构图的牺牲硬掩模层113。然后，可以在未被牺牲硬掩模层113覆盖的区域中蚀刻ILD层112。
参考图3(c)，在形成沟槽115a之后，沟槽优选衬有扩散阻挡衬里114，然后在沟槽115a中沉积导电材料以形成导体115。扩散阻挡衬里114可以通过任何合适的方法例如物理气相沉积(PVD)或“溅射”或者通过化学气相沉积(CVD)沉积而成。沉积扩散阻挡衬里114的优选方法是离子化的PVD。扩散阻挡衬里可以是通过PVD和/或CVD沉积的金属和金属氮化物的多个层。导电材料115可以通过任何合适的方法例如通过电镀、PVD或CVD，在沟槽115a中沉积而成。电镀是沉积铜导电材料115的最优选的方法。多余的衬里114、导电材料115和牺牲硬掩模113在CMP工艺中被去除，其中使导体115的顶面与ILD层112共面。
在沉积帽层116之前，优选在PECVD反应室中进行等离子体清洗步骤。对于200mm PECVD反应室，典型的等离子体清洗步骤采用氢源例如NH3或H2，流速在约50至500sccm范围内，并且该等离子体清洗步骤在约150℃至500℃范围内的衬底温度下，更优选在约300℃至400℃范围内的衬底温度下，进行约5至500秒更优选约10至100秒的时间。在该清洗步骤期间，RF功率在约100至700瓦特的范围内，更优选在约200至500瓦特的范围内。可选择地，可以以在约50至500sccm范围内的流速添加其它气体，例如He、氩(Ar)或N2。对于300mm PECVD反应室，优选的NH3或H2流速在500-2000sccm的范围内，其它可选择的气体例如He、Ar或N2在500-2000sccm的范围内，以及RF功率在200-800瓦特的范围内。
然后在导体115和ILD层112上沉积帽层116，如图3(d)所示。采用可以包括但不限于SiH4、NH3、N2、He、3MS、4MS和其它甲基硅烷的气体的结合，在约0.1至20乇范围内，更优选在约1至10乇范围内的压力下的反应室中，优选采用PECVD工艺沉积帽层116。
优选采用流速在约50至500sccm范围内的3MS或4MS以及流速在约50至2000sccm范围内的He沉积帽层116。沉积温度优选在约150℃至500℃的范围内，更优选在约300℃至400℃的范围内。通过N2或NH3气体，将氮包含在膜中。对于200mm PECVD反应室，N2或NH3流速在约50至500sccm的范围内，RF功率优选在约100至700瓦特的范围内，更优选在约200至500瓦特的范围内。对于300mm PECVD反应室，N2或NH3流速在约800至2000sccm的范围内，RF功率最优选在约400至800瓦特的范围内。最终的沉积厚度优选在约10至100nm的范围内，最优选在约25至70nm的范围内。
图3(a)-(d)示出了第一互连级的形成，第一互连级由附着促进剂层111、ILD层112、扩散阻挡衬里114、导体115和帽层116构成。在图3(e)中，第二互连级的形成从附着促进剂层117、ILD层118和牺牲硬掩模层119的沉积开始。附着促进剂层117可以采用与附着促进剂层111的相同的方法沉积。同样地，ILD层118可以采用与ILD层112的相同的方法沉积，以及牺牲硬掩模层119可以采用与牺牲硬掩模层113的相同的方法沉积。
图3(f)和3(g)示出了过孔121a和沟槽121b的形成。首先，可以采用常规光刻构图和蚀刻工艺，在牺牲硬掩模层119、ILD层118、附着促进剂层117和帽层116中形成至少一个过孔121a，如图3(f)所示。然后，可以采用常规光刻工艺，在牺牲硬掩模层119和部分ILD层118中形成至少一个沟槽121b，如图3(g)所示。过孔121a和沟槽121b可以采用与用于形成沟槽115a相同的光刻工艺形成。
可选地，过孔121a和沟槽121b可以通过首先构图和蚀刻在牺牲硬掩模119和ILD层118中的沟槽形成，其中该沟槽的深度等于沟槽121b的深度，但其长度等于沟槽121b的长度与过孔121a的宽度之和。然后可以通过蚀刻穿过剩余的ILD层118、附着促进剂层117和帽层116，形成过孔121a。
如图3(h)所示，在形成过孔121a和沟槽121b之后，过孔和沟槽优选衬有扩散阻挡衬里120，然后在过孔和沟槽中沉积导电材料以形成导体121。扩散阻挡衬里120可以通过与用于扩散阻挡衬里114的相同的方法沉积，导电材料121可以通过与用于导体115的相同的方法沉积。多余的衬里120、导电材料121和牺牲硬掩模119在CMP工艺中被去除，其中使导体121的顶面与ILD层118共面。
然后，在导体121和ILD层118上沉积帽层122，如图3(i)所示。帽层122可以采用与帽层116的相同的PECVD工艺沉积而成。
提供下面的非限制性实例，以便本领域的技术人员可以更容易地理解本发明。
实例1
当利用300mm PECVD反应室时，最优的工艺范围已经在前面列出并在此总结。
 处理条件  300mm PECVD反应室
 温度  300-400℃
 RF功率  400-800W
 3MS或4MS流速  50-500sccm
 He流速  50-2000ccm
 N2或NH3流速   800-2000sccm
对于400℃的沉积温度，具体条件是450sccm的3MS流量、1740sccm的NH3流量、730sccm的He流量和480瓦特的RF等离子体功率。较高的沉积温度导致这样的膜，其具有比美国专利申请公开20030134495中所述的对于200mm PECVD反应室的1.97g/cm3高的通过X射线反射(XRR)测得的2.10g/cm3的密度，并具有5.5的较高的介电常数。尽管这是介电常数的折衷，但较高的膜密度导致较好的对氧和铜物类的阻挡特性。帽层的提高的密度的另一个好处是，该帽层是用于过孔第一次处理的良好的蚀刻停止层。提高的密度还允许阻挡膜厚度在未来半导体代中减小，因为需要较小的膜厚度来阻止扩散物类穿过膜迁移到ILD或金属线中。
图4和5示出了改善的阻挡质量，图中示出了空气中炉退火之后在两个Si-C-N-H层中几种元素的浓度与深度的关系。为了在俄歇电子光谱(AES)深度分布之后检查帽层是否是良好的氧阻挡，通过在310-320℃下将样品在空气中退火约10-24小时进行该分析。因为空气包含氧，如果帽层不是良好的氧阻挡，高温退火将造成氧扩散穿过帽层。该实验模拟了工艺条件，其中在FTEOS沉积或CVD低k沉积期间，晶片处在高温的氧环境中。图4是在衬里/Si衬底上的厚Cu层上沉积的300mm Si-C-N-H样品，该样品具有与美国专利申请公开20030134495中的200mm膜类似的膜密度。在x轴的左侧的0mm深度表示帽表面，在x轴上向右的移动表示在膜中的垂直深度，直到到达厚Cu层。图5是300mm 400℃样品在空气退火后的深度分布图。对这些图的比较示出了改善的膜密度显著改善了Si-C-N-H对氧扩散的阻抗。
从对图4中的较低密度样品的俄歇电子光谱分析可知，氧一直向下扩散到Cu表面。当氧扩散到Cu表面时，氧在Si-C-N-H与Cu之间的界面处形成CuOx。CuOx促进了电迁移，因为如果由CuOx层引起的Cu与Si-C-N-H之间的附着差，则Cu沿着该界面扩散。对于在本实例中示出的这个问题的解决方案是提高沉积温度，从而增大膜密度和阻挡稳定性。除了介电常数的适度增加以外，该工艺的不利之处是在沉积期间较高的Cu小丘出现几率，这可导致级间短路。
实例2
对于最优的350℃工艺，具体的300m PECVD条件是300sccm的3MS流量、1200sccm的NH3流量、1200sccm的He流量和640瓦特的RF等离子体功率。在这些处理条件下沉积的膜具有与实例1中所述的400℃膜类似的膜密度，即通过XRR测得的2.15g/cm3。这些膜的介电常数略低于400℃膜，即5.4，表明密度是确定介电常数值的一个因素。因此，扩散阻挡有效性正比于膜密度和介电常数。
图6示出了通过空气退火和AES深度分布得到的该350℃膜的氧阻挡特性。比较图6和图5表明，改善的350℃处理条件重复了400℃膜的密度和阻挡有效性。通过降低沉积温度，在沉积期间发生的小丘的数量减少。这可以从图7中看出，图7示出了通过采用暗场晶片检测进行缺陷探测获得的400℃和最优的350℃工艺的加权缺陷密度的比较。降低沉积温度导致在下一处理级在蚀刻后(post-etch)ILD材料上的“嵌入污染”降低86％。大的Cu小丘被在下一级的ILD覆盖，看起来好像是直接在上一级的Cu线上方的凸起或嵌入的外来材料，如图7的插图所示。
降低的处理温度的其它好处包括减小的总的热预算以及通过AppliedMaterials ProducerTM PECVD反应室的性质改善的整个晶片的均匀性。另外，也许由于减少的小丘数量，与400℃工艺相比，电迁移略有改善。
尽管结合特定优选实施例和其它可选实施例具体说明了本发明，很明显，根据上述说明，许多替换、修改和变化对于本领域的技术人员而言是显而易见的。因此，所附的权利要求旨在包含落入本发明的真正范围和精神的所有这些替换、修改和变化。

Claims (17)

1.一种在衬底上形成的互连结构，包括：
介电层，覆盖所述衬底；
至少一个导体，嵌入所述介电层并具有与所述介电层的顶面基本上共面的表面；以及
帽层，在所述至少一个导体和所述介电层上，所述帽层具有与所述导体附着接触的底面。
2.根据权利要求1的互连结构，还包括导电衬里，其设置在所述至少一个导体与所述介电层之间。
3.根据权利要求1的互连结构，还包括附着促进剂层，其设置在所述介电层与所述衬底之间。
4.根据权利要求1的互连结构，其中所述介电层由介电常数为约2.0至约3.5的氧碳化硅(SiCOH)或掺氟的氧化硅形成。
5.根据权利要求1的互连结构，其中所述帽层由选自硅、碳、氮和氢的材料形成。
6.根据权利要求5的互连结构，其中所述帽层的材料是非晶氮化氢化碳化硅并具有约5.0至约5.5的介电常数。
7.根据权利要求5的互连结构，其中所述帽层的材料包括约20至约34原子％的硅、约12至约34原子％的碳、约5至约30原子％的氮和约20至约50原子％的氢。
8.根据权利要求5的互连结构，其中所述帽层的材料包括约22至约30原子％的硅、约15至约30原子％的碳、约10至约25原子％的氮和约30至约45原子％的氢。
9.根据权利要求1的互连结构，其中所述导体由铜形成。
10.根据权利要求5的互连结构，其中所述帽层在所述底面处包括小于1原子％的氧。
11.根据权利要求5的互连结构，其中所述帽层具有在所述帽层底面处的第一氮浓度和在所述帽层中心处的第二氮浓度，并且所述第一氮浓度大于所述第二氮浓度。
12.根据权利要求5的互连结构，其中所述帽层具有约2.1克/cm3的膜密度，从而提供改善的蚀刻停止特性。
13.根据权利要求12的互连结构，其中所述帽层具有在约5nm至120nm范围内的减小的厚度。
14.一种在衬底上形成互连结构的方法，包括以下步骤：
在衬底上沉积附着促进剂层或过渡层；
在所述附着层上沉积介电材料，从而形成介电层；
在所述介电层上沉积牺牲硬掩模材料，从而形成硬掩模层，所述硬掩模层具有被去除的顶面；
在所述硬掩模和介电层中形成至少一个开口；
用导电材料填充所述开口，从而形成至少一个导体，所述导体的表面与所述介电层的顶面基本上共面；以及
在所述导体上沉积帽层。
15.根据权利要求14的方法，其中所述顶面通过CMP平面化被去除。
16.根据权利要求14的方法，其中所述帽材料选自硅、碳、氮和氢。
17.根据权利要求16的方法，其中所述帽层通过包括以下步骤的方法形成：
利用等离子体清洗工艺清洗所述衬底，所述清洗工艺包括将所述衬底加热到约150℃至约500℃的温度，并将所述衬底暴露到氢源约5至约500秒的时间；以及
利用等离子体增强化学气相沉积(PECVD)工艺沉积所述帽材料，所述沉积工艺包括将所述衬底置于温度为约150℃至约500℃且压力为约0.1乇至约20乇的反应室中，将所述衬底暴露到至少一种甲基硅烷化合物，并施加约100瓦特至约800瓦特的RF功率。
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