CN1945821A - 半导体器件和半导体器件制造方法 - Google Patents

半导体器件和半导体器件制造方法 Download PDF

Info

Publication number
CN1945821A
CN1945821A CNA2006101007836A CN200610100783A CN1945821A CN 1945821 A CN1945821 A CN 1945821A CN A2006101007836 A CNA2006101007836 A CN A2006101007836A CN 200610100783 A CN200610100783 A CN 200610100783A CN 1945821 A CN1945821 A CN 1945821A
Authority
CN
China
Prior art keywords
substrate
interarea
semiconductor element
connection electrode
splicing ear
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2006101007836A
Other languages
English (en)
Inventor
大隅贵寿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of CN1945821A publication Critical patent/CN1945821A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/81024—Applying flux to the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

本发明揭示一种半导体器件和半导体器件制造方法，做成不需要衬底两面的阻焊层，减小衬底翘曲，使施加在连接部的应力减小，改善半导体元件的连接性，同时还使组装工序的自由度增大。

Description

半导体器件和半导体器件制造方法
发明领域
本发明涉及半导体器件和半导体器件制造方法，其技术涉及保护LSI片的集成电路部、而且确保外部装置与LSI片的电连接稳定、并可高密度安装的半导体器件，尤其涉及装载连接端子多的半导体元件的半导体器件。
背景技术
近年来，信息通信设备、事务用电子设备、家用电子设备、测量装置、组装机器手等产业用电子设备、医疗用电子设备、电子玩具等领域开展軽小化，强烈要求半导体器件安装面积小型化。
作为响应这些要求的一种措施，使用BGA(球栅阵)等。另一方面，BGA中装载的半导体元件随着高密度化，要求适应小片化、多引脚化。
图8是示出已有半导体器件的结构的剖视图。如图8所示，衬底5在一主面具有连接电极4，并且连接电极4在阻焊层10的开口中露出。在该主面上表面朝下地装载半导体元件1，半导体元件1在连接端子2上与衬底5的连接电极4电连接。在半导体元件1与衬底5之间，介入保护连接部的热硬化树脂3。
衬底5的另一主面具有外部电极7，并且外部电极7在阻焊层10的开口中露出。设置在衬底5的内部的通道6将连接电极4和外部电极7电连接，在外部电极7上形成外部端子8。
作为先行技术文献，有日本国专利公开公报：专利公开2003-2182799公报。
然而，如图7所示，已有的组成中，由于阻焊层10的收缩，衬底5产生全面翘曲。这是因为形成在衬底5的表面的阻焊层10的热收缩大于衬底5。
这种衬底5的翘曲导致产生下列问题。即，衬底5上装载半导体元件1时，不形成全部连接端子2与衬底5的连接电极4接触的状态。结果，半导体元件1的一部分连接端子2成为离开衬底5的连接电极的状态，产生接触欠佳的可能性大。
这样，连接部越增加，越要求衬底平坦，但上述衬底翘曲导致难以确保连接电极中电连接所需的平坦度。而且，连接部越增加，将半导体元件的连接端子连接到衬底的连接电极用的连接负载越增大。
因此，能适应半导体元件的多引脚化、小间距化、薄化的结构设计困难。
本发明鉴于上述课题，其目的在于提供一种半导体器件和半导体器件制造方法，能改善半导体元件的安装性(安装的可靠性、方便性)，减小半导体器件的连接应力，抑制连接部的变形，从而提高半导体器件的结构设计自由度。
发明内容
为了解决上述课题，本发明的半导体器件，具有衬底、表面朝下地装载在所述衬底的一主面的半导体元件、以及设置在所述衬底的另一主面的外部端子，其中，所述衬底在一主面下陷的位置具有与所述半导体元件的连接端子电连接的连接电极，在另一主面下陷的位置具有与所述外部端子电连接的外部电极，在内部具有连接所述连接电极和所述外部电极的通道。
根据上述组成，通过在衬底的从主面下陷的位置设置连接电极和外部电极，即使不形成阻焊层，也能防止钎焊材料等组成的连接端子的相邻端子或外部端子的相邻端子的桥接。
因此，不必在衬底的主面形成阻焊层，不发生起因于阻焊层的热收缩。
本发明的半导体器件，具有衬底、表面朝下地装载在所述衬底的一主面的半导体元件、以及设置在所述衬底的另一主面的外部端子，其中，所述衬底在一主面的与所述主面同高度的位置具有与所述半导体元件的连接端子电连接的连接电极，在另一主面下陷的位置具有与所述外部端子电连接的外部电极，在内部具有连接所述连接电极和所述外部电极的通道。
根据上述组成，通过在衬底的从主面下陷的位置设置外部电极，即使不形成阻焊层，也能防止钎焊材料等组成的外部端子的相邻端子的桥接。
因此，不必在衬底的主面形成阻焊层，不发生起因于阻焊层的热收缩。于是，能增加衬底的平坦度。
本发明的半导体器件，具有衬底、表面朝下地装载在所述衬底的一主面的半导体元件、以及设置在所述衬底的另一主面的外部端子，其中，所述衬底在一主面下陷的位置具有与所述半导体元件的连接端子电连接的连接电极，在另一主面的与所述主面同高度的位置具有与所述外部端子电连接的外部电极，在内部具有连接所述连接电极和所述外部电极的通道。
根据上述组成，通过在衬底的从主面下陷的位置设置连接电极，即使不形成阻焊层，也能防止钎焊材料等组成的连接端子的相邻端子的桥接。
因此，不必在衬底的主面形成阻焊层，不发生起因于阻焊层的热收缩。所以，即使在设置外部电极的主面形成阻焊层的情况下，也能使起因于阻焊层的热收缩减小，增加衬底的平坦度。
本发明的半导体器件，具有衬底、表面朝下地装载在所述衬底的一主面的半导体元件、以及设置在所述衬底的另一主面的外部端子，其中，所述半导体元件具有由丝焊装置形成的连接端子，所述衬底在一主面下陷的位置具有与所述半导体元件的连接端子电连接的连接电极，在另一主面下陷的位置具有与所述外部端子电连接的外部电极，在内部具有连接所述连接电极和所述外部电极的通道。
根据上述组成，通过在衬底的从主面下陷的位置具有连接电极和外部电极，即使不形成阻焊层，也能防止钎焊材料等组成的连接端子的相邻端子或外部端子的相邻端子的桥接。
因此，不必在衬底的主面形成阻焊层，不发生起因于阻焊层的热收缩。于是，能增加衬底的平坦度。
而且，即使偏离连接电极的中心装载由丝焊装置形成的、金材料组成的半导体元件的连接端子时，也通过在衬底的从主面下陷的位置设置连接电极，产生利用下陷将连接端子引导到连接电极的中心的效应。
本发明的半导体器件，具有衬底、表面朝下地装载在所述衬底的一主面的半导体元件、以及设置在所述衬底的另一主面的外部端子，其中，所述半导体元件具有由丝焊装置形成的连接端子，所述衬底在一主面的与所述主面同高度的位置具有与所述半导体元件的连接端子电连接的连接电极，在另一主面下陷的位置具有与所述外部端子电连接的外部电极，在内部具有连接所述连接电极和所述外部电极的通道。
根据上述组成，通过在衬底的从主面下陷的位置设置外部电极，即使不形成阻焊层，也能防止钎焊材料等组成的外部端子的相邻端子的桥接。
因此，不必在衬底的主面形成阻焊层，不发生起因于阻焊层的热收缩。于是，能增加衬底的平坦度。
本发明的半导体器件，具有衬底、表面朝下地装载在所述衬底的一主面的半导体元件、以及设置在所述衬底的另一主面的外部端子，其中，所述半导体元件具有由丝焊装置形成的连接端子，所述衬底在一主面下陷的位置具有与所述半导体元件的连接端子电连接的连接电极，在另一主面的与所述主面同高度的位置具有与所述外部端子电连接的外部电极，在内部具有连接所述连接电极和所述外部电极的通道。
根据上述组成，通过在衬底的从主面下陷的位置设置连接电极，即使不形成阻焊层，也能防止钎焊材料等组成的连接端子的相邻端子的桥接。
因此，不必在衬底的一主面(即安装半导体元件的主面)形成阻焊层，不发生起因于阻焊层的热收缩。于是，即使在设置外部电极的主面形成阻焊层的情况下，也能使起因于阻焊层的热收缩减小，使衬底的平坦度增加。
而且，即使偏离连接电极的中心装载由丝焊装置形成的、金材料组成的半导体元件的连接端子时，也通过在衬底的从主面下陷的位置设置连接电极，产生利用下陷将连接端子引导到连接电极的中心的效应。
本发明的半导体器件制作方法，包含以下工序：形成在一主面下陷位置具有连接电极，在另一主面下陷位置具有外部电极，并且在内部具有连接所述连接端子和所述外部电极的通道的衬底的衬底形成工序、在所述衬底的一主面表面朝下地装载半导体元件的倒装工序、使绝缘性热硬化树脂介入所述半导体元件与所述衬底的一主面之间的工序、以及将所述半导体元件的连接端子和所述衬底的连接电极电连接，并且同时使所述热硬化树脂硬化的加热工序。
根据上述组成，通过在衬底的从主面下陷的位置设置连接电极和外部电极，即使不形成阻焊层，也能防止钎焊材料等组成的连接端子的相邻端子或外部端子的相邻端子的桥接。
因此，不必在衬底的主面形成阻焊层，不发生起因于阻焊层的热收缩。于是，能增加衬底的平坦度。
本发明的半导体器件制作方法，包含以下工序：形成在一主面下陷位置具有连接电极，在另一主面下陷位置具有外部电极，并且在内部具有连接所述连接端子和所述外部电极的通道的衬底的衬底形成工序、以及在所述衬底的一主面表面朝下地装载半导体元件的倒装连接工序，在所述倒装连接工序中，一面使热硬化树脂介入所述半导体元件与所述衬底的一主面之间并进行加热，一面利用外加压力将所述半导体元件按压到所述衬底，对所述热硬化树脂进行热硬化后，使所述半导体元件与所述衬底接合，同时还将所述衬底的所述连接电极和所述半导体元件的连接端子电连接。
根据上述组成，通过在衬底的从主面下陷的位置具有连接电极和外部电极，即使不形成阻焊层，也能防止钎焊材料等组成的连接端子的相邻端子或外部端子的相邻端子的桥接。
因此，不必在衬底的主面形成阻焊层，不发生起因于阻焊层的热收缩。于是，能增加衬底的平坦度。
根据本发明，通过在衬底的从主面下陷的位置设置连接电极，不必形成阻焊层。因此，能抑制阻焊层热收缩造成的整个衬底翘曲，使衬底的平坦度增加。而且，由于衬底的平坦度增加，减轻对半导体元件的连接端子的平坦度要求。于是，使工序设计自由度增加。
又，可通过减小衬底的变形，抑制半导体元件安装后的衬底和半导体元件翘曲。
又，由于衬底平坦度增加，能减轻矫正衬底翘曲使其平坦用的负载。于是，能使将半导体元件安装到衬底时的负载降低。
由上述效果，实现有关半导体元件连接部的可靠性的提高。
附图说明
图1是示出本发明实施例1的半导体器件的剖视图。
图2是示出本发明实施例2的半导体器件的剖视图。
图3是示出本发明实施例3的半导体器件的剖视图。
图4是示出本发明实施例4的半导体器件的剖视图。
图5是示出本发明实施例5的半导体器件的剖视图。
图6是示出本发明实施例6的半导体器件的剖视图。
图7是示出已有半导体器件的剖视图。
图8是示出已有半导体器件的剖视图。
具体实施方式
下面，参照附图说明本发明的半导体器件的实施例。
实施例1
图1是示出本发明实施例1的半导体器件的结构的剖视图。如图1所示，衬底5在表里两个主面不形成阻焊层，而一主面中在从主面下陷的位置配置连接电极4，另一主面中在从主面下陷的位置配置外部电极7。然后，设置在衬底5内部的通道6将连接电极4和外部电极7电连接，并且在外部电极7上形成外部端子8。
连接电极4的表面至衬底5的一主面的高度和外部电极7的表面至衬底5的另一主面的高度，与形成阻焊层时的阻焊层厚度大小等同，具体而言，最好形成大于等于10微米。
下面，是在从衬底5的主面下陷的位置形成连接电极4和外部电极7的方法。
在半硬化状态的衬底5上，复制布线和电极的图案。此布线和电极的图案的厚度比衬底5的内部层上形成的布线电路的厚度大于等于10微米。
使衬底5硬化后，对连接电极4和外部电极7作蚀刻处理，使连接电极4和外部电极7在衬底5的从表面下陷的位置露出。作为其它方法，还有在半硬化的衬底5中，将电极和布线的图案埋入到离开衬底5的表面大于等于10微米的深度。
接着，说明半导体元件1的安装方法。半导体元件1中，利用电镀法、球装载法、印刷法等，在焊盘上形成连接端子2。将该半导体元件5以表面朝下的方式装载到衬底5的一主面，并以焊剂或导电糊等为中介，使半导体元件1的连接端子2与衬底5的连接电极4对接。在这种状态下，在衬底5上负载并按压每一连接电极4为大于等于5gf的外加压力。
接着，施加超过连接端子2的熔点的温度，使半导体元件1与衬底5接合，并且将连接端子2和连接电极4电连接。然后，在半导体元件1与衬底5之间介入热硬化树脂3，并使热硬化树脂硬化，以保护连接部。装载半导体元件1的衬底5的一主面用模压树脂9密封，用模压树脂9覆盖全部半导体元件1、连接端子2、连接电极4、热硬化树脂3。
在该实施例1中，连接端子2的材料是焊锡，但连接端子2中也可用Cu、树脂块。谋求进一步改善连接特性时，可考虑采用低温中熔化的基底树脂的方法。可在装载半导体元件1前将热硬化树脂涂覆或张贴在半导体元件1或衬底5上，也可在装载后使其介入半导体元件1与衬底5之间。外部端子8中一般使用焊锡球，但又可用焊锡以外的金属球，也可为不取球状的焊区、焊块。
衬底5由纤维强化树脂层等组成，其材料为玻璃布层压环氧树脂(玻璃环氧树脂)或芳香族聚酰胺无纺布等，此衬底5通过在半硬化状态的衬底5上复制布线和电极的图案，在其表面和内部形成布线和电极。
衬底5根据作为规范要求的布线密度叠积4层～8层。衬底5上形成的布线电路，其厚度为5微米～20微米左右，内层的布线材料使用Cu或Cu-Ni等，表面的布线材料使用Cu-Ni-Au等。
半导体元件1的厚度多数在大于等于30微米至小于等于300微米的范围，衬底5的厚度多数在大于等于260微米至小于等于420微米的范围。
连接端子2在配置于半导体元件1的外周部的情况下，配置成单列状或栅格状，其间距为60微米～80微米。连接端子2在半导体元件1的整个面上配置的情况下，配置成栅格状，其间距为150微米～250微米。
在上述组成的半导体器件中，通过在衬底5的从主面下陷的位置设置连接电极4和外部电极7，即使主面上不形成阻焊层，也能防止钎焊材料等组成的连接端子2的相邻端子或外部端子8的相邻端子形成桥接。
因此，衬底5的主面不必形成阻焊层，不发生起因于阻焊层的热收缩。于是，能使衬底5的平坦度提高。
其结果，将半导体元件1安装到衬底5时，使衬底5上负载的外加压力为低负载，可作形变量小的接合。又，即使由于连接端子2的数量增加而连接部的平坦性要求提高时，也能使接合负载减小。而且，能减小对连接端子2作用的应力，所以将半导体元件1安装到衬底5的安装工序设计容易，带动半导体器件可靠性提高。
实施例2
图2是示出本发明实施例2的半导体器件的结构的剖视图。图2中，衬底5的一主面上配置的连接电极4的表面处在与主面相同的高度上。衬底5的另一主面上配置的外部电极7配置在衬底5的从主面下陷的位置。
外部电极7的表面至衬底5的主面的高度与形成阻焊层时的阻焊层的厚度大小等同，具体而言，最好形成大于等于10微米。其它组成与上述实施例1相同，省略详细说明。
在这种组成中，通过在衬底5的从主面下陷的位置设置外部电极7，即使主面上不形成阻焊层，也能防止钎焊材料等组成的外部端子8的相邻端子形成桥接。
因此，衬底5的主面不必形成阻焊层，不发生起因于阻焊层的热收缩。于是，能使衬底5的平坦度提高。
其结果，将半导体元件1安装到衬底5时，使衬底5上负载的外加压力为低负载，可作形变量小的接合。又，即使由于连接端子2的数量增加而连接部的平坦性要求提高时，也能使接合负载减小。而且，能减小对连接端子2作用的应力，所以将半导体元件1安装到衬底5的安装工序设计容易，带动半导体器件可靠性提高。
实施例3
图3是示出本发明实施例2的半导体器件的结构的剖视图。图3中，衬底5的一主面上配置的连接电极4配置在衬底5的从主面下陷的位置。连接电极4的表面至衬底5的主面的高度与形成阻焊层时的阻焊层的厚度大小等同，具体而言，最好形成大于等于10微米。
衬底5的另一主面上配置的外部电极7在衬底5的另一主面上形成阻焊层10的开口中露出。外部电极7的表面处在与衬底5的主面相同的高度上。其它组成与实施例1相同，省略详细说明。
在上述组成的半导体器件中，通过在衬底5的从主面下陷的位置设置连接电极4，即使主面上不形成阻焊层，也能防止钎焊材料等组成的连接电极4的相邻电极形成桥接。
因此，衬底5的主面不必形成阻焊层，不发生起因于阻焊层的热收缩。于是，能使衬底5的平坦度提高。所以，即使配置外部电极7的另一主面上形成阻焊层10，也能减小起因于阻焊层的热收缩，使衬底5的平坦度增加。
其结果，将半导体元件1安装到衬底5时，使衬底5上负载的外加压力为低负载，可作形变量小的接合。又，即使由于连接端子2的数量增加而连接部的平坦性要求提高时，也能使接合负载减小。而且，能减小对连接端子2作用的应力，所以将半导体元件1安装到衬底5的安装工序设计容易，带动半导体器件可靠性提高。
实施例4
图4是示出本发明实施例4的半导体器件的结构的剖视图。如图4所示，衬底5在一主面下陷的位置配置连接电极4，在另一主面下陷位置配置外部电极7。
半导体元件1由丝焊装置在焊盘上形成连接端子2，连接端子2形成前端方尖细的形状。
将该半导体元件1表面朝下地装载到衬底5的一主面，一面加热，一面在衬底5上负载并按压每一连接电极4为大于等于20gf的外加压力。然后，一面利用外加压力进行衬底5的翘曲矫正，一面利用对介入半导体元件1与衬底5之间的热硬化树脂3加热并使其热硬化，将半导体元件1与衬底5接合后，将连接端子2与连接电极4电连接。
作为安装半导体元件1的其它方法有：将半导体元件1表面朝下的装载到衬底5的设置连接电极4的主面，以焊剂或导电糊为中介，使半导体元件1的连接端子2与衬底5的连接电极4对接。
接着，对衬底5负载并按压每一连接电极4为大于等于5gf的外加压力，并施加超过焊糊的熔点的温度或导电糊的硬化温度，使半导体元件1与衬底5接合，而且连接端子2与连接电极4电连接。使加热半导体元件1与衬底5之间的热硬化树脂3热硬化，以保护连接部。
本实施例中，连接端子2的材料是金，但连接端子2中也可用Ag、Cu等。谋求进一步改善连接特性时，可考虑采用低温中熔化的基底树脂的方法。可在装载半导体元件1前将热硬化树脂涂覆或张贴在半导体元件1或衬底5上，也可在装载后使其介入半导体元件1与衬底5之间。其它组成与上述实施例1相同，省略详细说明。
在上述组成的半导体器件中，通过在衬底5的从主面下陷的位置设置连接电极4和外部电极7，即使主面上不形成阻焊层，也能防止钎焊材料等组成的连接端子2的相邻端子或外部端子8的相邻端子形成桥接。
而且，即使在偏离连接电极4的中心装载由丝焊装置形成的、金材料等组成的半导体元件的连接端子2的情况下，也通过在衬底5的从主面下陷的位置设置连接电极4，产生利用下陷将连接端子2引导到连接电极4的中心的效应。于是，尽管主面上不形成阻焊层，也能防止钎焊材料等组成的连接端子2的相邻端子形成桥接。
因此，衬底5的主面不必形成阻焊层，不发生起因于阻焊层的热收缩。于是，能使衬底5的平坦度提高。
其结果，将半导体元件1安装到衬底5时，使衬底5上负载的外加压力为低负载，可作形变量小的接合。又，即使由于连接端子2的数量增加而连接部的平坦性要求提高时，也能使接合负载减小。而且，能减小对连接端子2作用的应力，所以将半导体元件1安装到衬底5的安装工序设计容易，带动半导体器件可靠性提高。
实施例5
图5是示出本发明实施例5的半导体器件的结构的剖视图。如图5所示，衬底5的一主面中，连接电极4的表面处在与衬底5的主面相同的高度上，并且另一主面中，在从主面下陷的位置设置外部电极7。此外部电极2的表面至衬底5的主面的高度与形成阻焊层使的阻焊层厚度大小等同，具体而言，最好形成大于等于10微米。
设置在衬底5的内部的通道6将连接电极4与外部电极7电连接，并且在外部电极7上形成外部端子8。半导体元件2由丝焊装置在焊盘上形成连接端子2，连接端子2形成前端方尖细的形状。其它组成和半导体元件1的安装方法与上述实施例4相同，省略详细说明。
在这种组成中，通过在衬底5的从主面下陷的位置设置外部电极7，即使不形成阻焊层，也能防止钎焊材料等组成的外部端子8的相邻端子形成桥接。
因此，衬底5的主面不必形成阻焊层，不发生起因于阻焊层的热收缩。于是，能使衬底5的平坦度提高。
其结果，将半导体元件1安装到衬底5时，使衬底5上负载的外加压力为低负载，可作形变量小的接合。又，即使由于连接端子2的数量增加而连接部的平坦性要求提高时，也能使接合负载减小。而且，能减小对连接端子2作用的应力，所以将半导体元件1安装到衬底5的安装工序设计容易，带动半导体器件可靠性提高。
实施例6
图6是示出本发明实施例6的半导体器件的结构的剖视图。如图6所示，衬底5的一主面上配置的连接电极4配置在衬底5的从表面下陷的位置，连接电极4的表面至衬底5的高度与形成阻焊层时的阻焊层厚度大小等同，具体而言，最好形成10大于等于微米。
衬底5的另一主面上配置的外部电极7在衬底5的另一主面上形成的阻焊层10的开口中露出，并且外部电极7的表面处在与衬底5的主面相同的高度上。其它组成和半导体元件1的安装方法与上述实施例4相同，省略详细说明。
在上述组成的半导体器件中，通过在衬底5的从主面下陷的位置设置连接电极4，即使主面上不形成阻焊层，也能防止钎焊材料等组成的连接端子2的相邻端子形成桥接。
而且，即使在偏离连接电极4的中心装载由丝焊装置形成的、金材料等组成的半导体元件的连接端子2的情况下，也通过在衬底5的从主面下陷的位置设置连接电极4，产生利用下陷将连接端子2引导到连接电极4的中心的效应。于是，尽管主面上不形成阻焊层，也能防止钎焊材料等组成的连接端子2的相邻端子形成桥接。
因此，衬底5的主面不必形成阻焊层，不发生起因于阻焊层的热收缩。于是，能使衬底5的平坦度提高。
其结果，将半导体元件1安装到衬底5时，使衬底5上负载的外加压力为低负载，可作形变量小的接合。又，即使由于连接端子2的数量增加而连接部的平坦性要求提高时，也能使接合负载减小。而且，能减小对连接端子2作用的应力，所以将半导体元件1安装到衬底5的安装工序设计容易，带动半导体器件可靠性提高。
工业上的实用性
本发明是保护LSI片的集成电路部、而且确保外部装置与LSI片的电连接稳定、又能高密度安装的半导体器件。因此，对装载耗电大的半导体元件的半导体器件尤其有效，并且使信息通信设备、事务用电子设备、家用电子设备、测量装置、组装机器手等产业用电子设备、医疗用电子设备、电子玩具等中用的半导体器件的可靠性提高。

Claims (8)

1.一种半导体器件，其特征在于，具有
衬底、
表面朝下地装载在所述衬底的一主面的半导体元件、以及
设置在所述衬底的另一主面的外部端子，
所述衬底在一主面下陷的位置具有与所述半导体元件的连接端子电连接的连接电极，在另一主面下陷的位置具有与所述外部端子电连接的外部电极，在内部具有连接所述连接电极和所述外部电极的通道。
2.一种半导体器件，其特征在于，具有
衬底、
表面朝下地装载在所述衬底的一主面的半导体元件、以及
设置在所述衬底的另一主面的外部端子，
所述衬底在一主面的与所述主面同高度的位置具有与所述半导体元件的连接端子电连接的连接电极，在另一主面下陷的位置具有与所述外部端子电连接的外部电极，在内部具有连接所述连接电极和所述外部电极的通道。
3.一种半导体器件，其特征在于，具有
衬底、
表面朝下地装载在所述衬底的一主面的半导体元件、以及
设置在所述衬底的另一主面的外部端子，
所述衬底在一主面下陷的位置具有与所述半导体元件的连接端子电连接的连接电极，在另一主面的与所述主面同高度的位置具有与所述外部端子电连接的外部电极，在内部具有连接所述连接电极和所述外部电极的通道。
4.一种半导体器件，其特征在于，具有
衬底、
表面朝下地装载在所述衬底的一主面的半导体元件、以及
设置在所述衬底的另一主面的外部端子，
所述半导体元件具有由丝焊装置形成的连接端子，所述衬底在一主面下陷的位置具有与所述半导体元件的连接端子电连接的连接电极，在另一主面下陷的位置具有与所述外部端子电连接的外部电极，在内部具有连接所述连接电极和所述外部电极的通道。
5.一种半导体器件，其特征在于，具有
衬底、
表面朝下地装载在所述衬底的一主面的半导体元件、以及
设置在所述衬底的另一主面的外部端子，
所述半导体元件具有由丝焊装置形成的连接端子，所述衬底在一主面的与所述主面同高度的位置具有与所述半导体元件的连接端子电连接的连接电极，在另一主面下陷的位置具有与所述外部端子电连接的外部电极，在内部具有连接所述连接电极和所述外部电极的通道。
6.一种半导体器件，其特征在于，具有
衬底、
表面朝下地装载在所述衬底的一主面的半导体元件、以及
设置在所述衬底的另一主面的外部端子，
所述半导体元件具有由丝焊装置形成的连接端子，所述衬底在一主面下陷的位置具有与所述半导体元件的连接端子电连接的连接电极，在另一主面的与所述主面同高度的位置具有与所述外部端子电连接的外部电极，在内部具有连接所述连接电极和所述外部电极的通道。
7.一种半导体器件制作方法，其特征在于，包含以下工序：
形成在一主面下陷位置具有连接电极，在另一主面下陷位置具有外部电极，并且在内部具有连接所述连接端子和所述外部电极的通道的衬底的衬底形成工序、
在所述衬底的一主面表面朝下地装载半导体元件的倒装工序、
使绝缘性热硬化树脂介入所述半导体元件与所述衬底的一主面之间的工序、以及
将所述半导体元件的连接端子和所述衬底的连接电极电连接，并且同时使所述热硬化树脂硬化的加热工序。
8.一种半导体器件制作方法，其特征在于，包含以下工序：
形成在一主面下陷位置具有连接电极，在另一主面下陷位置具有外部电极，并且在内部具有连接所述连接端子和所述外部电极的通道的衬底的衬底形成工序、以及
在所述衬底的一主面表面朝下地装载半导体元件的倒装连接工序，
在所述倒装连接工序中，一面使热硬化树脂介入所述半导体元件与所述衬底的一主面之间并进行加热，一面利用外加压力将所述半导体元件按压到所述衬底，对所述热硬化树脂进行热硬化后，使所述半导体元件与所述衬底接合，同时还将所述衬底的所述连接电极和所述半导体元件的连接端子电连接。
CNA2006101007836A 2005-10-04 2006-06-30 半导体器件和半导体器件制造方法 Pending CN1945821A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005290606A JP2007103614A (ja) 2005-10-04 2005-10-04 半導体装置および半導体装置の製造方法
JP2005290606 2005-10-04

Publications (1)

Publication Number Publication Date
CN1945821A true CN1945821A (zh) 2007-04-11

Family

ID=37901112

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2006101007836A Pending CN1945821A (zh) 2005-10-04 2006-06-30 半导体器件和半导体器件制造方法

Country Status (3)

Country Link
US (1) US20070075415A1 (zh)
JP (1) JP2007103614A (zh)
CN (1) CN1945821A (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7868440B2 (en) * 2006-08-25 2011-01-11 Micron Technology, Inc. Packaged microdevices and methods for manufacturing packaged microdevices
JP2011187484A (ja) * 2010-03-04 2011-09-22 Denso Corp 電子部品の実装構造
US9064781B2 (en) * 2011-03-03 2015-06-23 Broadcom Corporation Package 3D interconnection and method of making same
US8508045B2 (en) 2011-03-03 2013-08-13 Broadcom Corporation Package 3D interconnection and method of making same
JP7230462B2 (ja) * 2017-12-04 2023-03-01 ローム株式会社 半導体装置およびその製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3666591B2 (ja) * 2002-02-01 2005-06-29 株式会社トッパンＮｅｃサーキットソリューションズ 半導体チップ搭載用基板の製造方法

Also Published As

Publication number Publication date
US20070075415A1 (en) 2007-04-05
JP2007103614A (ja) 2007-04-19

Similar Documents

Publication Publication Date Title
CN1154178C (zh) 半导体装置及其制造方法、电路基板和电子装置
CN1835661A (zh) 配线基板的制造方法
CN1159956C (zh) 装有芯片封装的电路基板的端电极及其制造方法
CN100337327C (zh) 半导体器件及其制造方法
CN1107349C (zh) 一种半导体器件引线框架及引线接合法
CN1118098C (zh) 半导体集成电路器件
CN1160780C (zh) 用于半导体衬底的多层焊料密封带及其工艺
CN1665027A (zh) 半导体器件
CN1172368C (zh) 半导体器件
CN101080958A (zh) 部件内置模块及其制造方法
CN1191619C (zh) 电路装置及其制造方法
CN101044805A (zh) 复合多层基板及其制造方法
CN1221026C (zh) 由树脂制成应力吸收层的倒装片型半导体器件及制造方法
CN1577813A (zh) 电路模块及其制造方法
CN1185698C (zh) 半导体装置及其制造方法、电路板以及电子设备
CN1136220A (zh) 载片及其制造方法和安装方法
CN1551343A (zh) 电子元件封装结构及其制造方法
CN1266752C (zh) 电路装置的制造方法
CN1956183A (zh) 电子部件内置式基板及其制造方法
CN1758433A (zh) 半导体器件及其制造方法
CN1275246A (zh) 半导体装置及其制造方法、电路基板和电子装置
CN1281331A (zh) 带锚定焊盘的多层陶瓷衬底
CN1790651A (zh) 芯片集成基板的制造方法
CN1819133A (zh) 半导体装置的制造方法以及电连接部的处理方法
CN1815733A (zh) 半导体装置及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Open date: 20070411