CN1937217A - 封装结构与其封装方法 - Google Patents

封装结构与其封装方法 Download PDF

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CN1937217A
CN1937217A CNA2005101063992A CN200510106399A CN1937217A CN 1937217 A CN1937217 A CN 1937217A CN A2005101063992 A CNA2005101063992 A CN A2005101063992A CN 200510106399 A CN200510106399 A CN 200510106399A CN 1937217 A CN1937217 A CN 1937217A
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encapsulating structure
cupric oxide
copper conductor
substrate
conductive structure
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CN1937217B (zh
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许志岱
吴忠儒
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Silicon Integrated Systems Corp
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Silicon Integrated Systems Corp
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Abstract

本发明揭示一种封装结构与其封装方法；此封装结构具有基板、芯片、多条铜导线。基板具有至少一导电结构，铜导线表面具有绝缘物质。芯片固定于基板上，其借助包覆绝缘物质的铜导线电连接芯片与导电结构，故可减少因导线接近与交叠所造成的电性干扰与短路。

Description

封装结构与其封装方法
技术领域
本发明涉及一种封装结构与封装方法，特别涉及一种可减低电性干扰与短路的封装结构与封装方法，其借助包覆绝缘材质的铜导线而达成。
背景技术
传统的打线封装产品中，其信号的传递是使用打线接合(wire bonding)技术，将如金线从芯片的焊垫(pad)打线至封装基板上的结指(bondingfinger)，再经由基板上的走线(trace routing)、导电通孔、下层电路等将信号传递至基板底面的锡球，以完成信号传递。
图1为传统的封装结构剖面示意图，其封装基板118上固定有一芯片102，其以金线104连接基板118表面上导电的结指106，其与信号走线108相连接后，经由导电通孔110通过基板118与下层线路112连接，最后与基板118下方的锡球114相连接而形成一可以与外界电路连接的完整电路，使得信号以传至外界电路。芯片102则通常借助固晶银胶116粘粘结以固定于基板118上。此外，在完成封装结构时，需要使用绝缘材质，如封胶120(molding compound)覆盖，以固定多条金线104并且防止多条金线104之间产生导通的情形；之后再以导热上盖122覆盖于封胶120上。
然而，封装产品体积的日益缩小而电路布局的日趋复杂，因此金线密度也随之增加；因为金线本身为良好的导体并不绝缘，故相邻的金线或不同弧层的金线常常因为线距过密，以致于在封装作业过程中，只要有些许的电流便会有彼此电性导通的情形发生，造成产生短路现象；甚至，因为金线过于密集，若有金线彼此接触的情形，也同样会发生短路。现在多以限制金线的长度与限定结指位置分布的方式，减少金线彼此之间产生接近或交叠的机会以降低短路的机率。另外，为了降低金线间彼此的干扰，现有的封装技术需在相邻每一金线之间增加电性屏壁打线，而使得封装产品中的打线数目大大增加，容易造成封装上的困难度，以及时间与成本的浪费。此外，传统封装结构的打线接合即使使用了电性屏障打线而可避免金线间的短路及减少彼此的串扰(cross talk)，但是，对于金线之间磁性的干扰，传统的封装结构则多半无法加以阻隔。
鉴于前述传统封装基板的复杂走线设计以及电性的干扰，实有需要提出一种可以有效阻隔电性干扰而不增加打线数目的封装结构及其封装方法。
发明内容
于上述背景，本发明目的之一在于提供一种封装结构可以有效阻隔电性干扰。并有效地解决在现有技术中，因金线接近或交叠而产生的电性干扰与短路问题。
本发明的另一目的在于提供一种封装方法，无需利用电性屏壁打线即可阻隔电性干扰。其有助于有效地解决在现有技术中，以在各金线间增加接地线阻隔电性干扰而造成的金线密度过密、导致打线难度增加、电路布局复杂、封装难度与成本增加等问题。
根据上述的目的，本发明实施例之一提供一种封装结构与方法，其基板上具有接垫(例如结指)，每一个接垫经由基板内电路而电连接相对应的锡球，从而进行信号传递。芯片粘粘结固定于基板后，以包覆绝缘材质的铜导线进行打线接合。藉此，本发明即使因打线过密导致导线过于接近或交叠，也不会造成电性干扰或短路。再者，本发明无需电性屏障打线，故可避免传统复杂的走线布局，且可以避免连接导线之间的短路。
附图说明
图1为传统的封装结构剖面示意图；
图2为本发明实施例的封装结构剖面示意图；
图3A至图3E显示本发明图2封装结构的封装制造方法；
图4为本发明另一实施例的封装结构的剖面示意图，其具有电性屏蔽；
图5A至图5B为本发明导电固定结构分布区域不同的其它实施例的结构剖面示意图。
具体实施方式
本发明的一些实施例会详细描述如下。然而，除了该详细描述外，本发明还可以广泛地在其它的实施例施行。亦即，本发明的范围不受已提出的实施例的限制，还可有其他等效的变型实例。其次，当本发明的实施例图式中的各元件或结构以单一元件或结构描述说明时，不应以此作为有限定其数目多少的认知，故即使如下的说明未特别强调数目上的限制时，本发明的精神与应用范围仍可推及多数个元件或结构并存的结构与方法上。再者，在本说明书中，为充分揭露技术内容，各个元件的不同部分并没有依照尺寸绘图；某些尺度与其他相关尺度相比已经被夸张或是简化，以提供更清楚的描述和本发明的理解。而本发明所沿用的现有技艺，并不特别予以注明以免混淆完整揭露的条理，在此仅做重点式的引用，以助本发明的阐述。
图2为根据本发明实施例之一的封装结构的剖面示意图。封装基板218(底下简称基板)具有导电结构209；而导电结构209包含第一导电结构208、第二导电结构214。第一导电结构208形成于基板218的一表面，其可为接垫(pads)的形式(如结指)，或是其他种类型的导电结构(如柱状、圆形)。第二导电结构214形成于基板218的另一表面；其可为锡球或是其他种具有导电性质的材料及形状。此外，第一导电结构208借助基板218内线路212，如导电贯孔、金属线路层等，电连接相对应的第二导电结构214。
芯片202(chip或die)固定于基板218上；固定的方式可有多种不同方式，在本实施例中，借助一粘晶材料206而将芯片202粘结固定(diebond、die mount、或die attach)于基板218上。或者，如同再其他实施例，芯片202直接以焊接方式(solder)固定于基板218上。虽然，在本实施例中，粘晶材料206为具有导电性的粘性物质，如填充银粒子的环氧树脂(Epoxy)，一般称为银胶，但是再其他实施例中，也可以使用不具导电性的粘性物质，如环氧树脂、聚亚酰胺等，作为粘晶材料。
芯片202与基板218之间的信号传递借助芯片202的接垫(图中未示)与基板218的导电结构209之间的打线接合(wire bonding)而完成。其采用表面包覆有绝缘材质的铜导线204取代传统的金线。在本实施例中，包覆铜导线204的绝缘材质为氧化铜，但并不以此为限。其形成方式可以直接将铜导线进行氧化或是高温氧化从而形成氧化铜覆盖铜导线204的表面上，并且可借助氧化的温度与时间控制铜导线204上氧化铜的深度。然而，在其他实施例中，可以采用溅渡或是涂布等方式，将氧化铜覆盖于铜导线的表面上。
在芯片202与基板218的表面还可形成有绝缘层210，或可称势垒层(barrier layer)。此绝缘层210覆盖连接导线204与芯片202连接之处，以及覆盖连接导线204与导电结构209连接之处，从而保护这些连接处不与其他部份有所电性干扰。此外，阻挡结构216设置在基板218欲点胶的适当区域可形成边缘，以限制阻绝层210所分布的区域，不致使得绝缘层210在未凝固时四处流动。在本实施例中，阻挡结构216为一凸起结构的绝缘液挡墙，但并不是其唯一结构在其它实施例中亦可为一凹陷结构或可借助工艺控制无需挡墙，用以限制其形成范围。
如同图2所示，本发明的封装结构在完成时，需要使用封胶222(molding compound)覆盖，以保护基板218、芯片202、以及铜导线204不被破坏；之后再以导热上盖224覆盖于封胶222上。
图3A至图3E显示本发明封装结构的封装方法。首先，如图3A所示，准备一基板218，具有至少一导电结构209；在此实施例中，导电结构209具有第一导电结构208、第二导电结构214及电连接两者的基板内线路212。多个第一导电结构208设置于基板218上表面，第二导电结构214则设置于下表面上。
如图3B所示，在基板218上涂布一层粘晶材料206，用以将芯片202粘结固定于基板218上；而涂布粘晶材料206的方式有许多种，其中一种即是利用点胶方式形成。接着，如图3C所示，借助先前涂布的粘晶材料206将芯片202固定于基板218上。在本实施例中，因为采用需透过烘烤步骤而固化的粘晶材料206，如此，则需进行固化步骤，但并不以此为限。在其他实施例中，若粘晶材料206是能在常温下自动固化的材质、或不需固化步骤即可将芯片202固定于一限定范围的材质，则可配合整体制程，无需进行诸如烘烤(curing)、冷却等固化步骤。
图3D显示将多条铜导线204a以打线接合方式(wire bonding)连接于芯片202与导电结通209的第一导电结构208连接。借助铜导线204a使得芯片202、基板218、以及外界电路(图中未示)可以传递信号。接着，如图3E所示，在基板218与芯片202的适当部份形成绝缘层210(或可称势垒层)。其可依需求而只形成于需进行绝缘之处，如铜导线204a与导电结构209所连接之处，而不形成于其他部份；或可如本实施例般，以点胶技术使不导电材质(通常为液态或胶状的)分布于芯片202、基板218的大部份表面，而后可经烘烤使之固化；而使此绝缘层210填入芯片202焊垫与连接导线204连接处、连接导线204与第一导电结构208连接处的导体外露区域，使得整个电流流通路径之间彼此均被电绝缘(electricalinsulation)；如此，避免线路借助金属外露区域形成短路。此外，在基板218欲形成绝缘层210区域的外侧可先形成阻挡结构216，用以限定绝缘层210分布的范围。
另外，在烘烤绝缘层210使之固化的同时，借助烘烤的高温氧化上述的铜导线204a而在其表面以形成一层氧化铜，使其成为包覆绝缘材质(氧化铜)的铜导线204。然而，铜导线表面的氧化程度可以依需求而借助氧化的温度与时间来控制，如在本实施例中，采用125℃的高温烘烤8小时来形成，但并不以此为限。
然而，如图4所示，在本发明的封装结构中，以导电充填材料222a，例如导电银胶，取代封胶222包覆基板218、芯片202、与被氧化铜包覆的铜导线222。另外，导电充填材料222接触粘晶材料206，再透过连接基板218上的接地开窗207以形成接地，从而形成电性及电磁的屏蔽，减少电性及磁性干扰。前述导电充填材料222的工艺使用阻隔结构220，如边框式挡墙，用以限制导电充填材料222的分布范围。然后，使用覆盖结构224，如导热上盖，设置于阻隔结构220上。
在本发明中，可依需求而以不同方式界定绝缘层210的分布范围，并不限制于仅利用前述凸起结构或是凹陷结构。如图5A，其显示将多个芯片202a、202b、202c、202d设置于基板218上，并形成绝缘层210。对于包含多个芯片202a、202b、202c、202d的封装结构，绝缘层210的制作可以如图5A所示，不用阻挡结构而直接填入绝缘液使其可流至基板218上各个需要形成绝缘层210的位置。
本发明的封装结构所用的阻挡结构216，可以是如前所示的边框式挡墙包围住芯片，但亦可依需求而改变其型式。参照图5B，在芯片202与阻挡结构216之间填入绝缘液形成绝缘层210于所需的区域(芯片202上方、四周，或需要进行绝缘保护的区域)，而此阻挡结构216可在绝缘层形成后被移除。甚至亦可依需求，此阻挡结构216亦可用作界定导电充填材料分布范围的阻隔结构。
以上所述仅为本发明的较佳实施例，并非用以限定本发明的权利要求。在不脱离本发明的实质内容的范畴内仍可予以变化而加以实施，这些变化应仍属本发明的范围。而根据本发明的精神，本发明也可用于包含多个芯片的封装结构。因此，本发明的范畴由所附权利要求所界定。

Claims (36)

1.一种封装结构，包含：
基板，其具有至少一导电结构；
芯片，固定于所述基板；及
多条铜导线，每一所述这些铜导线表面皆被绝缘物质包覆，所述这些铜导线电连接所述芯片与所述导电结构。
2.如权利要求1所述的封装结构，其特征在于所述绝缘物质为氧化铜。
3.如权利要求2所述的封装结构，其特征在于所述氧化铜借助氧化所述铜导线表面而形成。
4.如权利要求2所述的封装结构，其特征在于所述氧化铜借助高温氧化所述铜导线表面而形成。
5.如权利要求2所述的封装结构，其特征在于所述氧化铜在125℃的环境中形成。
6.如权利要求5所述的封装结构，其特征在于所述氧化铜在125℃的环境中处理8小时所形成。
7.如权利要求2所述的封装结构，其特征在于所述氧化铜可以借助溅镀所述铜导线表面而形成。
8.如权利要求2所述的封装结构，其特征在于所述氧化铜可以借助涂布所述铜导线表面而形成。
9.如权利要求1所述的封装结构，其特征在于还包含导电充填材料，固定于所述这些铜导线之间。
10.如权利要求9所述的封装结构，其特征在于还包含接地结构，电连接所述导电充填材料。
11.如权利要求10所述的封装结构，其特征在于所述的基板具有接地开窗，所述接地结构为形成于所述基板上的所述接地开窗。
12.如权利要求1所述的封装结构，其特征在于还包含绝缘层，覆盖所述这些铜导线与所述导电结构相接处。
13.如权利要求1所述的封装结构，其特征在于还包含绝缘层，覆盖所述这些铜导线与所述芯片相接处。
14.如权利要求1所述的封装结构，其特征在于所述的导电结构包含：
第一导电结构，设置于所述基板的一表面；以及
第二导电结构，设置于所述基板的另一表面，并且所述第一导电结构电连接所述第二导电结构。
15.如权利要求14所述的封装结构，其特征在于所述的第一导电结构包含至少一接垫。
16.如权利要求14所述的封装结构，其特征在于所述的第二导电结构包含多个锡球，用以电连接外界电路。
17.一种封装方法，包含：
提供基板，其中所述基板具有至少一导电结构；
固定芯片于所述基板；
以多条铜导线电连接所述芯片与所述导电结构；及
形成绝缘物质包覆所述这些铜导线表面。
18.如权利要求17所述的封装方法，其特征在于形成所述绝缘物质步骤为形成氧化铜。
19.如权利要求18所述的封装结构，其特征在于形成所述氧化铜为氧化所述铜导线表面而形成。
20.如权利要求18所述的封装结构，其特征在于形成所述氧化铜为溅镀所述铜导线表面而形成。
21.如权利要求18所述的封装结构，其特征在于形成所述氧化铜为涂布所述铜导线表面而形成。
22.如权利要求17所述的封装方法，其特征在于还包含形成导电充填材料于所述这些铜导线之间。
23.如权利要求17所述的封装方法，其特征在于还包含形成接地结构连接所述导电充填材料。
24.如权利要求17所述的封装方法，其特征在于所述的接地结构为形成于所述基板内的接地开窗。
25.如权利要求17所述的封装方法，其特征在于还包含形成绝缘层覆盖所述导电结构与所述这些铜导线相接处。
26.如权利要求18所述的封装方法，其特征在于还包含烘烤步骤。
27.如权利要求26所述的封装结构，其特征在于所述氧化铜借助所述烘烤步骤氧化所述铜导线表面而形成。
28.如权利要求27所述的封装结构，其特征在于所述烘烤步骤以所述氧化铜形成于125℃的环境烘烤所述这些铜导线表面以形成氧化铜。
29.如权利要求28所述的封装结构，其特征在于烘烤步骤以125℃的环境处理8小时烘烤所述这些铜导线表面以形成氧化铜。
30.如权利要求17所述的封装方法，其特征在于还包含形成绝缘层覆盖所述这些铜导线与所述芯片相接处。
31.如权利要求30所述的封装方法，其特征在于还包含烘烤步骤。
32.如权利要求31所述的封装结构，其特征在于所述氧化铜借助所述烘烤步骤氧化所述铜导线表面而形成。
33.如权利要求32所述的封装结构，其特征在于烘烤步骤以125℃的环境烘烤所述这些铜导线表面以形成氧化铜。
34.如权利要求33所述的封装结构，其特征在于烘烤步骤以125℃的环境处理8小时烘烤所述这些铜导线表面以形成氧化铜。
35.如权利要求17所述的封装方法，其特征在于所述的形成导电结构包含：
形成第一导电结构，设置于所述基板的一表面；以及
形成第二导电结构，设置于所述基板的另一表面，并且所述第一导电结构电连接所述第二导电结构。
36.如权利要求17所述的封装方法，其特征在于所述的导电充填材料包含导电银胶。
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CN103096698A (zh) * 2011-10-31 2013-05-08 鸿富锦精密工业（深圳）有限公司 电磁屏蔽方法及制品
CN110024068A (zh) * 2017-01-13 2019-07-16 松下知识产权经营株式会社 电解电容器

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JP3537417B2 (ja) * 2001-12-25 2004-06-14 株式会社東芝 半導体装置およびその製造方法
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CN110024068A (zh) * 2017-01-13 2019-07-16 松下知识产权经营株式会社 电解电容器
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