CN1917156A - 在引线架结构上有倒装芯片的密封型芯片级封装及其方法 - Google Patents

在引线架结构上有倒装芯片的密封型芯片级封装及其方法 Download PDF

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CN1917156A
CN1917156A CNA2006101156031A CN200610115603A CN1917156A CN 1917156 A CN1917156 A CN 1917156A CN A2006101156031 A CNA2006101156031 A CN A2006101156031A CN 200610115603 A CN200610115603 A CN 200610115603A CN 1917156 A CN1917156 A CN 1917156A
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lead frame
chip
conductive
pad
lead wire
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CN1917156B (zh
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乔斯弗·K·弗蒂
小詹姆斯·P·莱特蔓
戴尼斯·西恩泊特
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Semiconductor Components Industries LLC
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Semiconductor Components Industries LLC
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Abstract

在一个实施例中，密封型电子封装包含装有在主表面上形成图形化可焊焊盘的半导体芯片。在组装过程期间，直接把图形化可焊焊盘安装到导电引线上。用例如MAP包覆成型工艺来密封组件，并且然后使组件通过分割加工而形成在引线架互连上装有倒装芯片的各个芯片级封装。

Description

在引线架结构上有倒装芯片的 密封型芯片级封装及其方法
技术领域
本发明一般地涉及电子器件，而更具体地涉及组件的薄剖面小基底面封装和方法。
背景技术
手持式消费产品市场在可移动电子设备微型化方面是所向披靡的。主要由于便携式电话市场和数字化辅助市场推动，这些器件的制造受到尽可能缩减大小尺寸和对更多PC类功能需要的挑战。这种挑战是不可抗拒的，迫使表面安装元件制造部门来设计尽可能控制最小面积的业内产品。这样做就使可移动电子设备设计人员能够把一些额外功能装入器件而没有增加总的产品尺寸。
制造部门研制了各种类型的封装技术和互连技术来减小半导体元件的总尺寸。封装技术方法的一些实施例包含无引线封装、表面安装封装、芯片级封装和球栅阵列封装。典型互连技术的一些实施例包含倒装芯片互连，倒装芯片互连包含焊料球互连结构、焊料块互连结构和双头块互连结构。
在使用倒装芯片互连的一种典型器件中，形成叠置在半导体芯片上面的铝焊接面。然后把氮化物钝化层覆盖在芯片上面并且把像苯并环丁酮(BCB1)层之类有机钝化层覆盖在氮化物钝化层上面。然后在BCB1和氮化物层中形成一些开口以露出铝焊盘。下一步，在开口里形成像AlNiVCu焊盘之类内块金属(UBM)焊盘并且接触在下面露出的铝焊盘。然后采用焊接、球压焊或双头块技术方法把焊料块或焊料球安装到UBM焊盘上。
在以上所述的倒装芯片互连工艺过程存在包含工艺变易性和可靠性的一些问题，结果是与一些不同的材料有关。并且，球安装或块工艺方法使工艺流程复杂化。此外，就每片200mm晶片$90～$150的成本来说，常规倒装法互连工艺是非常昂贵的。
因此，需要有一种具有小尺寸、成本低收效大和致力于解决与以上所描述的焊料球/块互连方案有关的一些可靠性问题的改进型电子封装结构及其方法。
附图说明
图1具体说明根据本发明一个实施例所封装的器件的横截面图；
图2具体说明根据本发明的一种互连结构的放大横截面图；
图3具体说明在制造中间阶段时图1中一部分已封装器件的高倍放大横截面图；
图4具体说明供本发明使用一种主引线架结构的一个实施例的顶视图；
图5具体说明在根据本发明的进一步处理以后图4中的主引线架结构的顶视图；
图6具体说明在根据本发明的更进一步处理以后图4中的主引线架结构的顶视图；
图7具体说明在分割以前根据本发明处理的图4中所封装器件的顶视图；
图8-12具体说明根据本发明一些不同实施例所封装的器件的局部侧视图；
图13具体说明根据本发明另一个实施例所封装的器件的局部侧视图；
图14具体说明根据本发明进一步实施例所封装的器件的横截面图；
图15具体说明根据本发明更进一步实施例所封装的器件的横截面图；以及
图16和17具体说明表示根据本发明形成互连结构的一部分衬底在各个制造阶段时的放大横截面图。
具体实施方式
为了便于理解，不一定按比例绘制附图中的一些元件，而且专用于所有不同附图的同样元件标词数字用来表示同样或类似的元件。
另外，下面使用方形扁平无引脚(QFN)芯片级封装实施例来描述本发明，同样，它也适用于理解本发明的其他芯片比例封装类型。
图1表示根据本发明一个实施例所封装的半导体器件或电子器件或结构10的高倍放大横截图。根据本发明，器件10包括在引线架互连结构上具有倒装片的一种密封型芯片级封装。正如在此所使用的那样，芯片级封装指的是比在封装里装有的电子元件的尺寸小大约1.2倍的一种封装。
器件10包含具有主要表面14的半导体芯片或者半导体器件12。举例来说，半导体芯片12包括逻辑元件、功率元件、存储器、传感器、光学元件或无源元件，并且在以上所描述的引线架结构上以倒装芯片表示半导体芯片12。在所示的实施例中，器件10适用于对仅在一个表面上的互连方案有要求的这些器件。下面将结合图4来描述对在多个表面上的互连方案有要求的一个替换实施例。
器件10进一步包含提供与下一级组件或到芯片12外部的一些结构电连接的多个导电引线或可焊接的导电引线17。导电引线17可以有各种各样形状和特征，下面将结合图8-13更充分地描述这些形状和特征。举例来说，导电引线17包括像铜合金(例如，TOMAC4、TAMAC5、2ZFROFC或CDA194)、镀铁/镍合金的铜(例如，镀合金42的铜)、镀铝的铜、涂敷塑料的铜或者诸如此类可焊接的材料。镀敷材料包含铜、银或者像镍-钯和金之类多层镀层。
密封层即覆盖层19密封芯片12和一部分导电引线17而使剩下其他部分导电引线17如例如图1所示那样沿器件10主表面22暴露出。举例来说，密封层19包括塑性环氧树脂材料。
根据本发明，形成或构图成叠加在主表面14上面的可焊接金属焊盘、多层可焊接导电结构、图形化的可焊接互连结构或者图形化的可焊接金属焊盘21，以使在芯片12上面、在芯片12上方或芯片12里面形成的电路与导电引线17互连。根据本发明，可焊焊盘21包含为连接或安装到器件10中的导电引线17上而以最外面层或暴露区形式定位或放置的图形化可焊接金属层或镀层。正如在此所使用的那样，把可焊接的金属定义为具有良好到极好可焊性的金属，或者具有熔融焊料比较容易浸润表面的金属。一些可焊接金属的实施例包含铜、银、金、钯、铑、镍-银等等。一些被认为不可焊接的金属的实施例包含铬、钛、铝和铝合金。
此外，正如在此所使用的那样，图形化结构指的是由在半导体芯片或晶片上面一层或更多层覆盖层沉积或形成所产生的一种结构，接着这些覆盖层是根据预先确定的图形或掩模来蚀刻或图形化的，以形成特定的结构。正如在此所使用的那样，图形化的结构不包含用电镀技术方法形成的结构。
图2表示一部分芯片12的局部高倍放大视图以提供一个根据本发明图形化可焊焊盘或一个根据本发明图形化互连结构21的补充细部图。在这个实施例中，焊盘21包括在表示出含电介质层113的芯片12上面所形成的一种导电材料多层结构。例如，焊盘21包含用铝或像AlCu、AlCuSi、AlSi、或诸如此类铝合金做的第一导电层，第一导电层在芯片12上形成并且接触例如在芯片内或上面所形成的器件结构即区域114。举例来说，第一薄层210具有厚度大约0.5微米～大约5.0微米。然后在第一导电层210上面形成粘结或第二导电层211并且包括例如钛、铬、氮化钛或诸如此类。举例来说，第二导电层211具有厚度大约0.1微米～大约0.2微米。然后在第二导电层211上面形成扩散阻挡层或第三导电层212并且包括例如镍、镍钒合金或诸如此类。举例来说，第三导电层212具有厚度大约0.15微米～大约0.3微米。在第三导电层212上面形成可焊接金属层或第四导电层213并且包括例如铜、银、金或诸如此类。举例来说，第四导电层具有厚度大约0.7微米～大约1.0微米。
根据本发明，叠置在芯片12上面的图形化可焊焊盘21是采用常规蒸发或溅射沉积技术来形成的并且接着是采用常规平板印刷和蚀刻技术来图形化的。图形化可焊焊盘21具有适合于在芯片12和引线17之间构成足够间隙的厚度。图形化可焊焊盘21避免了与使用包含UBM层、有机钝化层和所安装的焊料球或块的现有技术倒装芯片互连方案有关的组装和可靠性问题。另外，本发明由于简化了工艺过程而使互连工艺过程成本减少近80％。
图3表示一部分图1所示的器件10在制造中间阶段时的高倍放大横截面图。在这个步骤时，具有图形化焊盘21的半导体芯片12是与具有导电引线17的引线架同时构成的。安装层或焊料安装层24用来把图形化焊盘21连接到固定到导电引线17上而构成引线架结构或组件31的倒装芯片。举例来说，安装层包括焊料压片或焊料膏。例如，安装层24包括低共熔焊料、焊接焊料膏、焊料预加工薄膜或诸如此类。在一个实施例中，安装层24包括引线/锡/银或无引线焊接材料。
按一种工艺过程次序，把芯片12、安装层24和导电引线放置成保持接触以便形成组件31。然后用例如回流炉来使组件31加热以在图形化焊盘21和导电引线17之间形成金属键合。在一种替换工艺流程中，在一个分段工艺过程内使导电引线17预热，把安装层24放在导电引线17上，并且把芯片12固定或者焊接到导电引线17上。用替换实施例，把安装层24放在焊盘21上面而然后把安装层24放到预热的导电引线17上。
图4是适合于用作本发明一种部件的主引线架41的顶视图。主引线架41包括多个子引线架43，多个于引线架43包含多个导电引线17。虽然只表示出四个子引线架43，但是可以使用包含在具有多个行和列的阵列内的或更多或更少个子引线架43。
图5表示装有安装到其中一个子引线架43上以构成其中一个组件31第一半导体芯片12的主引线架41的顶视图。为了便于理解，图3所示的在引线架上倒装芯片组件31横截面图是沿图5的标记线3-3得出的。然后采用以上结合图3所概括阐述的工艺过程把另外一些芯片12安装到可以买得到的子引线架43或者剩留下的子引线架43上以构成多个在引线架上倒装芯片组件310。
图6表示图5的结构在主引线架41上面形成密封层以后的顶视图。图6中所示的实施例包括一种模制阵列封装(MAP)组件，其中密封层19以不间断薄膜形式覆盖多个子引线架43。用替换实施例，采用阴模模制技术、液封技术或槽缝模制技术来形成密封层19。
在形成密封层19以后，使用一种特殊工艺来把器件阵列分割成如图7所示的一些分立的封装或器件10。一些线条71表示在存在锯切割装置或者其他分割装置或特殊装置的场合下分割线的一个实施例。
现在翻到图8-12，根据本发明描述导电引线17的一些不同实施例。虚线71表示在所有不同实施例上所建议的特定线条。为了便于理解本发明的这个部分而没有表示出密封层19。图8表示包含用于安装芯片12内图形化可焊焊盘21中的隆起部分即台阶部分118的导电引线117的局部侧视图。隆起部分118的一个优点在于在安装过程期间为使芯片12更好地校正而提供保证，隆起部分118有助于在组装期间防止芯片12偶然转动。在所示的实施例中，使隆起部分118离末端部分119彼此留出一定间隔而在末端部分119和隆起部分118之间留下凹入部分121。在一种精细组装中，如图1所示那样导电引线117的暴露部分或外部表面延伸到器件10的边缘。
图9表示具有隆起部分即台阶部分218的导电引线217的局部侧视图。导电引线217除隆起部分与末端部分219毗连或邻接以外类似于导电引线117。在一种精细组装中，如图1所示那样导电引线217的暴露部分或外部表面延伸到器件10的边缘。
图10表示具有隆起部分318和凹入部分321的导电引线317的局部侧视图。导电引线317除用密封材料填满凹入部分321以便导电引线317的暴露部分或外部表面323在密封以后嵌在密封型器件的边缘与器件边缘分开以外类似于导电引线217。在下面描述的图13中表示出像这种结构的实施例。
图11表示具有与半导体芯片12边缘13毗连或邻接的对正特点或隆起部分422的导电引线417的局部侧视图，导电引线417为在组装过程期间更一致的半导体芯片12校正或方位提供保证。
图12表示具有对正特点或隆起部分522的导电引线517的局部侧视图，对正特点522类似于对正特点422。导电引线571进一步具有凹入部分521，在密封过程期间用密封材料填满凹入部分521。这样就使导电引线517的暴露部分或外部表面523嵌在密封型器件的边缘，并且与器件边缘分开。在下面描述的图13中表示出像这种结构的实施例。
图13表示根据本发明另一个实施例封装好的半导体器件或结构或者电子器件或结构100的局部横截面图。根据本发明，器件100包括具有在引线架上倒装芯片互连结构的一种密封型芯片级封装。器件100除器件100进一步包含与导电引线617连接的焊料球或块626以构成一种球栅阵列实施例以外类似于器件10。在一个实施例中，导电引线617包含容纳其中一个焊料球626的凹坑、陷窝或压痕620。在一些可选择的实施例中，导电引线617进一步包含隆起部分618和/或凹入部分623。另外，应当理解，可以把在此所公开、包含图8-12所表示的各种特点的一些不同特点其中一个特点或更多个特点并入器件10和100。
图14表示根据本发明进一步实施例封装好的半导体器件或者电子器件或结构200的高倍放大横截面图。根据本发明，器件200包括具有在引线架上倒装芯片互连结构的一种密封型芯片级封装。器件200包含除芯片212在导电引线717范围不装有焊盘21并且芯片212包含用于流通器件电流的有源主表面即第二主表面215以外类似于芯片12的芯片212。用在芯片212的主表面214上面形成的焊盘21来把芯片212安装到导电引线217上。结构200进一步包含把有源表面215连接或联接到导电引线717的一种附属装置36。举例来说，附属装置36包括像金属夹、镀金属的金属夹或镀金属的塑料夹之类导电夹具。另外，应当理解，可以把在此所公开、包含图8-13所表示的各种特点的一些不同特点其中一个特点或更多个特点并入器件200。
图15表示根据本发明更进一步实施例封装的半导体器件或者电子器件或结构300的高倍放大横截面图。根据本发明，器件300包括装有在引线架上倒装芯片互连结构的一种密封型芯片级封装。器件300除密封材料19不完全覆盖或不完全密封器件12的主表面315以外类似于器件10。换言之，露出表面315全部或者表面315的一部分。这就为电输送或热传导应用提供例如一种用于直接与芯片12表面315接触的实施例。举例来说，把夹具(例如图14所示的夹具36)或导线接头安装到用于使器件12连接到另一种组装结构的表面215上。用一种替换实施例，把一种头部展宽的装置(直接或间接)安装到表面315上以增强器件300的热性能。把典型的实施方案301和302表示为装有暴露表面315结构的一些实施例。在实施方式301中，密封层19基本上是与表面齐平的，并且是在模制期间使用掩模结构的掩盖层来形成的，或者在密封以后采用研磨或者其他清除技术来形成的。在实施方式302中，形成叠置在表面315上面的一部分密封层以构成窗框状结构。在膜制期间采用掩模技术或者在密封后采用蚀刻或一些其他清除技术来构成实施方式302。另外，应当理解，可以把在此所公开，包含图8-14所表示的各种特点的一些不同特点其中一个特点或更多特点并入器件300。
图16和17表示根据本发明在制造的各个阶段时的衬底或半导体晶片112的放大局部横截面图以举例说明用于形成图形化焊盘21的一种晶片校正方法。在图16中表示出装有电介质层113的晶片112，介电层113含有一些开口以提供通向在沿主表面14不同的位置上形成的一些器件区域114的一些入口。采用蒸发或溅射沉积枝术在薄片112上面沉积多个导电覆盖层209。在所表示的实施例中，多个薄层209包括结合图2所描述的一些导电层210-213。应当理解所述多个薄层209可以包括更多或更少导电层，并且应当理解这些薄层是在一次沉积中、在一些分立的沉积步骤中或者两者的组合中按顺序沉积的。根据本发明，所述多个的薄层209包含用作最外面导电层的可焊接金属层213。
然后在薄层209的上面沉积光致抗蚀剂层并且应用常规光刻技术方法使光致抗蚀剂层图形化以提供一种预定或所想要的图形215。下一步，蚀刻掉薄层209中的暴露部分，并且清除图形化的抗蚀剂层215以致形成图17所示的图形化导电焊盘即结构21。应当理解，可以按顺序沉积一部分薄层209并且使其图形化，和沉积另外部分薄层209并且使其图形化。然后使用一些众所周知的技术把薄片112分割成多个芯片或器件12。
到此为止，显而易见，已根据本发明提供了用于形成一种改进型电子封装的结构和方法。这种封装装入具有图形化的连接结构、或在主表面上形成的焊盘的电子芯片。图形化连接结构包含用于形成与导电引线金属键合以构成在引线架上倒装芯片结构的暴露或在外面的可焊接金属层。图形化连接结构提供一种与现有技术器件相比更可靠而成本更低收效更大的封装结构。
在一些进一步的实施例中，把一些焊料球或块加到一些导电引线上，并且装入使电子芯片主表面与导电引线连接的导电夹具。
虽然已参照其具体实施例描述了而且举例说明了本发明，但是并不意味着本发明局限于这些例证性实施例。

Claims (10)

1.一种用于形成在引线架互连结构上装有倒装芯片的芯片级封装的方法，该方法包括步骤：
提供具有第一和第二子引线架的主引线架，其中第一和第二子引线架装有多个导电引线；
提供第一和第二电子器件，每个电子器件装有在第一主表面上形成的多个图形化的可焊焊盘；
把在第一电子器件上图形化的可焊焊盘进行焊料安装(solderattaching)到第一子引线架上；
把在第二电子器件上图形化的可焊焊盘进行焊料安装到第二子引线架上；
用密封材料密封第一和第二子引线架以及第一和第二电子器件以形成密封型组件；以及
使密封型组件分离以构成芯片级封装。
2.根据权利要求1的方法，其中提供主引线架的步骤包括：提供具有含多个导电引线的第一子引线架的主引线架，而多个导电引线包括用于焊料安装到第一电子器件上图形化可焊焊盘上的隆起部分。
3.根据权利要求1的方法，其中构成主引线架的步骤包括：提供具有含多个导电引线第一子引线架的主引线架而多个导电引线包括凹入部分，让所述多个导电引线的暴露部分在密封以后从芯片级封装的边缘嵌出。
4.根据权利要求1的方法，其中构成主引线架的步骤包括：提供具有含多个导电引线第一子引线架的主引线架而多个导电引线包括隆起部分，并且其中把第一电子器件中的图形化可焊焊盘焊料安装到第一子引线架上的步骤包括焊料安装图形化可焊焊盘以使第一电子器件的边缘邻接隆起部分。
5.根据权利要求1的方法，其中提供主引线架的步骤包括：提供具有含多个导电引线第一子引线架的主引线架而多个导电引线包含用于容纳焊料块和焊料球其中之一的凹痕，该方法进一步包括把焊料块和焊料球其中之一安装到凹痕上。
6.根据权利要求1的方法，进一步包括使附属装置(an attachmentdevice)与第一电子器件的第二主表面联接并且与其中一条导电引线联接。
7.根据权利要求1的方法，其中构成第一和第二电子器件的步骤包括以下步骤：
形成在半导体晶片上面的多个导电层，其中最外面导电层包括可焊接金属；
使所述多个导电层图形化以提供多个图形化可焊焊盘；以及
把半导体晶片分割成分立的芯片以提供第一和第二电子器件。
8.一种用于形成密封在引线架上倒装芯片的半导体封装的工艺，包括以下步骤：
提供装有多个在第一主表面上形成的图形化可焊接结构的半导体芯片；
把图形化的可焊接结构安装到在引线架里的导电引线上而形成在引线架结构上的倒装芯片；和
用密封材料密封在引线架结构上的倒装芯片。
9.一种半导体封装，包括：
多个导电引线；
具有在电子器件第一主表面上面形成的多个图形化焊盘的电子器件，其中所述多个图形化焊盘中的每个图形化焊盘包含用作最外层的可焊接金属层，并且其中所述多个图形化焊盘是直接焊料安装到所述多个导电引线上；以及
覆盖电子器件和一部分导电引线的密封层，其中所述多个引线的另外部分是沿着半导体封装中的主表面暴露出的。
10.根据权利要求9的封装，其中可焊接金属层包括铜、银和金中之一。
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