CN1890807A - 半导体芯片封装 - Google Patents

半导体芯片封装 Download PDF

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Publication number
CN1890807A
CN1890807A CNA2004800367744A CN200480036774A CN1890807A CN 1890807 A CN1890807 A CN 1890807A CN A2004800367744 A CNA2004800367744 A CN A2004800367744A CN 200480036774 A CN200480036774 A CN 200480036774A CN 1890807 A CN1890807 A CN 1890807A
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China
Prior art keywords
chip
substrate
electric conducting
conducting material
trap
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CNA2004800367744A
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English (en)
Inventor
理查德·威尔森·阿诺德
马文·韦恩·考恩斯
查尔斯·安东尼·奥德加德
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Texas Instruments Inc
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Texas Instruments Inc
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Publication of CN1890807A publication Critical patent/CN1890807A/zh
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Abstract

一种半导体芯片封装包括一集成电路芯片(22)和一衬底(24)。一芯片接触衬垫(42)形成在所述芯片(22)的一第一侧(44)上。一接线柱(46)通过使用一导线绑定机而由引线形成于所述芯片接触衬垫(42)上。所述接线柱(46)具有一接合至所述芯片接触衬垫(42)的部分受挤压球部分(47)。所述接线柱(46)还具有一从所述部分受挤压球部分延伸的伸长部分。一第一绝缘材料层(48)位于所述衬底(24)的一第一侧(50)上。一有底阱(54)形成在所述第一层(48)中并在所述衬底(24)的所述第一侧(50)上开口。一第一导电材料(60)至少部分地填充所述阱(54)。所述第一导电材料(60)电连接至所述衬底(24)中的至少一条迹线(64)。所述接线柱(46)部分地嵌入所述第一导电材料(60)中，以在所述芯片(22)和所述衬底(24)之间形成一电连接。

Description

半导体芯片封装
技术领域
本发明大体涉及半导体芯片的封装。在一方面，更具体地说，本发明涉及以倒装芯片构型电连接至衬底的集成电路芯片。
背景技术
集成电路器件通常包括组装在封装中的半导体管芯或芯片。封装通常具有与芯片电连接的衬底部分。通常，衬底大于芯片，并且具有大于芯片的端子、引线或电接点，以便允许容易地将封装好的芯片电连接到电路板上(例如，在组装系统电路板时)。一种这样的封装构型是倒装芯片封装。
图1展示常规倒装芯片封装20的一个实例。在此实例中，芯片22通过焊料凸块阵列26电连接至衬底24。举例而言，此实例中的衬底24具有焊球阵列28(即，球栅阵列或BGA)，其可用于将封装好的芯片20附接到电路板(未图示)上。通常，在通过焊料凸块26将芯片22电连接至衬底24后，将底填材料30加到芯片22和衬底24之间的自由空间或间隙内。在图1中，略去了部分底填材料30，以便说明位于其中的一些焊料凸块26。在将芯片22电连接至衬底24并放置及固化底填材料30后的某一时间点，通常将盖帽32放置在芯片22的上方。为了说明的目的，图1中以双点划线展示盖帽32。除了保护封装20内的芯片22，此盖帽32可以(例如)由铝制成，并充当散热片以更好地冷却芯片22。
底填材料30的目的之一是使应力更均匀地分布在芯片22和衬底24之间，从而减小焊料凸块26、焊料凸块邦定点、和/或位于焊料邦定点上方/下方的电路层所受到的应力。这些应力至少部分是由芯片22、焊料凸块26和衬底24之间不同的热膨胀系数(即，热膨胀系数不匹配)引起的。举例而言，芯片22通常由硅晶片制成；衬底24通常由有机材料制成，其中延伸有铜线和通路；并且焊料凸块26通常由具有低熔点的金属化合物制成。因此，由于芯片22和衬底24之间具有不同的材料膨胀/收缩率，所以温度变化(例如，在芯片22使用过程中)会在将芯片22连接至衬底24的焊料凸块26上产生应力。底填材料30还可充当粘合剂，以有助于将芯片22保持在衬底24上，从而不仅仅是焊料凸块26将芯片22固持在适当位置。由此进一步降低施加在焊料凸块26上的应力。
使用焊料凸块制造和组装倒装芯片封装(例如，如上所述)要比其它将芯片附接到衬底的方法(例如，导线邦定法)昂贵。而且，使用导线邦定法形成的连接通常比使用焊料凸块形成的连接坚固。另外，许多制造设施已经有导线邦定机。但是，导线邦定法通常不适合于倒装芯片构型，并且一些制造商更喜欢倒装芯片构型。因此，需要提供一种使用导线邦定机并使用倒装芯片构型将芯片附接到衬底的方法。
发明内容
上述问题和需要可以通过本发明的实施例来解决。根据本发明的一个方面，提供一种半导体芯片封装，其包括集成电路芯片、芯片接触衬垫、接线柱和衬底。芯片接触衬垫形成在芯片的第一侧上。接线柱形成在芯片接触衬垫上。接线柱是通过使用导线邦定机而由导线形成。接线柱具有邦定至芯片接触衬垫的部分受挤压球部分。接线柱还具有从部分受挤压球部分延伸的伸长部分。衬底包括第一绝缘材料层、阱、第一导电材料和第二层。第一绝缘材料层位于衬底的第一侧上。阱形成在第一层中，并在衬底的第一侧上开口。阱具有底部。第一导电材料至少部分地填充阱。第二层中形成有导电迹线。第一导电材料电连接至这些迹线中的至少一条迹线。接线柱部分地嵌入在第一导电材料中，以在芯片和衬底之间形成电连接。芯片的第一侧面对衬底的第一侧。
根据本发明的另一方面，提供一种形成半导体芯片封装的方法。此方法包括本段中描述的以下步骤，步骤次序可以改变。提供一集成电路芯片。所述芯片包括形成于芯片第一侧上的芯片接触衬垫。提供导线邦定机中的导线。所述导线的尖端具有球形部分。用导线邦定机将导线的球形部分导线邦定到芯片接触衬垫上。所述球形部分在导线邦定过程中部分地受到挤压。切断所述导线，使得导线的伸长部分保持从所述部分受挤压球形部分延伸，以形成接线柱。提供一衬底，其包括第一绝缘材料层、阱、第一导电材料和第二层。第一绝缘材料层位于衬底的第一侧上。阱形成在第一层中，并在衬底的第一侧上开口。阱具有底部。第一导电材料至少部分地填充阱。第二层中形成有导电迹线。第一导电材料电连接至这些迹线中的至少一条迹线。接线柱的伸长部分的至少一部分浸没在第一导电材料中，以在芯片和衬底之间形成电连接。芯片的第一侧面对衬底的第一侧。
根据本发明的又一方面，提供一种半导体芯片封装，其包括集成电路芯片、芯片接触衬垫、接线柱、衬底和支撑部件。芯片接触衬垫形成在芯片的第一侧上。接线柱形成在芯片接触衬垫上。接线柱是通过使用导线邦定机而由导线形成。接线柱具有邦定至芯片接触衬垫的部分受挤压球部分。接线柱具有从部分受挤压球部分延伸的伸长部分。衬底包括第一绝缘材料层、阱、导电引线、第一导电材料和第二层。第一绝缘材料层位于衬底的第一侧上。阱形成在第一层中，并在衬底的第一侧上开口。阱具有底部。导电引线至少部分地引线于阱。第一导电材料至少部分地填充阱。第二层中形成有导电迹线。第一导电材料通过导电引线电连接至这些迹线中的至少一条迹线。支撑部件在芯片和衬底之间从衬底的第一层延伸。接线柱部分地嵌入第一导电材料中，以在芯片和衬底之间形成电连接。芯片的第一侧面对衬底的第一侧。芯片至少部分地由支撑部件支撑。
上文略述了本发明的相当广泛的特征，从而可以更好地理解以下对本发明的详细描述。下文将描述形成本发明权利要求书的主题的本发明的额外特征和优点。所属领域的技术人员应了解，所公开的概念和特定实施例可以容易地用作修改或设计其它用于实现本发明相同目的的结构或方法的基础。所属领域的技术人员还应认识到，这些均等构造并不背离随附权利要求书中所述的本发明的精神和范围。
附图说明
以下是对附图的简要说明，这些附图说明本发明的示范性实施例，其中：
图1是现有技术的倒装芯片封装的侧视图；
图2是根据本发明第一实施例的倒装芯片封装的侧视图；
图3是图2中的一部分的放大横截面图；
图4是根据本发明第二实施例的倒装芯片封装的侧视图；和
图5是图4中的一部分的放大横截面图。
具体实施方式
现参看附图，展示并描述本发明的说明性实施例，各图中，本文使用相同的附图标记来表示相同的元件。各图未必按比例绘制，在一些情况下，只是为了说明的目的，而适当地放大和/或简化附图。基于本发明的以下说明性实施例，所属领域的技术人员将了解本发明的许多可能的应用和变化。
图2和图3说明根据本发明第一实施例的半导体芯片封装20。图2是封装20的侧视图。如同图1，在图2中，为了说明接线柱40，略去了部分底填材料30。同样，为了说明的目的，图2中以双点划线展示盖帽32。在图2中，集成电路芯片22以倒装芯片构型电连接至衬底24。
图3是展示封装20的横截面的图2的放大部分。首先，将描述封装20的芯片部分。芯片接触衬垫42形成在芯片22的第一侧44上。芯片22的第一侧44面对衬底24。至少一些芯片接触衬垫42上邦定有接线柱40。接线柱40是通过使用导线邦定机(未图示)而由导线形成。在邦定之前，接线柱40开始时是从导线邦定机(未图示)送入的具有球形尖端(未图示)的导线，如同(例如)通常的导线邦定程序。导线的球形尖端通过导线邦定机邦定至其各自的芯片接触衬垫42。球形尖端至少部分地受到导线邦定机(例如，毛细管)的挤压。在将导线尖端邦定至芯片接触衬垫42后，拉出预定长度的导线，以提供接线柱40的伸长部分46。然后，导线邦定机切断导线以形成接线柱40，如(例如)图3所示。因此，接线柱40具有部分受挤压球部分47和伸长部分46。伸长部分46从部分受挤压球部分47延伸。重复此工序，直到在芯片22的第一侧44上形成所有接线柱40。一些或所有接线柱40可以同时(即，平行)形成，这可能取决于导线邦定机。
芯片接触衬垫42可以由多种合适材料中的任何材料制成，包括(例如，但不局限于)：金，铝，镍，钯，钨，铜，或其组合。接线柱40可以由多种合适材料中的任何材料制成，包括(例如，但不局限于)：金，银，铜，铝，铅，锡，焊料，及其组合。在邦定过程中，导线邦定机可以使用也可以不使用超声波能量，这至少部分取决于芯片接触衬垫42和接线柱40所用的材料。优选使用金作为接线柱40，且优选使用金作为芯片接触衬垫42的最外部的外露材料(因此，形成金-金邦定)。接线柱40和芯片接触衬垫42使用金的优点之一是，可以允许在低毛细管力下邦定；从而降低在邦定过程中施加在芯片22上的应力。在(例如)在芯片结构中实施弱的低-k介电材料的情况下，减小芯片上的应力正成为人们日益关注的问题。而且，金-金邦定可以少用或不用超声波能量和/或高热量来在接线柱40和芯片接触衬垫42之间形成邦定，这同样具有优势。在通过(例如)使用金-金邦定来降低施加在芯片22上的力的此种情况下，也可以将芯片接触衬垫42移到芯片22的中心部分；从而允许将芯片接触衬垫42放置在第一芯片侧44上的任何或几乎任何位置上。此可以允许每单位芯片面积具有更多的芯片接触衬垫42和/或允许芯片接触衬垫42之间具有更大的间隔。
仍参看图3，接下来描述封装20的衬底部分。第一绝缘材料层48提供于衬底24的第一侧50上，如图3所示。此第一层48可以是单层、复合层和/或多层。在图3中，为了说明的目的，将第一层48展示为单层。衬底24的第一侧50面对芯片22。阱54形成在第一衬底层48中，并在第一衬底侧50上开口。阱54具有底部56。在一优选实施例中，导电引线58至少部分地引线于至少一些阱54。例如，在图3中，展示导电引线58引线于每个阱54的壁和底部56。第一导电材料60至少部分地填充每个阱54。
第一衬底层48可以由多种合适材料中的任何材料制成，包括(例如，但不局限于)：有机材料(例如，在低成本衬底中常用的有机材料)，陶瓷，玻璃纤维，树脂，塑料，聚合物，及其组合。导电引线58可以由多种合适材料中的任何材料制成，包括(例如，但不局限于)：金属、铜、银、金、铝、钛、钽或其组合。在一优选实施例中，阱54具有形成于有机材料中的铜衬里58。
第一导电材料60可以是多种合适材料中的任何材料，包括(例如，但不局限于)：焊料，导电粘合剂，导电聚合物材料，金属化合物，或其组合。如果第一导电材料60使用焊料，那么优选允许(例如)小于90μm间距的超细间距焊料。可以将此类超细间距焊料(例如)丝网印刷到阱54中。另一优选焊料是(例如)Harima Chemicals的Super SolderTM，其可具有Sn、RCOO-Cu、RCOO-Ag和助焊剂的组合。但是，许多其它合适的焊料也可获得并可用于本发明的实施例。例如，在图3中，使用无铅焊料作为第一导电材料60。当使用焊料作为阱54中的第一导电材料60时，可以(例如)先将其沉积到阱54中，然后在将接线柱40插入到焊料中时通过加热衬底24来使其回流(即，加热到使得接线柱40可以穿过焊料)。
当使用导电粘合剂(例如，导电聚合物材料)作为阱54中的第一导电材料60时，可以(例如)先将其沉积到阱54中，然后在其固化前将接线柱40插入到第一导电材料60中。在一优选实施例中，导电粘合剂直到经过处理后才固化，以便提供充足的时间来插入接线柱40。此种处理可以通过(例如)加热粘合剂、在粘合剂中添加另一化学物质、将粘合剂暴露在某一气体或环境中、或其组合方法来提供。但是，在其它实施例中，导电粘合剂可以只是在一段指定时间固化。例如，在一优选实施例中，导电粘合剂在固化后仍保持指定量的柔度，以允许其中的接线柱40略微移动，从而消除热应力。在此或其它实施例中，包括在那些使用焊料作为第一导电材料60的实施例中，柔度也可以由跨越在芯片22和衬底24之间的导线接线柱46提供。柔度可以减轻由(例如)不同材料的不同CTE引起的应力。
当将芯片22电连接至衬底24时，如(例如)图3所示，接线柱40至少部分地嵌入阱54中的第一导电材料60中，以在芯片22和衬底24之间形成电连接。优选地，在将接线柱40插入在阱54中之前，接线柱40便已形成在芯片22上。同样，在将接线柱40插入在阱54中之前，阱54中优选填充有(或部分填充有)第一导电材料60。
在将接线柱40插入在阱54中的第一导电材料60中以使芯片22与衬底24互连后，可以在芯片22和衬底24之间提供底填材料30，如(例如)图2和图3所示。底填材料30可以是(例如)常规底填材料。
再次将目光集中在图3中的衬底24上，第二衬底层62位于第一衬底层48下方，其中形成有导电迹线64。至少一阱54的第一导电材料60电连接至第二衬底层62中的至少一条导电迹线64。因此，当阱衬里58覆盖阱54的底部56时，如图3所示，第一导电材料60通过阱衬里58电连接至一或多条迹线64。一实施例的衬底24可以具有一或多层导电迹线(例如，作为第二衬底层62)。例如，图3中展示了两层这样的层62，并且其间可以具有任意数量的额外层62。导电迹线64可以由多种合适材料中的任何材料制成，包括(例如，但不局限于)：金属铜、铝、金或其组合。包含导电迹线64的层62中可以使用绝缘材料(例如，有机材料)，如同(例如)衬底24中常规提供的那样。
通路68延伸至衬底24的第二侧70，并填充有第二导电材料72(例如，金属)，如图3所示。端子74位于第二衬底侧70上。导电通路68在端子74和导电迹线64之间提供电连接。端子74上可以形成有焊球28，以提供球栅阵列结构，如(例如)图2和图3所示。因此，例如，在图3的实例中，展示于第二衬底侧70上的焊球28通过接线柱40、填充有第一导电材料60的阱54、至少一条导电迹线64、导电通路材料72和端子74电连接至芯片22上的接触衬垫42中的一个接触衬垫42。
注意，在图3中，一些或所有接线柱40可以搁在阱54的底部56上，这取决于接线柱40的插入深度和接线柱长度的一致性。芯片22可以临时固持在衬底24上方，使得在将接线柱40插入到阱54中后且在第一导电材料60固化或冷却至固态时，很少或没有接线柱40碰到阱底部56。
图4和图5说明根据本发明第二实施例的半导体芯片封装20。第二实施例类似于第一实施例(见图2和图3)，其不同之处在于第一导电材料60的选择有所改变，并且提供了支撑部件80(见图4和图5)。图4是第二实施例的封装20的侧视图。如同图1和图2，在图4中，为了说明接线柱40和支撑部件80，略去了部分底填材料30。图5是更详细地展示封装20的横截面的图4中的放大部分。
参看图5，在此实例中，展示支撑部件80从第一衬底层48延伸。支撑部件80可以是第一衬底层48的一个整体零件。在另一实施例中，支撑部件80可以形成和/或附接在第一衬底层48上。在又一实施例中，支撑部件80可以是芯片22的一部分，也可以从芯片22延伸，和/或可以附接在芯片22上。支撑部件80所用的材料可以选自多种合适材料中的任何材料，包括(例如，但不局限于)：聚合物，有机材料，金属，塑料，陶瓷，玻璃纤维，树脂，硅，和其组合。优选地，所有支撑部件80都具有相同高度。但在其它实施例中，例如，支撑部件80不必都具有相同高度(例如，使芯片22相对于衬底24倾斜)。
在一优选构型中，芯片22搁在支撑部件80上，并且至少部分地由支撑部件80支撑。在接线柱40不具有一致长度的情况下，使用支撑部件80具有优势。而且，通过使芯片22搁在支撑部件80上，可以通过支撑部件80的高度、而不是接线柱40的长度和/或阱54的深度来控制芯片22和衬底24之间的距离。在图5所示的实例构型中，支撑部件80的高度相对于阱54的深度和平均接线柱长度的关系使得接线柱40不接触阱底部56。因此，在将接线柱40浸没在第一导电材料60中后在第一导电材料60固化或冷却至固态之前，芯片22可以完全由支撑部件80支撑。在第一导电材料60凝固并在芯片22和衬底24之间放置底填材料30后，第一导电材料60和底填材料30也可以帮助支撑芯片22及将芯片22固持在适当位置。尽管图2-5的第一和第二实施例中展示了底填材料30，但在其它实施例(未图示)中，也可以没有底填材料，因为可能不需要和/或不理想。由此可以提供结构中减轻应力的额外柔度。
所属领域的技术人员应了解，支撑部件80的高度、形状、放置和数量可以因本发明的实施例而异。同样，阱54的深度和宽度(或直径)也可以因本发明的实施例而异。阱54的横截面形状也可以有所变化，包括(例如，但不局限于)圆形、椭圆形、正方形、长方形或具有圆角。并且，导线尺寸、球尺寸和接线柱长度也可以因本发明的实施例而异。作为一说明性实例，阱54可以具有约200μm的深度和约100μm的直径，接线柱40可以具有约50μm的导线直径和约300μm的长度，并且支撑部件80可以具有约150μm的高度。因此，例如，在此情况下，第一芯片侧44和第一衬底侧50之间的间距可以约为150μm，接线柱40的尖端距阱底部56的距离将为约50μm，并且将有约150μm的接线柱40浸没在第一导电材料60中(假设在此情况下，在插入接线柱40后，第一导电材料60填充阱54)。在其它实施例中，例如，接线柱40的长度可以介于约50μm和约300μm之间，并且导线直径可以介于约30μm和约50μm之间。
放置在每个阱54中的第一导电材料60的量可以有所变化，以使得在插入接线柱40后，阱54中充满、未充满或充溢有第一导电材料60。如果在阱中插入接线柱40后第一导电材料60过度填充阱54，那么过量的第一导电材料60部分将可能粘附在衬底表面上方的接线柱40的侧面上并润湿侧面；从而避免过量的第一导电材料60部分散布在第一衬底侧50上，此散布可能会引起不良短路。因此，第一导电材料60对接线柱40的这种润湿或灯芯效应(wicking)可以是本设计的一个优选且有利的特征。在一优选实施例中，第一导电材料60刚好充满阱54(例如，见图3和图5)或刚好略微过度充满阱54(对接线柱40起灯芯效应)，使得接线柱40和第一导电材料60之间的接触面积最大。但在其它实施例中，在插入接线柱40后，第一导电材料60的量可能未填满阱54。如同第一实施例，第一导电材料60可以是(例如)焊料。
在一优选实施例中，衬底可以是(例如)具有其中形成有阱54的较厚第一衬底层48(例如，而不是凸块着陆衬垫)的低成本衬底24。而且，在其它实施例(未图示)中，衬底24可以不同于BGA的构型，例如具有从衬底的第二衬底侧70或其它侧延伸的引脚或引线的衬底24。得益于本公开内容，在并入本发明实施例中的有底阱54时，所属领域的技术人员将能实现对衬底设计的许多其它改变。而且，所属领域的技术人员将明白，芯片22上的芯片接触衬垫42(且因此涉及接线柱40)的放置和阵列构型可以作很大变化。
本发明的实施例的另一个优点是，可以明显减少焊料凸块构型(例如，见图1)中焊料邦定点上常遇到的应力集中。这些应力通常是由芯片22、焊料凸块26(例如，见图1)和衬底24之间的热膨胀系数(CTE)不匹配引起的。在本发明的实施例提供的结构构型下，这种CTE不匹配的影响可以有所减小，并且施加在芯片22上的邦定点上的应力也可以有所减小，和/或实施例的结构能够处理高得多的应力(与焊料凸块构型相比)。而且，当芯片22在金属间介电层中包含弱介电材料(例如，低k及超低k介电材料)(这越来越普遍)时，减小芯片上由CTE不匹配和其它应力源引起的应力显得很重要。接线柱40可以允许比焊料凸块大的横向柔度，此将有助于减轻由CTE不匹配引起的热应力，而不是只将应力传递给芯片22。因此，接线柱40优选由柔性材料(例如金)而不是由刚性材料制成。
尽管图2-5的第一和第二实施例中将接线柱46展示及描述为由最初具有球形尖端的导线形成，但在其它实施例(未图示)中，导线尖端的初始形状可以有所不同。例如，在切断以形成之前的接线柱后，初始导线尖端可以具有不特定形成的形状。接线柱可以用(例如)楔形邦定形成在芯片接触衬垫上。或者，例如，导线尖端的初始形状可以形成为某一其它形状(即，不同于球形的形状)。得益于本公开内容，所属领域的技术人员可以实现接线柱46的其它可能的变化。
尽管上文详细描述了本发明的实施例及其优点，但应了解，在不背离由随附权利要求书限定的本发明的精神和范围的前提下，可以对本发明做出各种改变、替换和变更。此外，不希望本申请案的范围局限于本说明书中描述的物质、手段、方法和步骤的工艺、机器、制造、组成的特定实施例。从本发明的公开内容，所属领域的技术人员将容易地明白，可以根据本发明利用目前已有或稍后将开发的用于执行与本文所述的对应实施例大体相同的功能或实现大体相同的结果的物质、手段、方法或步骤的工艺、机器、制造、组成。因此，希望随附权利要求书的范围内包括这些物质、手段、方法或步骤的工艺、机器、制造、组成。

Claims (20)

1.一种半导体芯片封装，包含：
一集成电路芯片；
一形成在所述芯片的一第一侧上的芯片接触衬垫；
一形成在所述芯片接触衬垫上的接线柱，所述接线柱是通过使用一导线邦定机而由导线形成，所述接线柱具有一从所述芯片接触衬垫延伸的伸长部分；
一衬底，包含：
一位于所述衬底的一第一侧上的第一绝缘材料层，
一形成在所述第一层中并且在所述衬底的所述第一侧上开口的阱，所述阱具有
一底部，
一至少部分地填充所述阱的第一导电材料，和
一其中形成有导电迹线的第二层，其中所述第一导电材料电连接至所述迹线中的至少一条迹线；并且
其中所述接线柱部分地嵌入在所述第一导电材料中以在所述芯片和所述衬底之间形成一电连接，并且其中所述芯片的所述第一侧面对所述衬底的所述第一侧。
2.如权利要求1所述的半导体芯片封装，进一步包含：
一至少部分地引线于所述阱的导电引线，其中所述阱中的所述第一导电材料通过所述导电引线电连接至所述至少一条迹线。
3.如权利要求1所述的半导体芯片封装，其中所述导电引线包含铜。
4.如权利要求1所述的半导体芯片封装，其中所述接线柱包含金，且其中所述接触衬垫的最外部表面包含金。
5.如权利要求1所述的半导体芯片封装，其中所述第一衬底层的所述绝缘材料包含有机材料。
6.如权利要求1所述的半导体芯片封装，其中所述第一导电材料包含焊料。
7.如权利要求1所述的半导体芯片封装，其中所述第一导电材料包含导电粘合剂。
8.如权利要求1所述的半导体芯片封装，其中所述衬底进一步包含：
两层或两层以上其中形成有导电迹线的层，
一与所述第一侧相对的第二侧，
一位于所述第二侧上的端子，
一填充有一第二导电材料的通路，其中所述端子电连接至所述通路中的所述第二导电材料，其中所述第二导电材料电连接至所述导电迹线中的至少一条导电迹线，并且其中所述端子通过所述接线柱、所述第一导电材料、所述导电迹线中的至少一条导电迹线和所述第二导电材料电连接至所述芯片接触衬垫。
9.如权利要求1所述的半导体芯片封装，进一步包含：
一在所述芯片和所述衬底之间从所述衬底的所述第一层延伸的支撑部件，其中所述芯片至少部分地由所述支撑部件支撑。
10.如权利要求9所述的半导体芯片封装，其中所述支撑部件包含聚合物材料。
11.如权利要求1所述的半导体芯片封装，进一步包含位于所述芯片和所述衬底之间的底填材料。
12.如权利要求1所述的半导体芯片封装，其中所述接线柱具有一接合至所述芯片接触衬垫的部分受挤压球部分，且其中所述伸长部分从所述部分受挤压球部分延伸。
13.一种形成一半导体芯片封装的方法，包含：
用一导线邦定机将一导线导线邦定到一集成电路芯片的一第一侧上的一芯片接触衬垫上；
切断所述导线，使得所述导线的一伸长部分保持从所述芯片接触衬垫延伸以形成一接线柱；
将所述接线柱的所述伸长部分的至少一部分浸没在一第一导电材料中，以在所述芯片和一衬底之间形成一电连接，其中所述第一导电材料形成于一阱中，其中所述阱形成于所述衬底的一第一层中，其中所述阱在所述衬底的一第一侧上开口，其中所述阱具有一底部，其中所述第一导电材料电连接至一形成于所述衬底的一第二层中的迹线，其中所述第一衬底层位于所述第二衬底层的上方，并且使得所述芯片的所述第一侧面对所述衬底的所述第一侧。
14.如权利要求13所述的方法，其中所述导线在所述导线邦定之前具有一球形尖端，且其中所述球形尖端在所述导线邦定过程中部分地受到挤压而抵靠在所述芯片接触衬垫上。
15.如权利要求13所述的方法，其中所述第一导电材料包含导电粘合剂，且其中所述方法进一步包含：
用所述第一导电材料至少部分地填充所述阱；和
在所述浸没之后固化所述第一导电材料。
16.如权利要求13所述的方法，其中所述第一导电材料包含焊料，且其中所述方法进一步包含在所述浸没之前至少部分地熔融所述焊料。
17.一种半导体芯片封装，包含：
一集成电路芯片；
一形成在所述芯片的一第一侧上的芯片接触衬垫；
一形成在所述芯片接触衬垫上的接线柱，所述接线柱具有一从所述芯片接触衬垫延伸的伸长部分；
一衬底，包含：
一位于所述衬底的一第一侧上的第一绝缘材料层，
一形成在所述第一层中并且在所述衬底的所述第一侧上开口的阱，所述阱具有一底部，
一至少部分地引线于所述阱的导电引线，
一至少部分地填充所述阱的第一导电材料，和
一其中形成有导电迹线的第二层，其中所述第一导电材料通过所述导电引线电连接至所述迹线中的至少一条迹线；和
一在所述芯片和所述衬底之间从所述衬底的所述第一层延伸的支撑部件，其中所述接线柱部分地嵌入在所述第一导电材料中以在所述芯片和所述衬底之间形成一电连接，其中所述芯片的所述第一侧面对所述衬底的所述第一侧，并且其中所述芯片至少部分地由所述支撑部件支撑。
18.如权利要求17所述的半导体芯片封装，其中所述接线柱具有一邦定至所述芯片接触衬垫的部分受挤压球部分，且其中所述伸长部分从所述部分受挤压球部分延伸。
19.如权利要求17所述的半导体芯片封装，其中所述第一导电材料包含焊料。
20.如权利要求17所述的半导体芯片封装，其中所述第一导电材料包含导电粘合剂。
CNA2004800367744A 2003-12-30 2004-12-21 半导体芯片封装 Pending CN1890807A (zh)

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