CN1838157A - 射频识别标签 - Google Patents
射频识别标签 Download PDFInfo
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- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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Abstract
一种射频识别标签,其包括:基体;设置在基体上用以形成通讯天线的天线模式,该天线模式具有为天线提供一个连接端的渐缩形连接端部;一连接至该天线模式的连接端部上的电导体,该电导体比该连接端部小;以及一通过电导体与天线模式进行电连接的电路芯片,该电路芯片利用天线进行无线电通讯。
Description
技术领域
本发明涉及一种可以与外部设备以非接触方式进行信息交换的RFID(射频识别)标签。顺便提及,在与本申请相关的技术领域中的技术人员中,将“射频识别标签”视为“射频识别标签”的一个内部的组成构件(嵌体(inlay)),从而本申请说明书中所用的“射频识别标签”一词有时可能称为“射频识别标签的嵌体”。或者,在某些情况下,“射频识别标签”可以被称为“无线电IC标签”。此外,非接触类型的IC卡也包括在这个“射频识别标签”当中。
背景技术
近些年来,出现了多种射频识别标签,这些射频识别标签利用无线电波以非接触方式,与以读数器/记录器为代表的外部设备进行信息交换(例如参见美国专利:US6239703B1)。作为这种射频识别标签的一种,已经提出了这样一种射频识别标签:用作无线电通信的天线模式(antenna pattern)和IC(集成电路)芯片被固定在由塑料或纸制成的基片上。这种类型的射频识别标签的构思模式是这样的:射频识别标签被连在一个物品或类似的东西上,并与外部设备交换关于该物品的信息以该物品进行识别。
在这种射频识别标签中,通过在该电路芯片以及该天线模式的末端部分之间压紧一个被称作凸块(bump)的微电子导体,将电路芯片和天线模式电连接。该电路芯片被固定在上述的基片上,并且此时,电路芯片和天线模式的末端部分之间除了被凸块占据的区域以外的地方用胶加以填充。结果,电路芯片和天线模式的末端部分成为电极,从而就形成了一个微型电容器。这种从设计角度来说没有必要的电容器的电容量叫做寄生电容量,在射频识别标签中寄生电容量有下文所述的不利作用。
有一种从外部设备获得内置电路芯片工作电力的射频识别标签。在该种射频识别标签中,从外部设备输入的电力通过天线模式供给电路芯片。此时,当相互电连接的电路芯片和天线模式的末端部分之间有寄生电容量存在时,从天线模式到电路芯片的工作电力的输入就会受到干扰。结果,可能出现因为工作电力不足而引起诸如射频识别标签通讯距离缩短(deterioration)这样的问题。
因此,出现了一种技术,其在天线模式侧设置一种调整模式,该调整模式能够通过蚀刻等作用来改变阻抗,并通过该调整模式来调整包括上述的天线模式末端和电路芯片之间的寄生电容量的阻抗。(例如参见美国专利US6535175B2)
然而,这种调节工作存在着生产率比较低的问题。
因此,消除上述射频识别标签中的寄生电容量的措施经常涉及到预测寄生电容量,并在天线模式的一侧提供能产生电感的模式(pattern),这种电感通过电路谐振抵消寄生电容的电容量。
上述的射频识别标签中的寄生电容量的预测是在夹着上述凸块的电路芯片和天线模式的末端部分的重叠区域(重叠部分)的基础上进行的。
然而,上述电路芯片和天线模式之间的位置关系在射频识别标签生产时千变百化,很难有一种稳定的方式来预测寄生电容量。而且,即使超出上述条件的限制确定了寄生电容量,并且在寄生电容量的基础上会有一个电感,那么在实际寄生电容量与预测寄生电容量不同的情况下,也不可能确保实际寄生电容量和阻抗之间的匹配,从而上述的谐振也就不可能产生了。结果,寄生电容没有消除,其仍旧伴随有上述的射频识别标签通讯距离缩短或类似问题。
发明内容
考虑到上述情况,本发明提供了一种射频识别标签,其制造生产率高,并且避免通讯距离缩短。
本发明公开了一种射频识别标签,该射频识别标签包括:
基体;
天线模式,其设置在该基体上以形成通讯天线,并且该天线模式具有为该天线提供连接端的渐缩形连接端部;
电导体,其连接在该天线模式的该连接端部上,并且该电导体比该连接端部小;以及
电路芯片,其通过该电导体与该天线模式电连接,并且该电路芯片利用该天线进行无线电通讯。
在本发明的射频识别标签中,“该天线模式具有电感产生部,该电感产生部产生与该连接端部和该电路芯片之间的电容相匹配的电感,并且防止由于该电容引起天线性能的下降”的形式是代表性形式。
在本发明的射频识别标签中,电路芯片悬在所述天线模式的连接端部的上方,并且电导体被夹在中间。结果,电路芯片和天线模式的连接端部相互重叠,并且两者之间有一个放置电导体的距离。在两者之间相互重叠的部分(重叠部分)中除了电导体以外的区域,形成了从设计角度来说不必要的电容器,此时相对的电路芯片和连接端部用作电极。该电容器的电容量(寄生电容量)与重叠部分的面积成比例,与处于该重叠部分内的电路芯片和天线模式的连接端部之间的距离成反比。
顺便提及,在制造本发明的射频识别标签时,通常采用的方法是将电导体连在电路芯片上,然后,在电路芯片被挤紧在基片上时将电路芯片加热,以确保电导体连接在天线模式的连接端部上。采用该方法时,电导体与连接端部的一部分一起嵌入基片中。
在电路芯片以向连接端部的顶端侧移动的方式安装的情况下,重叠部分的面积变小了(区域变窄了),相应的寄生电容量也与该变窄而成比例地变小了。此时,电导体连接到连接端部的位置朝着连接端部的顶端侧移动。并且,因为连接端部是渐缩形的,它的强度向着顶端方向递减,电导体深深地插进基片中,结果,在重叠部分中的电路芯片和天线模式的连接端部之间的距离变小(变窄)了,寄生电容量与该距离的减小成反比例地增加。这样,上述的变大和变小相互抵消,因此,即使是电路芯片的安装位置移向连接端部的顶端侧,寄生电容量也很少有变化。
另一方面,在电路芯片以向连接端部的底边移动的方式安装时,与上述情况相反,重叠部分的面积变大(区域变宽),并且在重叠区域内的电路芯片和天线模式的连接端部之间的距离也变大(变宽)。结果,寄生电容量随着重叠部分面积增加(变宽)而成比例地增加,并且随着电路芯片和连接端部之间的距离增加而成反比例地减小,两者相互抵消。因此,即使是电路芯片的安装位置移向该连接端部的底边时,寄生电容量也很少发生变化。
如上所述,在本发明的射频识别标签中,为了制造的原因,寄生电容量很稳定,因此,寄生电容量可以用一种稳定的方法来预先确定。结果,可以采取一种无需给制造工艺增加负担并且具有高生产率的措施,作为与寄生电容量有关的措施,例如,提供一种具有电感产生部分的天线模式,该电感产生部分能产生根据预定的寄生电容量确定的电感。换句话说,根据本发明,可以得到一种既具有高生产率又避免通讯距离缩短的射频识别标签。
如上所述,根据本发明,可以得到一种既能以高生产率生产又避免通讯距离缩短的射频识别标签。
附图说明
下面将在下述附图的基础上详细描述本发明的优选实施例,其中:
图1(A)和图1(B)分别为本发明第一实施例的主视图和侧视图;
图2为表示图1中天线模式的垫片形状的放大图;
图3(A)和图3(B)分别是在电路芯片以从标准位置移向三角形垫片的顶端的方式安装的情况下,基片附近区域的放大主视图和放大侧视图;
图4(A)和图4(B)分别是在电路芯片以从标准位置移向三角形垫片的基体一侧的方式安装的情况下,基片附近区域的放大主视图和放大侧视图;
图5为显示本发明第二实施例的射频识别标签中天线模式的形状的放大图;
图6为显示本发明第三实施例的射频识别标签中天线模式的形状的放大图。
具体实施方式
图1(A)和图1(B)分别为本发明第一实施例的主视图和侧视图。然而,在所示的主视图当中,从射频识别标签的前方看到其内部结构;在所示的侧视图当中,从射频识别标签的侧面看到其内部结构。
如图1(A)和图1(B)所示的射频识别标签1包括:位于基片2上的天线模式3;电路芯片4,其用环氧树脂胶8粘在基片2上并通过凸块6与天线模式电连接;电感模式5,其与天线模式3电连接并且产生电感;盖片7,其覆盖所述天线模式3、电路芯片4以及电感模式5,并且粘在基片2上。所述盖片7通常由从PET材料、聚酯材料、聚烯烃材料、聚碳酸酯材料、聚丙烯材料中选择的材料制成。
在第一实施例中,上述的基片2、电路芯片4和凸块6分别相当于本发明的基体、电路芯片和电导体的例子。并且,天线模式3和电感模式5的结合相当于根据本发明的天线模式的例子,电感模式5相当于本发明的电感产生部的例子。
射频识别标签1利用天线模式3接受由读数器或记录器所释放的电磁场能量作为电能,并且电路芯片4被该电能所驱动,因此通信就得以实现。
该射频识别标签1通过下述步骤得到。首先,将凸块6连接于电路芯片4上。在电路芯片4侧的天线模式3的末端设有使天线模式3与其它部分电连接的垫片3a。与凸块6连接的电路芯片4紧紧压在基片2上,以确保该凸块6连接在垫片3a上,同时,用胶8固定电路芯片4并且加热该电路芯片。
该天线模式3在电路芯片4侧的末端部分设有一个垫片3a,以通过凸块6使天线模式3与电路芯片4电连接;并且,该垫片3a和电路芯片4以在两者之间将凸块6夹住的方式部分地相互重叠,并且两者之间有一个凸块6的距离。在两者相互重叠的部分(重叠部分),除了凸块6以外的区域用胶8加以填充,结果在上述的重叠部分就形成了从设计角度来说不必要的电容,垫片3a和电路芯片4就成了电极。该电容的电容量(寄生电容量)妨碍了从天线模式3到电路芯片4的能量输入,引起诸如射频识别标签1的通讯距离缩短这样的问题。因此,本实施例的构思是:通过设置在由天线模式3侧的电感模式5在电感和上述的寄生电容量之间产生谐振,从而消除了该寄生电容量。
在本实施例中,假设电路芯片4安装在所设计的标准位置,则根据在电路芯片4和垫片3a的重叠部分产生的寄生电容量(标准电容量),利用下面的等式(1)就能够得到电感(inductance)。在等式(1)中,“L”是电感,“C”是标准电容量,“f”是谐振频率。
(2∏f)2=1/(L×C) ……… (1)
假设电路芯片4安装在标准位置,则利用下面的等式(2)就可以得到标准电容量C,其中电路芯片4和垫片3a的重叠部分的面积被表示为“S”,电路芯片4和垫片3a之间的距离(标准距离)被表示为“D”,胶8的介电常数被表示为“ε”。
C=ε×S/D ………(2)
因为制造精度等原因,电路芯片4的安装位置有各种变化,因此垫片3a和电路芯片4之间的重叠部分的面积与上述的标准面积S之间有一些误差。如果重叠部分的实际面积与标准面积S不同,则射频识别标签1中产生的实际的寄生电容量也与标准电容量C不同。因此,即使根据标准电容量C得到了电感L,也不可能使由根据等式(1)所得到的实际寄生电容量与电感L之间匹配,因此有可能寄生电容量不能被消除。因此,在本实施例中,即使电路芯片4的安装位置发生了变化,为了确保实际的寄生电容量与标准电容量C基本上相同,即,为了制造的原因要使寄生电容量被稳定在标准电容C,可以对天线模式3的垫片3a的形状进行如下设计。
图2为表示图1中天线模式的垫片形状的放大图。
图2显示了在本实施例中临近射频识别标签1中的天线模式3的垫片3a的区域的放大图。如图2所示,垫片3a为三角形,其顶端朝着电路芯片4。该垫片3a的3a-1部分与电路芯片4重叠。上述的寄生电容量就产生于该重叠部分。垫片3a的三角形相当于本发明的“渐缩形(tapered shape)”的例子。
即使是在电路芯片4的安装位置发生变化的情况下,图2所示的三角形的垫片3a也可以作为一种使寄生电容量稳定在标准电容C的水平上的设计方案,从该垫片3a所得的有益效果将在下文中加以解释。
图3(A)和图3(B)分别是当电路芯片以从标准位置移向三角形垫片的顶端侧的方式安装时,基片附近区域的放大主视图和放大侧视图。在此放大侧视图当中,可以透过侧面看到射频识别标签1中的垫片附近的内部结构。在本说明书当中,所有叫做放大侧视图的附图都是类似的。
如图3(A)的放大主视图所示,当电路芯片4以从标准位置P移向三角形垫片3a的顶端侧的方式安装时,电路芯片4和垫片3a之间的重叠部分的面积(窄于)小于在电路芯片4安装在标准位置P的情况下重叠部分的面积(即标准面积S)。
如上所述,电路芯片4紧贴在基片2上,并且凸块6夹在二者之间。结果,如在图3(B)的放大侧视图所示,凸块6受到了电路芯片4的压力,凸块6与垫片3a的一部分一起嵌在基片2当中。
同样,凸块6首先被粘在电路芯片4上。因为这个原因,当电路芯片4以从标准位置P移向三角形垫片3a的顶端侧的方式安装时,如图3(A)和图3(B)所示,与电路芯片4被安装在标准位置P相比,凸块6与临近垫片3a的顶端的部分连接。因为此时垫片3a具有三角形的形状,所以垫片3a中的用于放置凸块处的宽度W1与电路芯片4设置在标准位置P时垫片3a中的用于放置凸块处的宽度W相比变窄了。结果,与电路芯片4设置在标准位置P时对凸块6的支撑力相比,垫片3a支承凸块6的部分的力变弱了;与电路芯片4设置在标准位置P的情况相比,凸块6在基片2中嵌入更深。所以,在电路芯片4和垫片3a的重叠部分中,电路芯片4和垫片3a之间的距离D1小于电路芯片4设置在标准位置P时电路芯片4和垫片3a之间的距离(即距离D)。
当电路芯片4以从标准位置P移向三角形垫片3a的顶端侧的方式安装时,就如上文所述和在图3(A)和图3(B)所表示的例子那样,重叠部分的面积与标准面积S相比变小(变窄)了。根据上文中的等式(2)显然可以得出,重叠部分的寄生电容量与重叠部分的面积成比例,因此,上述的重叠部分面积的缩小将寄生电容量降低到了小于标准电容量C的水平。另外,根据等式(2)显然可以得出,寄生电容量与电路芯片4和垫片3a之间的距离成反比,因此,电路芯片4和垫片3a之间距离的缩短将寄生电容量增加到了大于标准电容量C的水平。最终,由于重叠部分面积的减少而引起的寄生电容量的减少被由于电路芯片4和垫片3a之间的距离的缩短引起的寄生电容量的增加所抵消。也就是说,即使电路芯片4以从标准位置P移向三角形垫片3a的顶端侧的方式安装,如在图3(A)和图3(B)所表示的例子那样,重叠部分的寄生电容量也几乎与标准电容量C相等。
下面,将对与图3(A)和图3(B)所表示的例子相反的情况进行描述,此时电路芯片4以移向三角形垫片3a底边的方式安装。
图4(A)和图4(B)分别是当电路芯片以从标准位置移向三角形垫片的底边的方式安装时,基片附近区域的放大主视图和放大侧视图。
在图4(A)和图4(B)所示的情况下,如图4(A)的放大主视图所示,电路芯片4和垫片3a的重叠部分的面积(宽于)大于电路芯片4设置在标准位置P时重叠部分的面积(即,上述的标准面积S)。另一方面,在这种情况下,在放置凸块6的部分的宽度W2宽于电路芯片4设置在标准位置P时放置凸块6的部分的宽度W。因此,与电路芯片4设置在标准位置P时获得的力相比,支承凸块6的垫片3a的部分的力变大了;并且,与电路芯片4设置在标准位置P时相比,凸块6在基片2中嵌入得比较浅。于是,在电路芯片4和垫片3a的重叠部分中,电路芯片4和垫片3a之间的距离D2变得大于上述的标准距离D。重叠部分面积的增大(变宽)将寄生电容量增加到了大于标准电容量P的水平;电路芯片4和垫片3a之间距离的变大将寄生电容量减小到了小于标准电容量C的水平。最终,由于重叠部分面积的增加而引起的寄生电容量的增加被由于电路芯片4和垫片3a之间的距离的变大所引起的寄生电容量的减小所抵消。也就是说,即使电路芯片4以从标准位置P移向三角形垫片3a的基体一侧的方式安装时,如图4(A)和图4(B)所示的例子,寄生电容量也几乎与标准电容量C相等。
参照图3(A)和图3(B)以及图4(A)和图4(B),如上所述,在本发明实施例的射频识别标签1中,即使电路芯片4的安装位置从上述标准为指P移向三角形垫片3a的顶端侧或者底边移动时,寄生电容量也几乎与标准电容量C相等。即,在本发明实施例的射频识别标签中,为了制造的原因,寄生电容量稳定在标准电容量C的水平,因此,在标准电容量C的基础上得到的电感L可以有效地作用。用这种方式,在本实施例的射频识别标签1中,在设计阶段就可以得到有效的电感L。因此在制造阶段,就没有必要进行诸如调整电感的烦锁的工作,唯一必须的是需要制造所设计的电感模式。因此,可以高生产率地制造本实施例的射频识别标签1,并且避免了由于寄生电容量导致通讯距离缩短。
顺便提及,本发明中的“渐缩形”并非限制在上述第一实施例中的三角形,其可以是下述的形状。
在下文中,将描述第二实施例和第三实施例,这两个例子中的垫片形状与第一实施例的垫片形状不同。然而,这些实施例仅在垫片形状方面与第一实施例不同,因此,下文将着重描述与第一实施例不同的地方。
图5为显示本发明第二实施例的射频识别标签中天线模式的形状的放大图。顺便提及,在图5中,类似的附图标记表示与上述第一实施例中的构件类似的部件。
在图5所示的射频识别标签9中,安装有凸块6的天线模式10的垫片10a为具有圆形顶端的渐缩形。在该实施例当中,垫片10a的这个形状产生的效果与第一实施例中垫片3a的三角形状产生的效果相同;并且,电路芯片4安装位置的变化所导致的寄生电容量的变化受到抑制,结果是:为了制造的原因,寄生电容量就变得稳定了。
图6为显示本发明第三实施例的射频识别标签中天线模式的形状的放大图。同样在图6中,类似的附图标记表示与上述第一实施例中的构件类似的部件。
在如图6所示的射频识别标签11中,安装有凸块6的天线模式12的垫片11a具有宽度朝向电路芯片4侧以阶梯状递减的渐缩形。在该实施例中,垫片12a的这个形状产生的效果与第一实施例中垫片3a的三角形状以及第二实施例中具有圆形顶端的三角形垫片10a的渐缩形的效果相同;并且,电路芯片4安装位置的变化所导致的寄生电容量的变化被抑制了,结果是:为了制造的原因,寄生电容量就变得稳定了。
如上所述,根据第一到第三实施例的射频识别标签,不管电路芯片的安装位置怎么变化,寄生电容量是稳定的;因此,在设计阶段就能获知用以有效消除寄生电容量的电感。结果,避免了在制造过程中诸如调整电感等烦锁的工作,从而使高生产率的制造成为可能。也就是说,可以高生产率地制造第一到第三实施例中的射频识别标签,同时避免了由寄生电容量导致通讯距离缩短。
在前文中,如本实施例的天线模式的例子那样,上文对有三角形垫片3a的天线模式3,对具有圆形顶端的渐缩形垫片10a的天线模式10,以及对具有宽度朝着电路芯片侧以阶梯状递减的渐缩形垫片12a的天线模式12这三个例子进行了描述。然而,本发明并非局限于此。任何具有朝着顶端宽度变窄的天线模式都可以作为本发明的天线模式,而不论其垫片的形状如何。
Claims (2)
1.一种射频识别标签,其包括:
基体;
天线模式,其设置在该基体上以形成通讯天线,并且该天线模式具有为该天线提供连接端的渐缩形连接端部;
电导体,其连接在该天线模式的该连接端部上,并且该电导体比该连接端部小;以及
电路芯片,其通过该电导体与该天线模式电连接,并且该电路芯片利用该天线进行无线电通讯。
2.根据权利要求1所述的射频识别标签,其中,该天线模式具有电感产生部,该电感产生部产生与该连接端部和该电路芯片之间的电容相匹配的电感,并且防止由于该电容引起天线性能的下降。
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2005
- 2005-03-22 JP JP2005081398A patent/JP2006268090A/ja not_active Withdrawn
- 2005-05-27 EP EP05253314A patent/EP1708127A3/en not_active Withdrawn
- 2005-05-30 TW TW094117645A patent/TWI301244B/zh active
- 2005-06-02 US US11/142,356 patent/US7298273B2/en not_active Expired - Fee Related
- 2005-06-14 KR KR1020050050736A patent/KR100642617B1/ko not_active IP Right Cessation
- 2005-06-17 CN CNB2005100785898A patent/CN100412898C/zh not_active Expired - Fee Related
-
2006
- 2006-06-19 US US11/454,848 patent/US20060244600A1/en not_active Abandoned
-
2007
- 2007-10-10 US US11/907,289 patent/US20080040913A1/en not_active Abandoned
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101251904B (zh) * | 2007-02-22 | 2012-05-30 | 富士通株式会社 | 无线射频标签和用于制造无线射频标签的方法 |
CN104395915A (zh) * | 2011-12-07 | 2015-03-04 | Rfid技术有限公司 | Rfid及其装置和方法 |
Also Published As
Publication number | Publication date |
---|---|
US20080040913A1 (en) | 2008-02-21 |
EP1708127A2 (en) | 2006-10-04 |
EP1708127A3 (en) | 2007-05-30 |
KR100642617B1 (ko) | 2006-11-13 |
US20060244600A1 (en) | 2006-11-02 |
US20060214793A1 (en) | 2006-09-28 |
TW200634645A (en) | 2006-10-01 |
TWI301244B (en) | 2008-09-21 |
CN100412898C (zh) | 2008-08-20 |
US7298273B2 (en) | 2007-11-20 |
KR20060102460A (ko) | 2006-09-27 |
JP2006268090A (ja) | 2006-10-05 |
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