CN1812123B - 应用金属氧化物半导体工艺的共振隧穿器件 - Google Patents

应用金属氧化物半导体工艺的共振隧穿器件 Download PDF

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CN1812123B
CN1812123B CN200510023017XA CN200510023017A CN1812123B CN 1812123 B CN1812123 B CN 1812123B CN 200510023017X A CN200510023017X A CN 200510023017XA CN 200510023017 A CN200510023017 A CN 200510023017A CN 1812123 B CN1812123 B CN 1812123B
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doped polysilicon
polysilicon layer
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CN1812123A (zh
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B·多伊尔
S·达塔
J·布拉斯克
J·卡瓦利罗斯
A·马朱姆达
M·拉多萨夫耶维克
R·仇
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Nomonks GmbH
Micron Technology Inc
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Intel Corp
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Abstract

本发明的一实施例涉及具有低截止漏电流的半导体器件的制造方法。第一器件的栅极结构形成在具有硬掩模的衬底层上。沟道在栅极结构下面形成并具有一定宽度用于支撑栅极结构。在衬底层上淀积一层氧化物或介电层。在氧化物层上淀积一层掺杂多晶硅层。在第一器件与相邻器件之间的掺杂多晶硅层上形成一凹陷结区。

Description

应用金属氧化物半导体工艺的共振隧穿器件
技术领域
本发明的实施例涉及半导体领域，以及更具体地，涉及半导体的制造工艺。
背景技术
对高性能处理器的需求给半导体器件制造技术提出了很多挑战。随着栅极长度的缩短，截止状态的漏电问题变得越来越严重。每一代工艺中，其可允许晶体管截止漏电流比上一代有3倍的增加。能够控制这些寄生的截止漏电以降低功率消耗和其他不希望的影响就显得非常重要。漏电因跨越源极与沟道之间的势垒的扩散而产生，这主要决定于晶体管的温度。
控制截止漏电的现有技术中还有很多的缺点。在一种技术中是通过平阱分布(flat-well profile)或晕圈掺杂(halo doping)对沟道区域进行主动掺杂。另一种技术之目的在于在掺杂的热处理阶段降低掺杂剂受到扩散的总量。然而，这些技术不是很有效并且要求复杂的处理操作。
发明内容
本发明的一实施例是一种具有低截止状态漏电流的半导体器件的制造方法。第一器件的栅极结构形成在具有硬掩模的衬底层上。在栅极结构的下面形成的沟道具有一定宽度用于支撑栅极结构。在衬底层上淀积氧化物或介电层。在氧化层上淀积掺杂多晶硅层。在第一器件与相邻器件之间的掺杂多晶硅层上形成凹陷结区。
在下面说明中，会提出很多具体的细节。然而，很清楚即使没有这些具体的细节本发明的实施例也可以实施。另一方面，为了避免模糊对本说明书的理解，就不再陈述那些众所周知的电路、结构和工艺方法。
本发明的一个实施例可以描述为一种工序，这通常表示为流程图、流程表、结构图或框图。尽管流程图可能将操作作为连续的工序进行说明，但是实际许多操作可以并行或同时完成。另外，操作的顺序可以重新配置。一个工序在其操作已经完成时终结。一个工序可对应一个方法、一个程序、一个顺序、一个制造或生产方法等。
本发明一实施例是通过使用通常的金属氧化物半导体(MOS)工艺技术来制造共振隧穿晶体管的一种方法。这种技术使用外延弧尖来底切栅极下的硅并形成宽度小于10纳米的沟道或硅柱。这导致沟道区域的量子局限。通过随后对蚀刻区的光氧化，源极和漏极区域通过隧道势垒从沟道分离。通过使用栅极改变费米能级，共振隧穿的条件由栅极势能控制。结由掺杂多晶硅的淀积及回蚀形成。
附图说明
通过参阅下面的描述和用于描述本发明实施例的图可以更好的理解本发明的实施例。
图1是描述本发明的一个实施例可以实施的器件的示意图。
图2是描述根据本发明的一个实施例的隧道势垒效应的示意图。
图3A是描述根据本发明的一个实施例构成栅极结构的示意图。
图3B是描述根据本发明的一个实施例形成沟道的示意图。
图3C是描述根据本发明的一个实施例淀积氧化物/介电层的示意图。
图3D是描述根据本发明的一个实施例淀积掺杂多晶硅层的示意图。
图3E是描述根据本发明的一个实施例形成凹陷结区的示意图。
图3F是描述根据本发明的一个实施例淀积抗蚀剂的示意图。
图3G是描述根据本发明的一个实施例蚀刻掺杂多晶硅层的示意图。
图3H是描述根据本发明的一个实施例去除抗蚀剂的示意图。
图4是描述根据本发明的一个实施例的器件制造工序的流程图。
具体实施方式
图1是描述本发明的一个实施例可以实施的器件100的示意图。器件100包括栅极结构110，结区120，氧化物或介电层150和衬底165。器件100是由通常的金属氧化物半导体(MOS)工艺技术制造而成。这是一种对于缩短的栅极沟道长度具有改进性能的典型MOS场效应晶体管(FET)器件。
栅极结构110包括栅电极112、2个侧壁114和介电层116。栅电极112是由多晶硅构成。2个侧壁114在栅电极的相对侧形成。栅电极112和2个侧壁114在介电层116上形成。
结区120形成在栅极结构110的周围以确定结区域。结区120包括在栅极结构110两侧的漏极区130和源极区140。漏极区130和源极区140通常是由掺杂多晶硅层形成。
氧化物或介电层150在漏极区130和源极区140下面形成。氧化物或介电层150大约有3至7埃的厚度。向栅极结构110内部底切以在每个漏极区130和源极区140中形成凹陷区。这些凹陷区在栅极结构110和结区120的下面形成隧道势垒155。氧化物或介电层150确定了具有宽度W的沟道、杆或柱165来支撑栅极结构110。其宽度W一般小于10纳米。
衬底层160在氧化物或介电层150的下面，通过蚀刻而形成沟道165，它一般由硅形成。
器件100能够呈现类似于共振隧穿晶体管的电特性。隧道势垒155和沟道165给器件100提供相对于距离的势能特性。此势能特性允许器件100在截止状态时有微小的漏电流。截止状态是指在器件100不导通电流的状态。导通状态是指在器件100导通电流的状态。
图2是描述根据本发明的一个实施例的隧道势垒效应的示意图。隧道势垒效应分别对于截止状态210和导通状态250进行描述。
在截止状态210中，器件100呈现势能特性220。特性220具有势能阱215，其对应于器件100的沟道165。在阱215的两侧具有的两个隧道势垒对应于器件100的隧道势垒155。在此说明例中，电流表示为通过入射电子230从源极区140到漏极区130的电子运动。能级量化为几个分散的能级，比如能级222和224。
在截止状态时，栅极电压Vg为0，入射电子230与沟道165中的能级222和224未配准。入射电子230基本上被阻挡而不能通过沟道165，导致最小限度的漏电流。
在导通状态250时，栅极电压Vg大于最低电压Vt，器件100呈现势能特性260。特性260的曲线沿漏极方向下降。当栅极加偏置电压时，量化的能级262和264比能级222和224低，从而使它们与入射电子270配准。入射电子270的费米能级可提供共振条件，其间载流子能够隧穿隧道势垒。入射电子270穿过沟道165而成为漏极区130中的透射电子280。透射电子280表现为导通状态时的有效电流。
被施加电压时，沟道165大体上调整势能阱215中的能级，以至截止状态下有微小的漏电流流动，在导通状态下有有效电流流动。通过控制或调整沟道165的宽度W和/或氧化物/介电层150的厚度，可以精确地控制并最小化漏电流的量。器件100可以通过如图3A至3H所示的通常的MOS工艺制造。
图3A是描述根据本发明的一个实施例构成栅极结构110的示意图。栅极结构110包括栅电极112、2个侧壁114和介电层116。介电层116在衬底层160上。衬底层通常为硅。形成栅极结构110的工艺可以是任意的MOS工艺方法。硬掩模残留在多晶硅上。
图3B是描述根据本发明的一个实施例形成沟道165的示意图。通过蚀刻衬底层160来底切两侧的栅极区而形成宽度小于10纳米的沟道165。沟道165大致在中部支撑栅极结构110。
图3C是描述根据本发明的一个实施例淀积氧化物/介电层的示意图。然后，硅经受氧化。在衬底层160上形成厚度大致5埃的氧化层150，通常在3至7埃之间。另外，也可以在衬底层160上淀积高介电常数的介电层150。在沟道165的两侧的凹陷区域形成两个隧道势垒155。
图3D是描述根据本发明的一个实施例来淀积掺杂多晶硅层的示意图。掺杂多晶硅层淀积在氧化物/介电层150上以及栅极结构110的周围。也可以先淀积未掺杂的多晶硅层再用注入法来掺杂该多晶硅层。这也可以是最终将完全成为硅化物的多晶硅层。
图3E是描述根据本发明的一个实施例构成凹陷结区的示意图。在这个说明例中，示出两个相邻的器件同在一个晶片上：器件301和器件302。这两个器件被沟槽308分离。器件302具有的栅极结构310以及氧化物/介电层350，类似于器件301中的栅极结构110和氧化物/介电层150。将晶片研磨到栅极硬掩模的高度。必要的话，可再次使用扩散掩模来清理隔离区域去除多晶硅(The isolation areas are cleared of the polysilicon by reusingthe diffusion mask)。随后进行反应离子蚀刻法(RIE)的硅蚀刻。在这个蚀刻过程中，栅极的多晶硅仍覆盖着硬掩模。在两个器件之间的多晶硅线会导致短路，因此两个器件需要被隔离。如果必要的话可再用扩散掩模清理隔离区域去除多晶硅。
图3F是描述根据本发明的实施例淀积抗蚀剂的示意图。抗蚀剂360淀积在掺杂多晶硅层上。重复使用沟槽掩模以淀积和显影抗蚀剂360。
图3G是描述根据本发明的一个实施例蚀刻掺杂多晶硅层的示意图。然后蚀刻在器件301和302之间的掺杂多晶硅层。至此，两个器件在电气上隔离。
图3H是描述根据本发明的一个实施例剥离抗蚀剂的示意图。然后剥离晶片上的抗蚀剂360。随后去除栅极硬掩模。
图4是描述根据本发明的一个实施例的器件制造工序400的流程图。
首先开始，工序400包括在具有硬掩模的衬底层上形成第一器件的栅极结构(框410)。如图3A所示，这可以通过传统的MOS工艺实现。然后，如图3B所示，工序400包括在栅极结构下面形成具有一定宽度用于支撑栅极结构的沟道(框420)。这可以通过蚀刻衬底层(框422)以及底切在栅极结构下面的衬底区(框424)来完成。然后，如图3C所示，工序400在衬底层上淀积氧化物或介电层(框430)。然后，如图3D所示，工序400在氧化物/介电层上淀积掺杂多晶硅层(框440)。这可以通过淀积未掺杂多晶硅层(框442)，然后对该未掺杂多晶硅层进行注入(框444)来完成。然后，工序400在第一器件与相邻器件之间的掺杂多晶硅层上面形成凹陷结区(框450)。这可以通过将掺杂多晶硅层研磨到硬掩模的高度(框452)、蚀刻掺杂多晶硅层的结区(框454)、并且如果必要用扩散掩模的手段清理结区(框456)来完成。
然后，如图3F所示，工序400用沟槽掩模在凹陷结区上淀积抗蚀剂(框460)。然后，如图3G所示，工序400蚀刻在第一器件与相邻器件之间的掺杂多晶硅层(框470)。然后，如图3H所示，工序400从凹陷结区剥离抗蚀剂(框480)，最后结束。
尽管本发明描述成几种具体实施例，但是本领域技术人员将认识到，本发明并不局限于上述实施例，而是也可在附属权利要求的精神和范围内修正或改变来实施。本说明只是说明性的而非限制性的。

Claims (8)

1.一种用于制造半导体结构的方法，包括如下步骤：
在衬底层上形成第一器件的栅极结构，其中所述栅极结构包括硬掩模；
向所述栅极结构进行内部底切以在所述第一器件的源极区和漏极区的衬底中形成凹陷区域，从而在所述栅极结构下面形成沟道，所述沟道具有一定宽度用于支撑所述栅极结构；
在所述衬底层的凹陷区域上淀积介电层，所述介电层在所述栅极结构两侧的所述凹陷区域形成隧道势垒；
在所述介电层上淀积一层掺杂多晶硅层，所述掺杂多晶硅层形成所述器件的结区；和
使所述掺杂多晶硅层变薄，以在所述第一器件与相邻器件之间的所述掺杂多晶硅层上形成凹陷结区；
用在第一器件与相邻器件之间的沟槽掩模在所述凹陷结区上淀积抗蚀剂；
蚀刻所述凹陷结区的所述掺杂多晶硅层以隔离所述第一器件和所述相邻器件。
2.如权利要求1所述的方法，其中淀积掺杂多晶硅层的步骤包括：
淀积未掺杂多晶硅层；和
通过对未掺杂多晶硅层注入而形成掺杂多晶硅层。
3.如权利要求1所述的方法，其中形成凹陷结区的步骤包括：
将掺杂多晶硅层研磨到硬掩模的水平；和
蚀刻所述掺杂多晶硅层以形成所述凹陷区域。
4.如权利要求3所述的方法，其中形成凹陷结区的步骤包括：使用扩散掩模。
5.如权利要求1所述的方法，还包括如下步骤：
从凹陷结区上剥离抗蚀剂。
6.如权利要求1所述的方法，其中，所述沟道的宽度小于10纳米。
7.如权利要求1所述的方法，其中，所述介电层的厚度在3至7埃之间。
8.如权利要求1所述的方法，其中，所述介电层是介电氧化物层。
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