CN1794469A - Schockley barrier MOS transistor and its manufacturing method - Google Patents
Schockley barrier MOS transistor and its manufacturing method Download PDFInfo
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- CN1794469A CN1794469A CN 200510130001 CN200510130001A CN1794469A CN 1794469 A CN1794469 A CN 1794469A CN 200510130001 CN200510130001 CN 200510130001 CN 200510130001 A CN200510130001 A CN 200510130001A CN 1794469 A CN1794469 A CN 1794469A
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Abstract
This invention provides a Schottky potential barrier MOS transistor characterizing that the source region and the drain region of said MOS transistor are composed of two layers of metals or compounds formed by metals and semiconductors, the process method of which is compatible with the traditional one and only adds the low energy ionic injection to increase the performance greatly.
Description
Technical field:
The invention belongs to semiconductor integrated circuit and manufacturing technology field thereof, relate in particular to Schockley barrier MOS transistor of a kind of new construction and preparation method thereof.
Background technology:
Schottky source drain (Schottky S/D) structure is in late 1960s, is put forward by Lepselter and Sze.They propose the source of device leaked and utilize metal (or silicide) to replace traditional source to leak and mix, formation Schottky potential barrier between metal (or silicide) and the silicon raceway groove, and the conducting of device is that the charge carrier direct Tunneling potential barrier by the source end realizes.Schottky S/D MOSFET compares traditional source and leaks doping MOSFET, and following advantage is arranged.The first, because metal or the metal silicide that has adopted high electricity to lead leaked in the source, the relative doped source and drain of the dead resistance of Schottky source drain is much smaller; The second, because the schottky interface that metal or metal silicide and silicon form has only several atomic layer sizes, make that super shallow source-and-drain junction is easy to form; The 3rd, because Schottky S/D MOSFET does not need the source to leak the high-temperature annealing process of doping and back, therefore technology is simple relatively, less heat budget is arranged, satisfy the required low temperature process process of high K and metal gate material like this, for the use of high K and metal gate material provides possible solution; The 4th, the high frequency characteristics of Schottky S/D MOSFET device is much better than traditional source and leaks doping MOSFET, and the space therefore may be widely used in the RF circuit.
Yet Schottky S/D MOSFET is because the OFF state electric leakage of schottky junction is more much bigger than the pn knot, and the existence of source end schottky junction simultaneously makes that the ON state current of device is smaller, thereby Schottky S/D MOSFET has the lower problem of switch attitude current ratio.By the research of material and technology, metal (or metal silicide) has been reduced to 0.2eV with the schottky barrier height that low-doped silicon forms, but the short channel effect of the Schottky S/D MOSFET device of low potential barrier becomes seriously.Have research to think can to adopt ultra-thin body (Ultra Thin Body, UTB) structure suppress short channel effect and leakage inductance answer potential barrier attenuate effect (Drain Induced Barrier Thinning, DIBT).Yet it is too thin that the UTB structure devices itself exists silicon film thickness, and technology controlling and process is difficult to guarantee full sheet consistency; In addition, the soi wafer that SIMOX forms, its silicon fiml is poor with the interface of burying oxygen, makes that the performance of device is seriously influenced.
Summary of the invention:
The Schockley barrier MOS transistor that the purpose of this invention is to provide a kind of new construction, this source transistor leak and have double-decker.
Second purpose of the present invention provides the manufacture method of above-mentioned double-deck source source/drain Schottky barrier MOS transistor.
Technical scheme of the present invention is as follows:
A kind of double-deck source source/drain Schottky barrier MOS transistor comprises a gate electrode, a gate dielectric layer, a pair of gate electrode side wall medium layer, semiconductor film, an insulating buried layer, semi-conductive substrate, a source region and a drain region; Described gate electrode is positioned on the gate dielectric layer; Described gate electrode side wall medium layer is positioned on gate electrode both sides, the gate dielectric layer; Described gate dielectric layer is positioned on the semiconductive thin film; Described semiconductive thin film links to each other with the drain region with described source region respectively in the part at gate electrode two ends; Described semiconductive thin film and described source region and drain region are positioned on the described insulating buried layer; Described insulating buried layer is positioned on the described Semiconductor substrate; Described source region and drain region are made of the compound-material that double layer of metal or metal and semiconductor form respectively.
The thickness that above-mentioned Schottky-barrier source is leaked the gate dielectric layer of MOS transistor is 1～5nm; The thickness of gate electrode is 80～150nm; The width of gate electrode side wall medium layer is 25～150nm.
The manufacture method of above-mentioned double-deck source source/drain Schottky barrier MOS transistor may further comprise the steps:
(1) be positioned on Semiconductor substrate and the insulating buried layer semiconductive thin film on form to isolate the place;
(2) growth gate dielectric layer;
(3) deposit gate electrode layer, then photoetching and etching gate electrode layer form gate electrode figure;
(4) be that mask carries out the low energy ion injection with the gate electrode figure, be different from the semiconductor lamella of substrate semiconductor material in source drain surface formation one;
(5) side wall medium layer is sacrificed in deposit, and Hui Kehou forms side wall in the gate electrode both sides, be that mask corrosion falls gate dielectric layer with gate electrode and the side wall figure that forms;
(6) deposit layer of metal, annealed formation metal and semi-conductive compound are then removed unreacted metal;
(7) enter the conventional cmos later process at last, comprise deposit passivation layer, opening contact hole and metallization etc., can make described MOS transistor.
In the above-mentioned manufacture method, the semi-conducting material in the described step (1) is selected from: the binary of Si, Ge, SiGe, GaAs or other II-VI, III-V and IV-IV family or the semi-conducting material of ternary compound form.
Above-mentioned manufacture method, the insulating material in the described step (1) is selected from: silicon dioxide, silicon nitride, aluminium nitride and other insulating material.
Above-mentioned manufacture method, the gate dielectric layer material in the described step (2) is selected from: silicon dioxide, hafnium oxide, gallium oxide and other conductor oxidate.
Above-mentioned manufacture method, the method for described step (2) growth gate dielectric layer is selected from one of following method: conventional thermal oxidation, nitrating thermal oxidation, chemical vapor deposition, physical vapor deposition.
In the above-mentioned manufacture method, semiconductor film layer material in the described step (4) is selected from: the binary of Si, Ge, SiGe, GaAs or other II-VI, III-V and IV-IV family or the semi-conducting material of ternary compound form, but with the binary of described step (1) or other II-VI, III-V and IV-IV family or the semi-conducting material of ternary compound form, but the semi-conducting material of selecting for use with described step (1) is different.
Above-mentioned manufacture method is sacrificed the side wall medium layer material in the described step (5) and is silicon nitride or other all has high corrosion to select the thin-film material of ratio with silicon and silica.
Above-mentioned manufacture method, the metal material in the described step (6) is selected from: Pt, Er, Co, Ni and other can form the metal of compound with the substrate semiconductor material by annealing.
Above-mentioned manufacture method, the thickness of the gate dielectric layer of growing on the described semiconductive thin film are 1-5nm; The thickness of gate electrode layer is 80-150nm; The lateral wall width that the gate electrode both sides form is 25-150nm; The injection energy that low energy is injected is 200eV-30KeV.
Advantage of the present invention and good effect: double-deck source of the present invention source/drain Schottky barrier MOS transistor, because leaking, its source has double-decker, this double-decker can obtain two kinds of schottky barrier heights, by selecting suitable semiconductor and metal material, make that the schottky barrier height on upper strata is little, the schottky barrier height of lower floor is relatively large simultaneously.The low Schottky barrier on upper strata can improve the ON state current that Schottky-barrier source is leaked MOS transistor; Meanwhile, the high Schottky barrier of lower floor can improve the immunocompetence of device to short channel effect, reduces the off-state current of device; The high schottky barrier layer of lower floor can become very thick, and the performance of device can't produce too big degeneration, and therefore whole semiconductive thin film can become very thick.
It is compatible mutually with traditional Schottky barrier source drain MOSFET transistor fabrication technology that the present invention proposes the transistorized its preparation process of double-deck source source/drain Schottky barrier MOSFET, just having increased by a step low energy ion in technical process injects, process complexity does not have to change substantially, and the performance of device is greatly improved.
Description of drawings:
Fig. 1 is the processing step schematic diagram that carries out shallow-trench isolation on the semiconductive thin film that is positioned on the insulator;
Fig. 2 is the processing step schematic diagram of growth gate dielectric layer;
Fig. 3 is the processing step schematic diagram that gate electrode forms;
Fig. 4 is that low energy ion injects the processing step schematic diagram that semiconductor lamella is leaked in the formation source;
Fig. 5 is that gate electrode is sacrificed the processing step schematic diagram that side wall forms;
Fig. 6 is the processing step schematic diagram that depositing metal annealing forms Schottky source drain;
Among the figure:
1-silicon substrate 2-oxygen buried layer
3-silicon fiml 4-separator
5-gate oxide 6-polysilicon gate
The 7-germanium silicon thin layer 8-of mixed semiconductor silicon nitride side wall
9-germanium metal silicon compound 10-metal silicide
The 11-metal silicide gate electrode
Embodiment:
Following specific embodiment helps to understand the features and advantages of the present invention, but enforcement of the present invention never only is confined to described embodiment.
One specific embodiment of manufacture method of the present invention comprises extremely processing step shown in Figure 6 of Fig. 1:
1. as shown in Figure 1, used soi wafer adopts silicon substrate (1), and the crystal orientation of the monocrystalline silicon membrane (3) on the oxygen buried layer (2) is (100), and silicon fiml is initially light dope, adopts conventional cmos shallow-trench isolation fabrication techniques active area isolation layer (4) on silicon fiml.
2. as shown in Figure 2, the gate oxide (5) of on silicon fiml (3) and separator (4), then growing, gate oxide is a silicon dioxide, its thickness is 1～5nm.The formation method of gate oxide can be one of following method: conventional thermal oxidation, nitrating thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD).
3. as shown in Figure 3, deposit gate electrode layer doped polysilicon layer, the thickness of polysilicon layer are 80～150nm.Then adopt the polysilicon layer of photoetching of conventional cmos technology and etching institute deposit, form polysilicon gate (6).The gate material of institute's deposit can also be the poly-SiGe alloy.
4. as shown in Figure 4, be mask with the gate electrode that forms, inject formation source, gate electrode both sides by ion and leak germanium silicon mixed semiconductor's thin layer (7), ion implanted impurity is a germanium, implantation dosage is 5e+15cm
-2, the injection energy is 5KeV.
5. as shown in Figure 5, with the sacrifice side wall medium layer silicon nitride of LPCVD deposit 10～30nm, then using back quarter (etch-back) technology is the silicon nitride side wall (8) of 5～20nm at gate electrode both sides formation width.
6. as shown in Figure 6, with MOCVD method deposit layer of metal Pt, through the low temperature thermal annealing, form germanium metal silicon compound (9) and metal silicide (10) with germanium silicon mixed semiconductor's thin layer and Si semiconductor thin layer respectively, the grid place forms metal silicide gate electrode (11) simultaneously.
Enter the conventional cmos later process at last, comprise deposit passivation layer, opening contact hole and metallization etc., can make the leakage of described source and have double-deck Schottky-barrier MOSFET transistor and preparation method thereof.
Claims (10)
1. a Schockley barrier MOS transistor comprises a gate electrode, a gate dielectric layer, a pair of gate electrode side wall medium layer, semiconductor film, an insulating buried layer, semi-conductive substrate, a source region and a drain region; Described gate electrode is positioned on the gate dielectric layer; Described gate electrode side wall medium layer is positioned on gate electrode both sides, the gate dielectric layer; Described gate dielectric layer is positioned on the semiconductive thin film; Described semiconductive thin film links to each other with the drain region with described source region respectively in the part at gate electrode two ends; Described semiconductive thin film and described source region and drain region are positioned on the described insulating buried layer; Described insulating buried layer is positioned on the described Semiconductor substrate; Described source region and drain region are made of the compound-material that double layer of metal or metal and semiconductor form respectively.
2. Schockley barrier MOS transistor as claimed in claim 1 is characterized in that: the thickness of described gate dielectric layer is 1～5nm, and the thickness of gate electrode is 80～150nm, and the width of gate electrode side wall medium layer is 25～150nm.
3. the manufacture method of a Schockley barrier MOS transistor may further comprise the steps:
(1) on the semiconductive thin film that is positioned on Semiconductor substrate and the insulating buried layer, forms the isolation place;
(2) growth gate dielectric layer;
(3) deposit gate electrode layer, then photoetching and etching gate electrode layer form gate electrode figure;
(4) be that mask carries out the low energy ion injection with the gate electrode figure, be different from the semiconductor lamella of substrate semiconductor material in source drain surface formation one;
(5) side wall medium layer is sacrificed in deposit, and Hui Kehou forms side wall in the gate electrode both sides, be that mask corrosion falls gate dielectric layer with gate electrode and the side wall figure that forms;
(6) deposit layer of metal, annealed formation metal and semi-conductive compound are then removed unreacted metal;
(7) enter the conventional cmos later process at last, comprise deposit passivation layer, opening contact hole and metallization etc., can make described MOS transistor.
4. manufacture method as claimed in claim 3, it is characterized in that, described step (1) is different with the used semi-conducting material of step (4), is selected from respectively: the binary of Si, Ge, SiGe, GaAs or other II-VI, III-V and IV-IV family or the semi-conducting material of ternary compound form.
5. manufacture method as claimed in claim 4 is characterized in that, described semiconductor substrate materials is a monocrystalline silicon, and described gate electrode layer material is polysilicon or poly-SiGe alloy.
6. manufacture method as claimed in claim 3 is characterized in that, the insulating material in the described step (1) is selected from: silicon dioxide, silicon nitride, aluminium nitride.
7. manufacture method as claimed in claim 3 is characterized in that, the gate dielectric layer material in the described step (2) is selected from: silicon dioxide, hafnium oxide, gallium oxide.
8. manufacture method as claimed in claim 3 is characterized in that, the method for described step (2) growth gate dielectric layer is selected from one of following method: conventional thermal oxidation, nitrating thermal oxidation, chemical vapor deposition, physical vapor deposition.
9. manufacture method as claimed in claim 3 is characterized in that, the sacrifice side wall medium layer material in the described step (5) is that silicon nitride or other all have high corrosion to select the thin-film material of ratio with silicon and silica.
10. as the described manufacture method of the arbitrary claim of claim 3～9, it is characterized in that: the thickness of the gate dielectric layer of growing on the described semiconductive thin film is 1～5nm, the thickness of gate electrode layer is 80～150nm, and the lateral wall width that the gate electrode both sides form is 25～150nm; The injection energy that low energy is injected is 200eV-30KeV.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101866953A (en) * | 2010-05-26 | 2010-10-20 | 清华大学 | Low Schottky barrier semiconductor structure and formation method thereof |
| CN102119445A (en) * | 2008-08-13 | 2011-07-06 | E.I.内穆尔杜邦公司 | Compositions and processes for forming photovoltaic devices |
| CN102117833A (en) * | 2011-01-19 | 2011-07-06 | 北京大学 | Comb-shaped gate composite source MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof |
| CN107528001A (en) * | 2017-08-31 | 2017-12-29 | 清华大学 | The preparation method and nanotube diode of a kind of nanotube diode |
| CN108292687A (en) * | 2015-12-24 | 2018-07-17 | 英特尔公司 | Low schottky barrier contact structure for ge nmos |
| CN109671780A (en) * | 2018-11-28 | 2019-04-23 | 中国科学院微电子研究所 | Schotthy barrier transistor and preparation method thereof |
Family Cites Families (5)
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| US6828632B2 (en) * | 2002-07-18 | 2004-12-07 | Micron Technology, Inc. | Stable PD-SOI devices and methods |
| KR100508548B1 (en) * | 2003-04-16 | 2005-08-17 | 한국전자통신연구원 | Schottky barrier transistor and method for fabricating the same |
| JP4647889B2 (en) * | 2003-04-25 | 2011-03-09 | 富士通セミコンダクター株式会社 | Method for manufacturing field effect transistor having Schottky source / drain structure |
| JP2005026563A (en) * | 2003-07-04 | 2005-01-27 | Renesas Technology Corp | Semiconductor device |
| JP2005079277A (en) * | 2003-08-29 | 2005-03-24 | Toshiba Corp | Field effect transistor |
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2005
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102119445A (en) * | 2008-08-13 | 2011-07-06 | E.I.内穆尔杜邦公司 | Compositions and processes for forming photovoltaic devices |
| CN101866953A (en) * | 2010-05-26 | 2010-10-20 | 清华大学 | Low Schottky barrier semiconductor structure and formation method thereof |
| CN101866953B (en) * | 2010-05-26 | 2012-08-22 | 清华大学 | Low Schottky barrier semiconductor structure and formation method thereof |
| CN102117833A (en) * | 2011-01-19 | 2011-07-06 | 北京大学 | Comb-shaped gate composite source MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof |
| CN102117833B (en) * | 2011-01-19 | 2012-07-25 | 北京大学 | Comb-shaped gate composite source MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof |
| CN108292687A (en) * | 2015-12-24 | 2018-07-17 | 英特尔公司 | Low schottky barrier contact structure for ge nmos |
| CN107528001A (en) * | 2017-08-31 | 2017-12-29 | 清华大学 | The preparation method and nanotube diode of a kind of nanotube diode |
| CN107528001B (en) * | 2017-08-31 | 2019-10-11 | 清华大学 | A kind of preparation method and nanotube diode of nanotube diode |
| CN109671780A (en) * | 2018-11-28 | 2019-04-23 | 中国科学院微电子研究所 | Schotthy barrier transistor and preparation method thereof |
| CN109671780B (en) * | 2018-11-28 | 2023-06-16 | 中国科学院微电子研究所 | Schottky barrier transistor and preparation method thereof |
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| CN100389501C (en) | 2008-05-21 |
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