CN1889273A - MOS transistor with partial depletion SOI structure and producing method thereof - Google Patents
MOS transistor with partial depletion SOI structure and producing method thereof Download PDFInfo
- Publication number
- CN1889273A CN1889273A CN 200610103561 CN200610103561A CN1889273A CN 1889273 A CN1889273 A CN 1889273A CN 200610103561 CN200610103561 CN 200610103561 CN 200610103561 A CN200610103561 A CN 200610103561A CN 1889273 A CN1889273 A CN 1889273A
- Authority
- CN
- China
- Prior art keywords
- layer
- dielectric
- semiconductor
- gate electrode
- mos transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Thin Film Transistor (AREA)
Abstract
The present invention provides part depletion SOI constructional MOS transistor used in nano integrated circuit manufacturing technology and making method. The upper part of said transistor source drain expansion zone is thin semiconductor layer, the lower part being cavity unit, said structure having advantages of ultrathin unit all depletion SOI MOS transistor and partial depleted SOI MOS transistor and overcoming their shortage. Said invented preparation method is compatible with traditional MOS transistor making technology, with simple technological process and use value.
Description
Technical field:
The invention belongs to semiconductor integrated circuit and manufacturing technology field thereof, relate in particular to MOS transistor of a kind of new construction and preparation method thereof.
Background technology:
The characteristic size of MOS transistor is constantly scaled, when entering nanoscale, various small-size effects such as short-channel effect (SCE), leakage inductance are answered potential barrier to reduce effect (DIBL) etc. and are become more and more serious, seriously influence the device performance of small size MOS transistor.Therefore, in order to continue to keep MOS transistor still to have strong scaled ability at nanoscale, the researcher has proposed multiple new construction, new material and new technology.
Silicon-on-insulator (SOI) device is exactly wherein a kind of.Press the difference of silicon film thickness, the SOI device mainly is divided into two classes:
One class is to be the full-exhaustion SOI device of representative with the ultra-thin body, and such device has series of advantages, comprises that inhibition short channel effect ability is strong, and technology and conventional MOS process compatible have been eliminated the problem of shallow junction making etc.Yet when such device was reduced to inferior 50nm when grid length, its corresponding silicon film thickness required to have only several nanometers, and the present technological level of so little thickness is difficult to guarantee their full sheet uniformity, and the inconsistent meeting of thickness brings the fluctuation of threshold voltage; In addition, because silicon film thickness is too little, the dead resistance that leak in the source can become very big, dead resistance for leak in the reduction source must adopt the source-drain structure of raising, and has so not only brought the problem of the complexity of technology, also increase simultaneously the parasitic capacitance that grid leak the source, seriously influenced the performance of device; In addition, the full depletion mos transistor of ultra-thin body structure is subjected to the influence of silicon fiml and oxygen buried layer interface scattering bigger, causes mobility of charge carrier rate decline in the raceway groove, thereby reduces the performance of such device.The existence of these problems makes such device be difficult to be applied to the production of integrated circuit.
The SOI MOS transistor that another kind of SOI device is a part depletion.The SOI MOS transistor of part depletion has bigger silicon film thickness, and its structure is similar to traditional body silicon MOS with design, be subjected to the diffuse transmission influence at silicon fiml and oxygen buried layer interface also less simultaneously, thereby channel carrier can have higher mobility.Yet, the SOI MOS transistor of this part depletion is because grid are limited to the control ability of raceway groove, therefore its short channel effect is serious, scaled limited in one's ability, also there is serious Kink effect in such device simultaneously, and these make such device also be difficult to be applied to the integrated circuit production of nanoscale.
Summary of the invention:
The purpose of this invention is to provide a kind of partial depletion SOI mos transistor structure that can be applicable to the nanoscale ic manufacturing technology, and this transistorized manufacture method.
Technical scheme of the present invention is as follows:
A kind of MOS transistor of partial depletion SOI structure comprises a gate electrode, a gate dielectric layer, and a gate electrode side wall medium layer, the semiconductor tagma, an oxygen buried layer, semi-conductive substrate, a source region and a drain region, the expansion area is leaked in expansion area, a source and; Described oxygen buried layer is positioned on the Semiconductor substrate; Described source region and drain region are positioned on the oxygen buried layer, gate electrode side wall medium layer both sides; Described semiconductor body is positioned under the gate dielectric layer, and on the oxygen buried layer, both sides are leaked the expansion area with the source respectively and linked to each other; Described gate electrode side wall medium layer is positioned at gate electrode and gate dielectric layer both sides; Described source is leaked the expansion area and is made up of a thin semiconductor layer and the cavity body or the insulator that are positioned under it.
Above-mentioned cavity body can obtain described insulator by the filling of dielectric material.
The manufacture method of the MOS transistor of above-mentioned partial depletion SOI structure may further comprise the steps:
(1) use shallow-trench isolation (STI) technology on the semiconductor lamella of semiconductor SOI structural material, be formed with the source region, wherein said S0I structure comprises Semiconductor substrate, oxygen buried layer and semiconductor lamella;
(2) growth gate dielectric layer, deposit gate electrode layer, deposit one deck dielectric one then;
(3) photoetching and etching form gate figure;
(4) deposit one deck is different from the dielectric two of dielectric one, covers the source-drain area that exposes, and surrounds the grid structure of whole exposure;
(5) another layer of deposit dielectric one, and be engraved in the grid both sides and form the side wall that constitutes by dielectric one by returning;
(6) selective etching gate electrode both sides show the dielectric two that leaks, and form to inject window;
(7) inject by ion, form the highly doped dopant profiles in low-doped bottom, top layer at the semiconductor film layer region that injects under the window;
(8) deposit one deck dielectric one is once more filled and is injected window, carves the dielectric of removing on the isolated area one by returning;
(9) oxide layer beyond the source of corrosion drain region, the heavily doped semiconductor layer part until the place of being injected into appears in the side.
(10) employing is to the corrosive liquid of doping content sensitivity, and the highly doped semiconductor region that selective etching is exposed stays top low-doped thin layer, and forms cavity body down at it;
(11) remove whole dielectrics;
(12) form another film dielectric layer, ion implantation doping source-drain area and gate electrode return then to engrave and state film dielectric layer to form new gate electrode side wall;
(13) enter the conventional cmos later process at last, comprise deposit passivation layer, opening contact hole and metallization etc., can make described MOS transistor.
In the above-mentioned manufacture method, the semi-conducting material in the described step (1) is selected from Si, Ge, SiGe, GaAs and other II-VI, the binary or the ternary semiconductor of III-V and IV-IV family.
Above-mentioned manufacture method, dielectric one material in the described step (2) is selected from silicon dioxide, silicon nitride, aluminium nitride, TEOS (silester) and other insulating material.
Above-mentioned manufacture method, dielectric two materials in the described step (4) are selected from silicon dioxide, silicon nitride, aluminium nitride, TEOS (silester) and other insulating material, but are different from dielectric one.
Above-mentioned manufacture method, the injection energy range that the ion in the described step (7) injects is 0.5eV-200KeV, the implantation dosage scope is at 1e11-5e15/cm
2
Etchant solution is the solution of hydrofluoric acid-nitric acid etching system in the above-mentioned manufacture method, described step (9), as volume ratio 40%HF: 70%HNO
3: 100%CH
3COOH=1: 3: 8 hydrofluoric acid, nitric acid and acetate mixture, perhaps other has high corrosion to select the etchant solution prescription of ratio to semi-conducting materials such as doped silicons.
Advantage of the present invention and good effect:
Improved partial depletion SOI mos transistor structure of the present invention, it is thin semiconductor layer that top, expansion area is leaked in the source of this structure, the bottom is a cavity body, so can have the advantage of ultra-thin body full-exhaustion SOI MOS transistor and partial depletion SOI MOS transistor concurrently, has overcome their deficiency simultaneously.
Be limited on the cavity body because the semiconductor layer on top, expansion area is leaked in the source, semiconductor layer relatively can be very thin, and is therefore similar to ultra-thin body full-exhaustion SOI MOS transistor, can obtain stronger short channel effect and suppress ability.The existence of expansion area lower cavity body is leaked in the source, not only eliminated the passage of leakage current, thereby reduced the OFF leakage current of device, the potential barrier break-through between leak in the source that also makes is suppressed, and answers potential barrier to reduce the influence of (DIBL) effect to device property thereby reduced leakage inductance.Meanwhile, along with the increase of cavity body height, it is very thick that the semiconductor film of channel region and source-drain area can become, and therefore makes its series of advantages with partial depletion SOI MOS transistor, simplicity of design, and the source is leaked not need to adopt and is raised structure etc.In addition, partial depletion SOI mos transistor structure of the present invention, eliminated that ultra-thin body full-exhaustion SOI MOS transistor requires the harshness of film and wherein the mobility that causes of the interface scattering between semiconductor layer and the oxygen buried layer reduce problem, thereby also eliminated the degeneration of such device performance that causes thus.
Its preparation process of the improved partial depletion SOI MOS transistor that the present invention proposes and traditional MOS transistor manufacture craft compatibility, utilize ripe selective etching technology realization source to leak the device architecture of top, expansion area thin semiconductor layer, lower cavity body, process is simply ingenious, extremely strong practical value is arranged, can be applicable in the nanoscale ic manufacturing technology.
Description of drawings:
Fig. 1 is the schematic diagram of SOI silicon substrate;
Fig. 2 is the growth gate dielectric layer, the processing step schematic diagram of deposit gate electrode and silicon nitride protective layer thereof;
Fig. 3 is the processing step schematic diagram that photoetching and etching form gate electrode;
Fig. 4 is the processing step schematic diagram of deposit silicon dioxide;
Fig. 5 is once more the processing step schematic diagram of deposit silicon nitride;
Fig. 6 is that etching forms the processing step schematic diagram that injects window;
Fig. 7 is the processing step schematic diagram that ion injects;
Fig. 8 fills window, and selective etching forms the processing step schematic diagram of cavity structure;
Fig. 9 is a processing step schematic diagram of removing silicon nitride and silicon dioxide;
Figure 10 injects the processing step schematic diagram that leak in the formation source and gate electrode mixes and forms side wall.
Among the figure:
1-silicon substrate 2-oxygen buried layer
3-silicon fiml 4-gate dielectric layer silicon dioxide
5-silicon dioxide 6-gate electrode layer polysilicon
7-silicon nitride 8-silicon nitride side wall
9-highly doped silicon 10-silicon nitride
11-cavity body structure 12-silicon dioxide side wall
Expansion area 14-source-drain area is leaked in the 13-source
Embodiment:
Specific embodiment below in conjunction with description of drawings helps to understand the features and advantages of the present invention, but enforcement of the present invention never only is confined to described embodiment.
One specific embodiment of manufacture method of the present invention comprises extremely processing step shown in Figure 10 of Fig. 1:
1. as shown in Figure 1, prepare the SOI silicon substrate, this SOI silicon substrate structure comprises silicon substrate (1), oxygen buried layer (2) and silicon fiml (3), adopts shallow-trench isolation (STI) technology to be formed with the source region on silicon fiml (3);
2. as shown in Figure 2, adopt thermal oxidation process growth gate dielectric layer silicon dioxide (4), gate dielectric layer silicon dioxide (4) thickness range is at 1-10nm; Then, the gate electrode layer polysilicon (6) of deposit 100nm; Afterwards, the dielectric layer deposited silicon nitride is used for grill-protected electrode polysilicon (4) again;
3. as shown in Figure 3, photoetching and etch silicon nitride (7) and gate electrode layer polysilicon (6) form gate figure;
4. as shown in Figure 4, deposit one dielectric layer silicon dioxide (5) covers the source-drain area that exposes, and surrounds whole grid structure;
5. as shown in Figure 5, deposit one dielectric layer silicon nitride returns and is engraved in the bigger silicon nitride side wall (8) of grid both sides formation;
6. as shown in Figure 6, the silicon dioxide (5) of gate electrode layer polysilicon (6) both sides is removed in selective etching, forms and injects window, and silicon dioxide (5) can keep 10nm, as the resilient coating that injects;
7. as shown in Figure 7, be infused in the semiconductor film layer region that injects the window place by ion and form the highly doped dopant profiles in low-doped bottom, top layer, ion implantation energy is 60KeV, and implantation dosage is 1E13/cm
2
8. as shown in Figure 8, deposit silicon nitride (10) is filled and is injected window, and returns to carve and remove the silicon nitride (10) of isolating on the place; Oxide layer beyond the source of corrosion drain region appears in the side until the highly doped silicon (9) that injects the window place; Employing is according to the different selective etching solution that mixes, and etchant solution is hydrofluoric acid, nitric acid and acetate mixture, fills a prescription to be 40%HF: 70%HNO
3: 100%CH
3COOH mixes with volume ratio at 1: 3: 8, and the highly doped silicon that selective etching is exposed (9) forms cavity body structure (11);
9. as shown in Figure 9, remove silicon nitride (7), remove silicon dioxide (5) then;
1O. as shown in figure 10, deposit one thin silicon dioxide, ion implantation doping source-drain area (14) and gate electrode return then to engrave and state thin silicon dioxide layer to form new thin silicon dioxide side wall (12), and expansion area (13) is leaked in the formation source down at silicon dioxide side wall (12) in the annealing back;
Enter the conventional cmos later process at last, comprise deposit passivation layer, opening contact hole and metallization etc., can make the MOS transistor of described partial depletion SOI structure.
Claims (8)
1. the MOS transistor of a partial depletion SOI structure comprises a gate electrode, a gate dielectric layer, and a gate electrode side wall medium layer, the semiconductor tagma, an oxygen buried layer, semi-conductive substrate, a source region and a drain region, the expansion area is leaked in expansion area, a source and; Described oxygen buried layer is positioned on the Semiconductor substrate; Described source region and drain region are positioned on the oxygen buried layer, gate electrode side wall medium layer both sides; Described semiconductor body is positioned under the gate dielectric layer, and on the oxygen buried layer, both sides are leaked the expansion area with the source respectively and linked to each other; Described gate electrode side wall medium layer is positioned at gate electrode and gate dielectric layer both sides; Described source is leaked the expansion area and is made up of a thin semiconductor layer and the cavity body or the insulator that are positioned under it.
2. the manufacture method of the MOS transistor of a partial depletion SOI structure may further comprise the steps:
(1) use the shallow-trench isolation technology on the semiconductor lamella of semiconductor SOI structural material, be formed with the source region, wherein said soi structure comprises Semiconductor substrate, oxygen buried layer and semiconductor lamella;
(2) growth gate dielectric layer, deposit gate electrode layer, deposit one deck dielectric one then;
(3) photoetching and etching form gate figure;
(4) deposit one deck is different from the dielectric two of dielectric one, covers the source-drain area that exposes, and surrounds the grid structure of whole exposure;
(5) another layer of deposit dielectric one, and be engraved in the grid both sides and form the side wall that constitutes by dielectric one by returning;
(6) selective etching gate electrode both sides show the dielectric two that leaks, and form to inject window;
(7) inject by ion, form the highly doped dopant profiles in low-doped bottom, top layer at the semiconductor film layer region that injects under the window;
(8) deposit one deck dielectric one is once more filled and is injected window, carves the dielectric of removing on the isolated area one by returning;
(9) oxide layer beyond the source of corrosion drain region, the heavily doped semiconductor layer part until the place of being injected into appears in the side.
(10) employing is to the corrosive liquid of doping content sensitivity, and the highly doped semiconductor region that selective etching is exposed stays top low-doped thin layer, and forms cavity body down at it;
(11) remove whole dielectrics;
(12) form another film dielectric layer, ion implantation doping source-drain area and gate electrode return then to engrave and state film dielectric layer to form new gate electrode side wall;
(13) enter the conventional cmos later process at last, comprise deposit passivation layer, opening contact hole and metallization etc., can make described MOS transistor.
3. manufacture method as claimed in claim 2 is characterized in that, the semi-conducting material in the described step (1) is selected from Si, Ge, SiGe, GaAs or other II-VI, the binary or the ternary semiconductor of III-V and IV-IV family.
4. manufacture method as claimed in claim 2 is characterized in that, the dielectric one in the described step (2) is different with dielectric two materials in the step (4), is selected from respectively: silicon dioxide, silicon nitride, aluminium nitride, silester.
5. manufacture method as claimed in claim 2 is characterized in that, the injection energy range that the ion in the described step (7) injects is 0.5eV-200KeV, and the implantation dosage scope is at 1e11-5e15/cm
2
6. manufacture method as claimed in claim 2 is characterized in that, the corrosive liquid in the described step (9) is selected the etchant solution of ratio for doped semiconductor materials there being high corrosion.
7. manufacture method as claimed in claim 6 is characterized in that, described etchant solution is the solution of hydrofluoric acid-nitric acid etching system.
8. manufacture method as claimed in claim 7 is characterized in that, described etchant solution is volume ratio 40%HF: 70%HNO
3: 100%CH
3COOH=1: 3: 8 hydrofluoric acid, nitric acid and acetate mixture.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200610103561XA CN100414714C (en) | 2006-07-21 | 2006-07-21 | MOS transistor with partial depletion SOI structure and producing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200610103561XA CN100414714C (en) | 2006-07-21 | 2006-07-21 | MOS transistor with partial depletion SOI structure and producing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1889273A true CN1889273A (en) | 2007-01-03 |
| CN100414714C CN100414714C (en) | 2008-08-27 |
Family
ID=37578536
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB200610103561XA Expired - Fee Related CN100414714C (en) | 2006-07-21 | 2006-07-21 | MOS transistor with partial depletion SOI structure and producing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100414714C (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100527371C (en) * | 2007-09-14 | 2009-08-12 | 北京大学 | Portion exhausted SOI MOS transistor preparation method |
| CN102487033A (en) * | 2010-12-03 | 2012-06-06 | 中芯国际集成电路制造(北京)有限公司 | Method for forming standard SOI (Silicon On Insulator) structure |
| CN102903641A (en) * | 2012-10-26 | 2013-01-30 | 哈尔滨工程大学 | Method for reducing partial contact resistance and parasitic capacitance of SOI (Silicon on Insulator) PD (Partially-Depleted) MOSFET (Metal-Oxide -Semiconductor Field Effect Transistor) |
| WO2015051561A1 (en) * | 2013-10-13 | 2015-04-16 | 中国科学院微电子研究所 | Mosfet structure and method for manufacturing same |
| CN111986996A (en) * | 2020-08-21 | 2020-11-24 | 中国科学院上海微系统与信息技术研究所 | SOI device for improving self-heating effect and preparation method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3408437B2 (en) * | 1998-10-30 | 2003-05-19 | シャープ株式会社 | Method for manufacturing semiconductor device |
| JP2001044437A (en) * | 1999-07-27 | 2001-02-16 | Matsushita Electronics Industry Corp | Mos transistor and manufacture thereof |
| CN100356527C (en) * | 2005-08-31 | 2007-12-19 | 北京大学 | Method for making MOS transistor with source-drain on insulating layer |
| CN100356528C (en) * | 2005-08-31 | 2007-12-19 | 北京大学 | Method for making MOS transistor with source-drain on insulating layer |
-
2006
- 2006-07-21 CN CNB200610103561XA patent/CN100414714C/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100527371C (en) * | 2007-09-14 | 2009-08-12 | 北京大学 | Portion exhausted SOI MOS transistor preparation method |
| CN102487033A (en) * | 2010-12-03 | 2012-06-06 | 中芯国际集成电路制造(北京)有限公司 | Method for forming standard SOI (Silicon On Insulator) structure |
| CN102487033B (en) * | 2010-12-03 | 2014-04-02 | 中芯国际集成电路制造(北京)有限公司 | Method for forming standard SOI (Silicon On Insulator) structure |
| CN102903641A (en) * | 2012-10-26 | 2013-01-30 | 哈尔滨工程大学 | Method for reducing partial contact resistance and parasitic capacitance of SOI (Silicon on Insulator) PD (Partially-Depleted) MOSFET (Metal-Oxide -Semiconductor Field Effect Transistor) |
| WO2015051561A1 (en) * | 2013-10-13 | 2015-04-16 | 中国科学院微电子研究所 | Mosfet structure and method for manufacturing same |
| CN104576377A (en) * | 2013-10-13 | 2015-04-29 | 中国科学院微电子研究所 | Mosfet structure and manufacturing method thereof |
| US9608064B2 (en) | 2013-10-13 | 2017-03-28 | Institute of Microelectronics, Chinese Academy of Sciences | MOSFET structure and method for manufacturing same |
| CN111986996A (en) * | 2020-08-21 | 2020-11-24 | 中国科学院上海微系统与信息技术研究所 | SOI device for improving self-heating effect and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100414714C (en) | 2008-08-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100597460B1 (en) | Transistor of semiconductor device and fabricating method thereof | |
| CN100342505C (en) | Method for fabricating a high voltage power MOSFET having a voltage sustaining region that includes doped columns formed by rapid diffusion | |
| CN1290203C (en) | Semiconductor device structure and its producing method | |
| US20060091453A1 (en) | Trench MIS device and method for manufacturing trench MIS device | |
| CN1552102A (en) | Trench FET with self aligned source and contact | |
| CN1731570A (en) | Method for making MOS transistor with source-drain on insulating layer | |
| CN1095860A (en) | Make the method for the semiconductor device of the silicon structure on the insulator | |
| CN101068029A (en) | Double-fin type channel double-grid multifunction field effect transistor and producing method thereof | |
| CN1797762A (en) | Semiconductor structure of wafer and method for forming same | |
| CN1941412A (en) | Planar ultra-thin semiconductor-on-insulator channel MOSFET and method of making same | |
| CN1731569A (en) | Method for making MOS transistor with source-drain on insulating layer | |
| CN101079450A (en) | Fin channel dual-bar multi-function field effect transistor and its making method | |
| CN1889273A (en) | MOS transistor with partial depletion SOI structure and producing method thereof | |
| CN1324113A (en) | Self-alignment dual gate metal oxide semi-conductor field-effect transistor having separating gate | |
| CN116072546A (en) | Silicon carbide split gate trench MOSFET integrated with SBD and preparation method | |
| CN1956214A (en) | Field effect transistor and manufacturing method thereof | |
| CN1851930A (en) | Partial consumption SOI MOS transistor and making method | |
| CN1649173A (en) | Semiconductor apparatus and method of manufacturing the same | |
| CN1779988A (en) | Integrated high-voltage VDMOS transistor structure and production thereof | |
| CN1794469A (en) | Schockley barrier MOS transistor and its manufacturing method | |
| CN1135615C (en) | Semiconductor device fabrication method | |
| CN1099706C (en) | Method for making semiconductor device | |
| CN101814436A (en) | Method for preparing longitudinal high-pressure deep-slot transistor | |
| CN1540768A (en) | Source/drain sink type ultrathin SOIMOS transistor and method for preparing IC | |
| CN1193432C (en) | Structure for lowering series resistor between source and drain in silicon transistors on insulator as well as implement method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080827 Termination date: 20140721 |
|
| EXPY | Termination of patent right or utility model |