CN100356528C - Method for making MOS transistor with source-drain on insulating layer - Google Patents
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- CN100356528C CN100356528C CNB2005100863242A CN200510086324A CN100356528C CN 100356528 C CN100356528 C CN 100356528C CN B2005100863242 A CNB2005100863242 A CN B2005100863242A CN 200510086324 A CN200510086324 A CN 200510086324A CN 100356528 C CN100356528 C CN 100356528C
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Abstract
The present invention discloses a method for preparing MOSFET transistors with source drain positioned on an insulating layer. The present invention has the steps that a low doped layer is formed on the surface of a semiconductor substrate through diffusion or ion injection and epitaxy processes, and a high doped buried layer is formed under the low doped layer; then, the high doped layer arranged under the source drain is etched off through a doped selective etching technology; next, holes left after the etching are filled with a medium to form an insulating layer positioned under the source drain, so the MOSFET transistor with the source drain arranged on the insulating layer is realized. The preparation method of the present invention is compatible with the traditional CMOS process. The prepared device has two new technology advantages of the nanometer MOSFET device, and has high practicability. The present invention is hopeful to be applied to future nanometer integrated circuits.
Description
Technical field:
The invention belongs to semiconductor integrated circuit and manufacturing technology field thereof, relate in particular to a provenance and leak the manufacture method that is positioned at the mosfet transistor on the insulating barrier.
Background technology:
The integrated circuit especially main devices in the very lagre scale integrated circuit (VLSIC) is metal-oxide semiconductor fieldeffect transistor (metal oxide semiconductor field effect transistor is called for short MOSFET).Device size constantly dwindle the performance that can improve the MOSFET device, can greatly improve the integration density of single chip simultaneously.And along with the continuous expansion of chip size, circuit function also constantly increases.Now, the physical dimension of MOSFET has entered into nanoscale.
When the physical dimension of MOSFET device enters into nanoscale, various microeffects occur in succession, have seriously influenced device performance and have dwindled further raising with size.Continue to improve the performance of device when making device dimensions shrink, various design of new processes and new device structure are constantly proposed.Wherein, most important two kinds of new technologies are silicon (SOI) and the Super halo doping techniques on the insulator.
Silicon on the insulator comprises that ultra-thin body (UTB) technology is undoubtedly a kind of very attractive technology that nanometer MOSFET device is made that is used for.But because the existence of burying oxygen in the SOI material, the SOI device has two intrinsic shortcomings, promptly so-called " floater effect " and " self-heating effect ".In addition, the UTB device is for the requirement of silicon film thickness, and to the conforming requirement of full sheet silicon film thickness, is difficult to realize in the also present SOI technology.
Super halo doping techniques also is a very important technology.When device dimensions shrink arrived deep-submicron yardstick and even nanoscale, Super halo mixes can reduce the short-channel effect of device extremely significantly, and good threshold voltage adjustments ability is provided.But Superhalo mixes needs point-device dopant profiles, and this is difficult to accomplish in the technology of reality; Secondly, utilize traditional body silicon MOSFET device of Super halo doping techniques to have bigger source to omit living electric capacity and electric leakage; Once more, because raceway groove is relatively still highly doped, because the threshold voltage amplitude of oscillation that the impurity fluctuation brings also is difficult to eliminate in Super halo doping MOSFET device.
A kind of new source is leaked the mosfet transistor that is positioned on the insulating barrier and can be solved the problem that above-mentioned technology exists.The source of this structure devices is leaked and is positioned on the insulating barrier, compares with traditional body silicon MOSFET device, and the source is omitted living electric capacity and reduced, and short-channel properties also has bigger improvement.Simultaneously, oxygen is not buried in the raceway groove below of this structure devices, and raceway groove directly links to each other with substrate, and raceway groove and substrate are electric coupling, can not produce the floater effect that causes owing to carrier accumulation, the heat that produces during device work can dissipate away in time by the silicon passage that buries in the oxygen.Like this, the floater effect of SOI device and self-heating effect have obtained solution.Utilize Super halo doping techniques and it is carried out its corresponding simplified, avoid the complexity of technology, new structure MOSFET device property has further raising.
Summary of the invention:
The purpose of this invention is to provide a kind of source for preparing and leak the method that is positioned at the mosfet transistor on the insulating barrier.
Technical scheme of the present invention is as follows:
One provenance is leaked the manufacture method of the MOS transistor on insulating barrier, may further comprise the steps:
(1) forms high-doped zone at semiconductor substrate surface;
(2) epitaxial growth one doping semiconductor layer not;
(3) form the shallow-trench isolation place;
(4) growth gate dielectric layer;
(5) deposit gate electrode layer and sacrificial dielectric layer, then the sacrificial dielectric layer of photoetching and the deposit of etching institute, gate electrode layer form gate electrode figure;
(6) side wall medium layer is sacrificed in deposit, and Hui Kehou forms side wall in the gate electrode both sides, be that mask corrosion falls gate dielectric layer with gate electrode and the side wall figure that forms, and the both sides substrate surface is exposed;
(7) corrode the substrate that is exposed, stop corrosion during to high-doped zone;
(8) selective etching high-doped zone stops corrosion when arriving grid covering place;
(9) deposit dielectric is filled the cavity that etching forms, and returns and carves the dielectric of removing the surface;
(10) erode after the sacrificial dielectric layer at gate electrode both sides and top deposit again or thermal oxide growth and form another film dielectric layer;
(11) ion implantation doping source-drain area and gate electrode return then to engrave and state film dielectric layer to form new gate electrode side wall;
(12) enter the conventional cmos later process at last, comprise deposit passivation layer, opening contact hole and metallization etc., can make described MOS transistor.
Above-mentioned manufacture method, described semiconductor substrate materials is selected from Si, Ge, SiGe, GaAs, or other II-VI, the binary and the ternary semiconductor of III-V and IV-IV family.
Above-mentioned manufacture method, the gate dielectric layer material in the described step (4) is a silicon dioxide.
Above-mentioned manufacture method, the method for described step (4) growth gate dielectric layer is selected from one of following method: conventional thermal oxidation, nitrating thermal oxidation, chemical vapor deposition, physical vapor deposition.
Above-mentioned manufacture method, the gate electrode layer material in the described step (5) is a polysilicon.
Above-mentioned manufacture method, the sacrificial dielectric layer material in the described step (5) is a silicon nitride, perhaps other all has high corrosion to select the thin-film material of ratio with silicon and silica.
Above-mentioned manufacture method, the sacrifice side wall medium layer material in the described step (6) is a silicon nitride, perhaps other all has high corrosion to select the thin-film material of ratio with silicon and silica.
Above-mentioned manufacture method, the etchant solution in the described step (8) are hydrofluoric acid and nitric acid system, and perhaps other has high corrosion to select the etchant solution prescription of ratio to semi-conducting materials such as doped silicons.
The packed layer of deposit is silicon dioxide or silicon nitride in the above-mentioned manufacture method, described step (9).
Above-mentioned manufacture method, described on high-doped zone the thickness 5-30nm of epitaxially grown not doping semiconductor layer; The thickness of gate dielectric layer is 1-1.5nm; The thickness of gate electrode layer is 80-150nm; The thickness of sacrificial dielectric layer is 20-40nm; The thickness of sacrificing side wall medium layer is 30-150nm; The lateral wall width that the gate electrode both sides form is that the thickness of 25-150nm film dielectric layer is 5-20nm.
The manufacture method of the MOS transistor on insulating barrier is leaked in source of the present invention, be to inject and epitaxy technique by diffusion or ion, form low doped layer at semiconductor substrate surface, and at the highly doped buried layer of its following formation, utilize selective etching technology that the high-doped zone under the leakage of source is eroded again to mixing, fill the hole that stays after the corrosion with medium afterwards, the insulating barrier that leaks down in the formation source, thus the mosfet transistor that is positioned on the insulating barrier is leaked in the realization source.
Advantage of the present invention and good effect:
Mosfet transistor its preparation process of the present invention is compatible mutually with traditional CMOS technology, utilizes from leakage two ends, source fluting high-doped zone is carried out selective etching, and this technical process is self aligned.With respect to the manufacture method of annotating the oxygen isolation technology, prepared process of the present invention is utilized the selective etching technology, less heat budget is arranged, can not cause damage simultaneously to the semiconductor film that leak in the source, can guarantee that device has less source to omit living resistance and good short-channel properties, helps improving the performance of device.Simultaneously, adopt its preparation process of the present invention, the tagma that links to each other with insulating barrier below the channel region in the mosfet transistor of preparation is highly doped, forms the Impurity Distribution that is doped to step function perpendicular to channel direction at channel region.The Superhalo that this Impurity Distribution can be regarded as simplification mixes, and can improve the short-channel properties of device.
Preparation method's technology of the present invention is simple, and the device of preparing combines the advantage of two kinds of new technologies of nanometer MOSFET device making technics, has higher utility, is expected to be applied in the nanometer integrated circuit in future.
Description of drawings:
Fig. 1 has illustrated at the processing step of substrate surface formation high-doped zone;
Fig. 2 has illustrated the processing step of on high-doped zone epitaxial growth silicon layer;
Fig. 3 has illustrated the processing step of shallow-trench isolation;
Fig. 4 has illustrated the processing step of growth gate dielectric layer;
Fig. 5 has illustrated gate electrode and sacrifice the processing step that side wall forms;
Fig. 6 has illustrated bulk silicon etching to form the processing step of silicon groove;
Fig. 7 has illustrated the processing step of the highly doped silicon layer of selective etching;
Fig. 8 has illustrated the processing step that the silicon groove is filled;
Fig. 9 has illustrated gate electrode side wall formation for the second time and source to leak the processing step that injects;
Among the figure:
1-silicon substrate 2-injects highly doped silicon area
3-epitaxial growth silicon fiml 4-shallow-trench isolation
5-gate oxide 6-silicon nitride side wall
The silicon groove that 7-polysilicon gate 8-RIE etching forms
The silicon groove 10-that the 9-selective etching forms fills the silicon dioxide of silicon groove
The drain region of 11-silicon dioxide side wall 12-device
The source region of 13-device
Embodiment:
One specific embodiment of manufacture method of the present invention comprises extremely processing step shown in Figure 9 of Fig. 1:
The crystal orientation of used monocrystalline substrate is (100), and the tagma is initially light dope, B
+Ion injects, and implantation dosage is 1e+16/cm
-2, the injection energy is 20KeV, obtains the highly doped silicon area in a surface, as shown in Figure 1.
Extension one undoped layer silicon fiml on highly doped silicon, thickness is 5-30nm, as shown in Figure 2.
Adopt conventional cmos shallow-trench isolation fabrication techniques active area isolation layer, as shown in Figure 3.
The gate dielectric layer of then growing, gate dielectric layer is a silicon dioxide, its thickness is 1-1.5nm.The formation method of gate medium can also be one of following method: conventional thermal oxidation, nitrating thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD), as shown in Figure 4.
Deposit gate electrode layer polysilicon layer and sacrificial dielectric layer silicon nitride, as shown in Figure 5.The thickness of polysilicon layer is 80-150nm, and the thickness of silicon nitride layer is 20-40nm.Then adopt the polysilicon layer and the sacrificial dielectric layer silicon nitride of the deposit of photoetching of conventional cmos technology and etching institute.The gate material of institute's deposit can also be the poly-SiGe alloy.With the sacrifice side wall medium layer silicon nitride of LPCVD deposit 30-150nm, then use back quarter (etch-back) technology to form width in the gate electrode both sides be the silicon nitride side wall of 25-150nm.Be the exposed part that mask corrosion falls the grid silicon dioxide layer with gate electrode and the side wall figure that forms then.
With the sacrificial dielectric layer silicon nitride mask corrosion part that semiconductor body was appeared to form the silicon groove.The degree of depth of silicon groove is 20-50nm.Owing to the silicon groove is that dielectric layer silicon nitride with the gate electrode both sides is that mask forms, so its structure and gate electrode are self aligned, as shown in Figure 6.
Adopt selective etching technology corroded high doping silicon layer, etchant solution is HF: HNO
3: CH
3COOH, volume ratio is 1 (40%): 3 (70%): 8 (100%), by the control etching time, when arriving the grid boundary, corrosion stops, as shown in Figure 7.
Adopt CVD deposit layer of silicon dioxide, in order to fill the beneath silicon groove of source leakage that corrosion brings, the insulating barrier under leak in the formation source, the silicon dioxide that goes back to removal surface at quarter.As shown in Figure 8.
Fall the sacrificial dielectric silicon nitride layer of all gate electrode tops and both sides with hot phosphoric acid corrosion, and another thickness of heat growth is the silica dioxide medium layer of 5-20nm, and as resilient coating, low energy ion injects the tagma part of dope gate electrode and gate electrode both sides, and dopant is an arsenic.Then the described ion of anisotropic dry etch injects resilient coating to form the gate electrode side wall and the tagma is exposed on the surface of gate electrode both sides, as shown in Figure 9.
Enter the conventional cmos later process at last, comprise deposit passivation layer, opening contact hole and metallization etc., can make described source and leak the MOS transistor that is positioned on the insulating barrier.
Claims (10)
1. a provenance is leaked the manufacture method that is positioned at the MOS transistor on the insulating barrier, may further comprise the steps:
(1) forms high-doped zone at semiconductor substrate surface;
(2) epitaxial growth one doping semiconductor layer not;
(3) form the shallow-trench isolation place;
(4) growth gate dielectric layer;
(5) deposit gate electrode layer and sacrificial dielectric layer, then photoetching and etching form gate electrode figure;
(6) side wall medium layer is sacrificed in deposit, and Hui Kehou forms side wall in the gate electrode both sides, be that mask corrosion falls gate dielectric layer with gate electrode and the side wall figure that forms, and the both sides substrate surface is exposed;
(7) corrode the substrate that is exposed, stop corrosion during to high-doped zone;
(8) selective etching high-doped zone stops corrosion when arriving grid covering place;
(9) deposit dielectric is filled the cavity that etching forms, and returns and carves the dielectric of removing the surface;
(10) erode after the sacrificial dielectric layer at gate electrode both sides and top deposit again or thermal oxide growth and form another film dielectric layer;
(11) ion implantation doping source-drain area and gate electrode return then to engrave and state film dielectric layer to form new gate electrode side wall;
(12) enter the CMOS later process at last, can make described MOS transistor.
2. manufacture method as claimed in claim 1 is characterized in that, the semiconductor substrate materials in the described step (1) is selected from Si, Ge, SiGe, GaAs, or other II-VI, III-V, a kind of in the binary of IV-IV family or the ternary compound.
3. manufacture method as claimed in claim 1 is characterized in that, the gate dielectric layer in the described step (4) is a silicon dioxide.
4. manufacture method as claimed in claim 2 is characterized in that, the method for described step (4) growth gate dielectric layer is selected from one of following method: conventional thermal oxidation, nitrating thermal oxidation, chemical vapor deposition, physical vapor deposition.
5. manufacture method as claimed in claim 1 is characterized in that, the gate electrode layer material in the described step (5) is polysilicon or poly-SiGe alloy.
6. manufacture method as claimed in claim 1 is characterized in that, the sacrificial dielectric layer material in the described step (5) is a silicon nitride.
7. manufacture method as claimed in claim 1 is characterized in that, the sacrifice side wall medium layer material in the described step (6) is a silicon nitride.
8. manufacture method as claimed in claim 1 is characterized in that, the etchant solution in the described step (8) is hydrofluoric acid and nitric acid system.
9. manufacture method as claimed in claim 1 is characterized in that, the dielectric of deposit is silicon dioxide or silicon nitride in the described step (9).
10. manufacture method as claimed in claim 1 is characterized in that, described on high-doped zone the thickness 5-30nm of epitaxially grown not doping semiconductor layer; The thickness of gate dielectric layer is 1-1.5nm; The thickness of gate electrode layer is 80-150nm; The thickness of sacrificial dielectric layer is 20-40nm; The thickness of sacrificing side wall medium layer is 30-150nm; The lateral wall width that the gate electrode both sides form is 25-150nm; The thickness of film dielectric layer is 5-20nm.
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| CNB2005100863242A CN100356528C (en) | 2005-08-31 | 2005-08-31 | Method for making MOS transistor with source-drain on insulating layer |
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| CN100356528C true CN100356528C (en) | 2007-12-19 |
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Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100440537C (en) * | 2006-04-11 | 2008-12-03 | 北京大学深圳研究生院 | Partial consumption SOI MOS transistor and making method |
| CN100414714C (en) * | 2006-07-21 | 2008-08-27 | 北京大学深圳研究生院 | MOS transistor with partial depletion SOI structure and producing method thereof |
| CN100527371C (en) * | 2007-09-14 | 2009-08-12 | 北京大学 | Portion exhausted SOI MOS transistor preparation method |
| CN101986435B (en) * | 2010-06-25 | 2012-12-19 | 中国科学院上海微系统与信息技术研究所 | Manufacturing method of metal oxide semiconductor (MOS) device structure for preventing floating body and self-heating effect |
| CN102903640B (en) * | 2012-10-23 | 2015-09-30 | 哈尔滨工程大学 | A kind of SOI MOSFET body contact formation method utilizing sacrifice layer |
| CN105322011A (en) * | 2014-07-16 | 2016-02-10 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| US9306003B2 (en) | 2014-07-16 | 2016-04-05 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor device and method for manufacturing the same |
| CN105322010B (en) * | 2014-07-16 | 2019-05-28 | 中国科学院微电子研究所 | The manufacturing method of semiconductor devices |
| CN105322012B (en) * | 2014-07-16 | 2018-12-04 | 中国科学院微电子研究所 | Semiconductor devices and its manufacturing method |
| CN105304628B (en) * | 2014-07-16 | 2018-06-01 | 中国科学院微电子研究所 | Semiconductor devices and its manufacturing method |
| CN105990144B (en) * | 2015-02-04 | 2021-04-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| CN105990143B (en) * | 2015-02-04 | 2019-12-10 | 中芯国际集成电路制造(上海)有限公司 | semiconductor device, manufacturing method thereof and electronic device |
| CN105097822B (en) * | 2015-09-12 | 2018-09-18 | 中国科学院微电子研究所 | Semiconductor devices and its manufacturing method |
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| US20040094797A1 (en) * | 2002-11-18 | 2004-05-20 | Il-Yong Park | MOS transistor having short channel and manufacturing method thereof |
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| US20050095796A1 (en) * | 2003-10-31 | 2005-05-05 | Van Bentum Ralf | Technique for forming a transistor having raised drain and source regions with a reduced number of process steps |
| US20050139932A1 (en) * | 2003-12-31 | 2005-06-30 | Cho Yong S. | Transistors of semiconductor devices and methods of fabricating the same |
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Patent Citations (5)
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| US20040029349A1 (en) * | 2002-07-25 | 2004-02-12 | Yongsoo Cho | Methods of fabricating a MOSFET |
| US20040094797A1 (en) * | 2002-11-18 | 2004-05-20 | Il-Yong Park | MOS transistor having short channel and manufacturing method thereof |
| US20050026379A1 (en) * | 2003-07-31 | 2005-02-03 | Thorsten Kammler | Polysilicon line having a metal silicide region enabling linewidth scaling |
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| US20050139932A1 (en) * | 2003-12-31 | 2005-06-30 | Cho Yong S. | Transistors of semiconductor devices and methods of fabricating the same |
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