CN105322012B - Semiconductor devices and its manufacturing method - Google Patents
Semiconductor devices and its manufacturing method Download PDFInfo
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- CN105322012B CN105322012B CN201410340104.7A CN201410340104A CN105322012B CN 105322012 B CN105322012 B CN 105322012B CN 201410340104 A CN201410340104 A CN 201410340104A CN 105322012 B CN105322012 B CN 105322012B
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Abstract
The present invention provides a kind of semiconductor devices, comprising: first area includes substrate, and the substrate has the first semiconductor material；Second semiconductor layer is located at substrate；Third semiconductor layer is located at the second semiconductor layer, is the first nmosfet formation region；First isolation structure is located at third semiconductor layer two sides, substrate；Cavity, under the source and drain areas of third semiconductor layer, between the first isolation structure and the second semiconductor layer end；Second area includes substrate；Second device of substrate；Second isolation structure, on the substrate of the second device two sides.Device of the invention has the characteristics that low cost, electric leakage is small, low in energy consumption, speed is fast, technique is relatively simple and integrated level is high.Meanwhile compared with SOI device, floater effect and self-heating effect are eliminated.In addition, lower dielectric constant at cavity, so that it can bear higher voltage.
Description
Technical field
The present invention relates to field of semiconductor devices, in particular to a kind of semiconductor devices and its manufacturing method.
Background technique
With the continuous diminution of device size, the device count on unit area chip is more and more, this will lead to dynamic
The increase of power consumption, meanwhile, the continuous of device size reduces the increase for necessarily causing leakage current, and then causes the increasing of quiescent dissipation
Add, and it is highly integrated with semiconductor devices, and MOSFET channel length constantly shortens, a series of in MOSFET long channel model
In negligible effect become more significant, or even as the leading factor for influencing device performance, this phenomenon is referred to as short
Channelling effect.Short-channel effect can deteriorate the electric property of device, and threshold voltage of the grid decline, power consumption is such as caused to increase and believe
The problems such as making an uproar than declining.
SOI substrate is that silicon dioxide layer is embedded in below silicon, the device formed relative to body silicon device, SOI substrate
Leakage current and power consumption can be obviously reduced, improve short-channel effect, there is apparent performance advantage.However, the cost of SOI substrate
It is higher, and need bigger device area to avoid floater effect (Floating Body Effect), it is difficult to meet device height
Integrated requirement is spent, further, since being embedded in silicon dioxide layer, the heat dissipation performance of device is affected.
Summary of the invention
The purpose of the present invention aims to solve at least one of above-mentioned technological deficiency, provides a kind of semiconductor devices and its manufacturer
Method.
The present invention provides a kind of semiconductor devices, comprising:
First area includes
Substrate, the substrate have the first semiconductor material；
Second semiconductor layer is located at substrate；
Third semiconductor layer is located at the second semiconductor layer, is the first nmosfet formation region；Described the second half are etched to lead
Body layer and the third semiconductor layer are to form active area and the first isolated groove；It is removed from the end of second semiconductor layer
The second partial semiconductor layer makes second semiconductor layer be made only in the ditch of the third semiconductor layer to form opening
Below road region；
First isolation structure is located at third semiconductor layer two sides, substrate；
Cavity, under the source and drain areas of third semiconductor layer, the first isolation structure and the second semiconductor layer end it
Between；
Second area includes
Substrate；
Second device of substrate；
Second isolation structure, on the substrate of the second device two sides.
Optionally, the substrate is body silicon substrate, and the second semiconductor layer is GexSi1-x, 0 < x < 1, third semiconductor layer is
Silicon.
Optionally, further includes:
Oxide skin(coating), on the surface of semiconductor material for constituting cavity.
Optionally, also shape between the first isolation structure and substrate and between third semiconductor layer and the first isolation structure
At there is oxide skin(coating), oxide skin(coating) is also formed between the second isolation structure and substrate.
Optionally, second area also includes third semiconductor layer formed on substrate, and the second device is located on substrate
On third semiconductor layer.
In addition, the present invention also provides a kind of manufacturing methods of semiconductor devices, comprising steps of
The substrate with the first semiconductor material is provided, the substrate has first area and second area；
The second semiconductor layer is formed on the first area of substrate, and third semiconductor is formed on the second semiconductor layer
Layer；
Second semiconductor layer and the third semiconductor layer are etched to form active area and isolated groove；From the second half
Second semiconductor layer of the end removal part of conductor layer is made only in second semiconductor layer described to form opening
Below the channel region of third semiconductor layer；
The first isolation structure is formed in third semiconductor layer two sides, substrate, forms the in the substrate of second area
Two isolation structures, and form cavity, the cavity is located under the source and drain areas of third semiconductor layer, the first isolation structure and
Between two semiconductor layer ends；
The first device is formed on the third semiconductor layer of first area, forms the second device on the substrate of second area
Part,.
Optionally, the step of forming the second semiconductor layer and third semiconductor layer on the first area of substrate specifically:
The first exposure mask is formed on the second area of substrate；
The second semiconductor layer of epitaxial growth on the first area of substrate；
Remove the first exposure mask；
The epitaxial growth third semiconductor layer on the substrate of the second semiconductor layer and second area；
Etch the second semiconductor layer and third semiconductor layer, with first area formed patterned second semiconductor layer and
Third semiconductor layer and the first isolated groove, and active area and the second isolated groove are formed in second area.
Optionally, the substrate is body silicon substrate, and the second semiconductor layer is GexSi1-x, 0 < x < 1, third semiconductor layer is
Silicon.
Optionally, from the second semiconductor layer of the end of the second semiconductor layer removal part, have the step of opening to be formed
Body includes:
Using wet etching, the second semiconductor layer of selective removal is open with being formed in the end of the second semiconductor layer.
Optionally, after the opening is formed, it is formed before isolation structure, is further comprised the steps of:
Oxidation technology is carried out, forms oxidation on the surface of the exposure of substrate, the second semiconductor layer, third semiconductor layer
Layer.
Semiconductor devices provided in an embodiment of the present invention and its manufacturing method are integrated there are two types of device, wherein are forming the
Be formed with the structure of cavity under the source and drain areas of the third semiconductor layer of one device, and the channel region of third semiconductor layer it
It is down semiconductor layer.Such device architecture, while there is the respective advantage of body silicon device and SOI device, there is low cost, leakage
The feature that electricity is small, low in energy consumption, speed is fast, technique is relatively simple and integrated level is high.Meanwhile compared with SOI device, floating body is eliminated
Effect and self-heating effect.In addition, lower dielectric constant at cavity, so that it can bear higher voltage.
Detailed description of the invention
Above-mentioned and/or additional aspect and advantage of the invention will become from the following description of the accompanying drawings of embodiments
Obviously and it is readily appreciated that, in which:
Fig. 1-Figure 10 shows the schematic diagram of each formation stages of semiconductor devices according to an embodiment of the present invention；
Figure 11 shows the flow chart of the manufacturing method of semiconductor devices according to an embodiment of the present invention.
Specific embodiment
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, and for explaining only the invention, and is not construed as limiting the claims.
The present invention is directed to propose a kind of semiconductor devices, with reference to shown in Fig. 9,10, which includes first area
100 and second area 200, in which:
First area 100 includes
Substrate 10, the substrate have the first semiconductor material；
Second semiconductor layer 13 is located at substrate；
Third semiconductor layer 14 is located on the second semiconductor layer 13, is 30 forming region of the first device；
First isolation structure 23, on 14 two sides of third semiconductor layer, substrate 10；
Cavity 22, under the source and drain areas of third semiconductor layer 14, the first isolation structure 23 and the second semiconductor layer
Between 13 ends；
Second area 200 includes
Substrate 10；
The second device on substrate 10；
Second isolation structure 24, on the substrate of 40 two sides of the second device.
In the present invention, the substrate in first area forms the second semiconductor layer, second semiconductor layer
There is the third semiconductor layer for being used to form the first device, which is made only in the channel region of third semiconductor layer
Lower section, and the second semiconductor layer be isolated between, the structure of cavity is formed with below source and drain areas, in this way, can pass through
Body silicon substrate forms device, reduces manufacturing cost, further, since the presence of cavity, can be obviously reduced leakage current and function
Consumption, while relative to SOI device, the integrated requirement of element height can be better met, channel region has preferably heat dissipation
The dielectric constant of performance, device is lower, and resistance to pressure is stronger.The device is easy to same traditional devices and integrates, and meets different circuit designs
Demand.
In addition, device of the invention is applicable to the environment of intense radiation, such as strategic arms, due under channel and non-oxidation
The insulating layer of silicon reduces radiation sensitive region area, and can be adjusted by backgate, discharges electricity caused by partial illumination
Sub- hole pair avoids irradiating caused floater effect.
In the present invention, it can be needed in a manufacturing process according to device and the demand of device performance, select substrate, the
The material of two semiconductor layers, third semiconductor layer can use identical or different semiconductor material, in preferred reality of the invention
It applies in example, the substrate is body silicon substrate, and the second semiconductor layer is GexSi1-x, 0 < x < 1, third semiconductor layer is silicon, this half
The selection of conductor material is convenient for by second, third semiconductor layer for being epitaxially-formed crystal, device has superior property
Energy.
In the present invention, the second device is formed on substrate, i.e. the part-structure of its device, as doped region can be formed only
In the substrate, it can also be formed in other semiconductor layers on substrate, in an embodiment of the present invention, as shown in Figures 9 and 10,
Second device 40 is formed on another semiconductor layer 14 on substrate, and the doped region of the second device can form half on substrate
It in conductor layer, can also be formed in the semiconductor layer on substrate and substrate, specifically, which can be and the firstth area
The semiconductor layer that the third semiconductor layer in domain is formed together.
In addition, oxide skin(coating) 16 is formed on the surface of the semiconductor material of cavity, i.e., third semiconductor layer in cavity
Surface, be formed with oxide skin(coating) 16 on the side of the second semiconductor layer and the surface of substrate, further, in third half
23 oxide skin(coating) 16 is also formed between 23 and substrate 10 and isolation structure between conductor layer 12 and isolation structure, the second isolation
Oxide skin(coating) 16 is also formed between structure 24 and substrate and third semiconductor layer, the formation of the oxide skin(coating) can eliminate quarter
The surface defect formed in the technical process such as erosion, so that surface planarisation.The oxide skin(coating) 16 can be ultra-thin oxide skin(coating),
Thickness exists
In addition, the present invention also provides the manufacturing methods of above-mentioned semiconductor device, skill in order to better understand the present invention
Art scheme and technical effect are described in detail specific embodiment below with reference to flow chart 11.
Firstly, providing the substrate 10 with the first semiconductor material in step S01, the substrate has first area 100
With second area 200, with reference to shown in Fig. 1.
The substrate is semiconductor substrate in the present invention, preferably can for single two body substrate of semiconductor material,
Such as can be Si substrate, Ge substrate, SiGe substrate, it can also be the lining for including other elements semiconductor or compound semiconductor
Bottom, such as GaAs, InP or SiC etc., in the present embodiment, the substrate are body silicon substrate.
Then, it in step S02, forms the second semiconductor layer 13 on the first area of substrate 100, and is led the second half
Third semiconductor layer 14 is formed on body layer 13, with reference to shown in Fig. 6.
In the present embodiment, specific the following steps are included:
Firstly, the first exposure mask 11 is formed on the second area 200 of substrate, with reference to shown in Fig. 2.
As shown in Figure 1, the first mask material 11 can first be deposited on substrate, as silica then smears photosensitive etching
Agent 12-1 (photoresist) is simultaneously performed etching, and only forms the first mask layer 11 on the second region, and photosensitive etching agent is gone
It removes, as shown in Figure 2.
Then, the second semiconductor layer of epitaxial growth 13 on the first area of substrate, with reference to shown in Fig. 3.
It can carry out epitaxial growth GexSi1-xThe second semiconductor material 13, wherein 0 < x < 1, since second area is by
The covering of one exposure mask 11, has only been epitaxially formed the second semiconductor layer 13, as shown in Figure 3 on the substrate 10 of first area.
Then, first exposure mask 11 is removed, to expose the substrate 10 of second area 200, with reference to shown in Fig. 4.
Then, epitaxial growth third semiconductor layer 14 is carried out, with reference to shown in Fig. 4.
The third semiconductor material that can carry out epitaxial growth Si, on the substrate of the second semiconductor layer and second area all
Third semiconductor material 14 is formd, as shown in Figure 4.
Then, the second semiconductor layer and third semiconductor layer are etched, to form patterned the second half in first area 100
Conductor layer 13 and third semiconductor layer 14 and the first isolated groove 20, and second area 200 formed active area and second every
From groove 21, with reference to shown in Fig. 6.
Specifically, first carry out the deposit of the second exposure mask 15, second exposure mask for example can for silicon nitride, silica or they
Combination, and photosensitive etching agent 12-2 (photoresist) is smeared on first area and second area, as shown in figure 5, going forward side by side
Row etching, forms patterned second exposure mask 15, and perform etching under the cover of second exposure mask, in first area 100, carves
13 grades of third semiconductor layers 14 of the second semiconductor layer are lost, in second area 200, etch third semiconductor layer 14, respectively the
One region 100 and second area 200 form active area and isolated groove, as shown in Figure 6.
In the present embodiment, the second semiconductor layer is formed by the way of selective epitaxial growth, in this way, first can be made
The device area in region is consistent with traditional devices, avoid due to the second semiconductor layer there are caused by bring additional stress
The reduction of device mobility improves the performance of device.
It certainly, is only preferred embodiment herein, it in other embodiments of the invention, can also be traditional by other
Technique forms the second semiconductor layer and third semiconductor layer on the first region, for example, depositing second, third semiconductor layer
Later, etch away second on second area and the method for third semiconductor layer formed.
Then, in step S03, the second semiconductor layer of part is removed from the end of the second semiconductor layer, to form opening
22, with reference to shown in Fig. 7.
It in the present embodiment, can be using wet etching, the second semiconductor layer 13 of selective removal part, specifically
, solvent can use 49% HF, 30%H2O2, 99.8% CH3COOH and H2The mixed solution of O, ratio 1:18:27:
8, by controlling the time, the second semiconductor layer of both ends part is removed, namely under the source-drain area of 100 active area of first area
Without the support of the second semiconductor layer, for empty part.
Then, oxidation technology is carried out.
In the present embodiment, by dry oxidation, such as rapid thermal oxidation, to form ultra-thin oxide skin(coating), thickness can
ThinkAfter thermal oxide, oxide skin(coating) is all formd on the surface of exposed semiconductor material, in substrate,
Oxide layer 16 is formed on the surface of the exposure of two semiconductor layers, third semiconductor layer, as shown in Figure 8.
Then, in step S04, the first isolation structure 23 is formed in third semiconductor layer two sides, substrate, in the secondth area
The second isolation structure 24 is formed in the substrate in domain, with reference to shown in Fig. 9.
In the present embodiment, the isolation structure 23,24 can be formed by traditional handicraft, firstly, carrying out dielectric material
Deposit, such as silica；Then, it is planarized, such as carries out chemical mechanical grinding (CMP), thickness monitor can be passed through
Or the method for terminal triggering so that CMP is stopped at the target thickness of the second exposure mask, in the CMP step, first area still
Retain the second exposure mask of segment thickness, so that active area is injury-free in a cmp process, then, the property of can choose etching will
Remaining second exposure mask 15 removes, refering to what is shown in Fig. 10, to form isolation structure 23,24 and cavity 22.
Finally, forming the first device 30 on third semiconductor layer in step S05, being formed on the substrate of second area
Second device 40, wherein opening 22 is located under the source and drain areas of third semiconductor layer, with reference to shown in Figure 10.
It can form device according to traditional technique, in the present embodiment, divide in first area 100 and second area 200
Cmos device 30,40 is not formd, as shown in Figure 10, in the firstth area, 100, trap doping 31 is formed in third semiconductor layer 14, the
In two semiconductor layers 13 and partial substrate 10, gate structure 32 is formd on the third semiconductor layer 14 of first area；
Side wall 33 is formd on the side wall of the gate structure 32；Source and drain is formd in the third semiconductor layer of 32 two sides of gate structure
Area 34, the source-drain area 34 are located on cavity 22；Metal silicide layer 35 is also formed on source-drain area 34.
In second area 200, trap doping 41 is formed in third semiconductor layer 14 and partial substrate 10, in second area
Third semiconductor layer 14 on form gate structure 42；Side wall 43 is formd on the side wall of the gate structure 42；In grid
Source-drain area 44 is formd in the third semiconductor layer of 42 two sides of pole structure；Metal silicide layer is also formed on source-drain area 44
45.In other embodiments, third semiconductor layer can not be formed on second area, the second device is formed directly into substrate
On, doped region is formed in the substrate, identical as common body silicon device.
Later, the other component of device, such as source and drain contact, gate contact and interconnection structure can also be formed.
So far the integrated of two kinds of devices of the embodiment of the present invention, in the present embodiment, the shape by the way of extension are completed
At the second semiconductor layer and third semiconductor layer, the presence for avoiding the second semiconductor layer may bring additional stress, lead to device
The problem of part mobility reduces, meanwhile, it is sufficiently combined for the device of cavity with traditional body silicon device technique under the source and drain of formation
Together, meet the multifarious requirement of circuit performance, while not influencing the electric property of traditional devices.
The above described is only a preferred embodiment of the present invention, being not intended to limit the present invention in any form.
Although the present invention has been disclosed in the preferred embodiments as above, however, it is not intended to limit the invention.It is any to be familiar with ability
The technical staff in domain, without departing from the scope of the technical proposal of the invention, all using in the methods and techniques of the disclosure above
Appearance makes many possible changes and modifications or equivalent example modified to equivalent change to technical solution of the present invention.Therefore,
Anything that does not depart from the technical scheme of the invention are made to the above embodiment any simple according to the technical essence of the invention
Modification, equivalent variations and modification, all of which are still within the scope of protection of the technical scheme of the invention.
Claims (10)
1. a kind of semiconductor devices, including first area and second area；Wherein,
First area includes
Substrate, the substrate have the first semiconductor material；
Second semiconductor layer is located at substrate, wherein second semiconductor layer is GexSi1-x, 0 < x < 1；
Third semiconductor layer is located at the second semiconductor layer, is the first nmosfet formation region；Etch second semiconductor layer
With the third semiconductor layer to form active area and the first isolated groove；Part is removed from the end of second semiconductor layer
The second semiconductor layer, with formed opening, so that second semiconductor layer is made only in the channel region of the third semiconductor layer
Below domain；
First isolation structure is located at third semiconductor layer two sides, substrate；
Cavity, under the source and drain areas of third semiconductor layer, between the first isolation structure and the second semiconductor layer end；The
Two regions include
Substrate；
Second device of substrate；
Second isolation structure, on the substrate of the second device two sides.
2. semiconductor devices according to claim 1, which is characterized in that the substrate is body silicon substrate, third semiconductor
Layer is silicon.
3. semiconductor devices according to claim 1, which is characterized in that further include:
Oxide skin(coating), on the surface of semiconductor material for constituting cavity.
4. semiconductor devices according to claim 3, which is characterized in that between the first isolation structure and substrate and
It is also formed with oxide skin(coating) between three semiconductor layers and the first isolation structure, is also formed with oxygen between the second isolation structure and substrate
Compound layer.
5. semiconductor devices according to claim 1, which is characterized in that second area also includes formed on substrate
Third semiconductor layer, the second device are located on the third semiconductor layer on substrate.
6. a kind of manufacturing method of semiconductor devices, which is characterized in that comprising steps of
The substrate with the first semiconductor material is provided, the substrate has first area and second area；
The second semiconductor layer is formed on the first area of substrate, and third semiconductor layer is formed on the second semiconductor layer,
Wherein, second semiconductor layer is GexSi1-x, 0 < x < 1；
Second semiconductor layer and the third semiconductor layer are etched to form active area and isolated groove；From the second semiconductor
Second semiconductor layer of the end removal part of layer makes second semiconductor layer be made only in the third to form opening
Below the channel region of semiconductor layer；
Third semiconductor layer two sides, substrate formed the first isolation structure, on the substrate of second area formed second every
From structure, and cavity is formed, the cavity is located under the source and drain areas of third semiconductor layer, the first isolation structure and the second half
Between conductor layer end；
The first device is formed on the third semiconductor layer of first area, forms the second device on the substrate of second area.
7. manufacturing method according to claim 6, which is characterized in that form the second semiconductor on the first area of substrate
The step of layer and third semiconductor layer specifically:
The first exposure mask is formed on the second area of substrate；
The second semiconductor layer of epitaxial growth on the first area of substrate；
Remove the first exposure mask；
The epitaxial growth third semiconductor layer on the substrate of the second semiconductor layer and second area；
The second semiconductor layer and third semiconductor layer are etched, to form patterned second semiconductor layer and third in first area
Semiconductor layer and the first isolated groove, and active area and the second isolated groove are formed in second area.
8. manufacturing method according to claim 7, which is characterized in that the substrate is body silicon substrate, third semiconductor layer
For silicon.
9. manufacturing method according to claim 6, which is characterized in that from the of the end of the second semiconductor layer removal part
Two semiconductor layers are specifically included the step of opening with being formed:
Using wet etching, the second semiconductor layer of selective removal is open with being formed in the end of the second semiconductor layer.
10. manufacturing method according to claim 6, which is characterized in that after the opening is formed, formed isolation structure it
Before, it further comprises the steps of:
Oxidation technology is carried out, forms oxide layer on the surface of the exposure of substrate, the second semiconductor layer, third semiconductor layer.
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| CN201410340104.7A CN105322012B (en) | 2014-07-16 | 2014-07-16 | Semiconductor devices and its manufacturing method |
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|---|---|---|---|
| CN201410340104.7A CN105322012B (en) | 2014-07-16 | 2014-07-16 | Semiconductor devices and its manufacturing method |
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| CN105322012B true CN105322012B (en) | 2018-12-04 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6448115B1 (en) * | 1999-10-12 | 2002-09-10 | Samsung Electronics Co., Ltd. | Semiconductor device having quasi-SOI structure and manufacturing method thereof |
| CN1542965A (en) * | 2003-05-02 | 2004-11-03 | 三星电子株式会社 | Integrated circuit devices having an epitaxial pattern with a void region formed therein and methods of forming the same |
| CN1731570A (en) * | 2005-08-31 | 2006-02-08 | 北京大学 | Method for making MOS transistor with source-drain on insulating layer |
-
2014
- 2014-07-16 CN CN201410340104.7A patent/CN105322012B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6448115B1 (en) * | 1999-10-12 | 2002-09-10 | Samsung Electronics Co., Ltd. | Semiconductor device having quasi-SOI structure and manufacturing method thereof |
| CN1542965A (en) * | 2003-05-02 | 2004-11-03 | 三星电子株式会社 | Integrated circuit devices having an epitaxial pattern with a void region formed therein and methods of forming the same |
| CN1731570A (en) * | 2005-08-31 | 2006-02-08 | 北京大学 | Method for making MOS transistor with source-drain on insulating layer |
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| CN105322012A (en) | 2016-02-10 |
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