CN105304629B - Semiconductor devices and its manufacturing method - Google Patents
Semiconductor devices and its manufacturing method Download PDFInfo
- Publication number
- CN105304629B CN105304629B CN201410339866.5A CN201410339866A CN105304629B CN 105304629 B CN105304629 B CN 105304629B CN 201410339866 A CN201410339866 A CN 201410339866A CN 105304629 B CN105304629 B CN 105304629B
- Authority
- CN
- China
- Prior art keywords
- semiconductor
- substrate
- area
- semiconductor layer
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Thin Film Transistor (AREA)
- Element Separation (AREA)
Abstract
The present invention provides a kind of semiconductor devices, including the first device area：Substrate；First active area stacks, including the first semiconductor region on substrate and the second semiconductor region thereon and cavity, cavity are located between end, the second semiconductor region and the substrate of the first semiconductor region；First device is located on the second semiconductor region, and its source-drain area is located on cavity；Second device area：Substrate；Second active area stacks, including third semiconductor region on substrate and the 4th semiconductor region thereon and insulating layer, insulating layer are located between end, the 4th semiconductor region and the substrate of third semiconductor region；Second device is located on the 4th semiconductor region, and its source-drain area is located on insulating layer.The semiconductor devices has the characteristics that low cost, electric leakage is small, low in energy consumption, speed is fast, technique is relatively simple and integrated level is high.
Description
Technical field
The present invention relates to field of semiconductor devices, more particularly to a kind of semiconductor devices and its manufacturing method.
Background technology
With the continuous diminution of device size, the device count on unit area chip is more and more, this can lead to dynamic
The increase of power consumption, meanwhile, the continuous of device size reduces the increase for necessarily causing leakage current, and then causes the increasing of quiescent dissipation
Add, and it is highly integrated with semiconductor devices, and MOSFET channel length constantly shortens, a series of in MOSFET long raceway groove models
In negligible effect become more significantly, or even as influence device performance leading factor, this phenomenon is referred to as short
Channelling effect.Short-channel effect can deteriorate the electric property of device, such as cause threshold voltage of the grid to decline, power consumption increases and letter
The problems such as making an uproar than declining.
SOI substrate is that silicon dioxide layer is embedded in below silicon, the device formed relative to body silicon device, SOI substrate
Leakage current and power consumption can be obviously reduced, improve short-channel effect, there is apparent performance advantage.However, the cost of SOI substrate
It is higher, and need the device area of bigger to avoid floater effect (Floating Body Effect), it is difficult to meet device height
Integrated requirement is spent, further, since being embedded in silicon dioxide layer, the heat dissipation performance of device is affected.
Invention content
The purpose of the present invention aims to solve at least one of above-mentioned technological deficiency, provides a kind of semiconductor devices and its manufacturer
Method.
The present invention provides a kind of semiconductor devices, including the first device area and the second device area, wherein
First device area includes：
Substrate；
First active area stacks, including the first semiconductor region on substrate and the second semiconductor region thereon and cavity,
Cavity is located between end, the second semiconductor region and the substrate of the first semiconductor region；
First device is located on the second semiconductor region, and its source-drain area is located on cavity；
Second device area includes：
Substrate；
Second active area stacks, including the third semiconductor region on substrate and the 4th semiconductor region thereon, and insulation
Layer, insulating layer are located between end, the 4th semiconductor region and the substrate of third semiconductor region；
Second device is located on the 4th semiconductor region, and its source-drain area is located on insulating layer.
Optionally, further include third device area, the third device area includes：
Substrate；
Third device is located at substrate.
Optionally, the first semiconductor region includes that the third on the second semiconductor layer and the second semiconductor layer on substrate is partly led
Body layer, the second semiconductor region are the 4th semiconductor layer；Third semiconductor region is the second semiconductor layer, and the 4th semiconductor region is the 4th
Semiconductor layer.
Optionally, the substrate is body silicon substrate, and the second semiconductor layer and third semiconductor layer are GexSi1-x, 0<x<1,
4th semiconductor layer is silicon.
Optionally, the first device area further includes oxide skin(coating), is formed on the surface of the semi-conducting material of cavity.
In addition, the present invention also provides a kind of manufacturing method of semiconductor devices, including step：
S01, provides substrate, and the substrate has first area and second area；
S02 forms the first semiconductor region and the second semiconductor region thereon on the first area of substrate, and in substrate
Second area on form third semiconductor region and the 4th semiconductor region thereon；
S03 forms the first opening and the second opening in the end of the first semiconductor region and third semiconductor region respectively；It fills up
Second opening, to form insulating layer；
S04 forms the first device and the second device on the second semiconductor region and the 4th semiconductor region respectively.
Optionally, the substrate also has third region；
In step S04, further include：Third device is formed on the substrate in third region.
Optionally, step S02 is specifically included：
The second semiconductor layer of epitaxial growth on first area and second area；
The epitaxial growth third semiconductor layer on the second semiconductor layer of first area；
Epitaxial growth is carried out, forms the 4th semiconductor on the second semiconductor layer of third semiconductor layer and second area
Layer；
It performs etching, it includes the first the half of the second semiconductor layer and third semiconductor layer to be formed patterned in first area
Conductor region and the second semiconductor region for including the 4th semiconductor layer, it includes the second semiconductor layer to be formed patterned in second area
Third semiconductor region and include the 4th semiconductor region of the 4th semiconductor layer, the opening of the 4th semiconductor layer both sides is isolating trenches
Slot.
Optionally, the substrate also has third region；The step of progress epitaxial growth further includes：In third region
Substrate on formed the 4th semiconductor layer；
Described the step of performing etching further includes：Patterned 4th semiconductor layer is formed on the third area；
Further include in step S04：Third device is formed on the 4th semiconductor layer in third region.
Optionally, the step of filling up the second opening specifically includes：Oxidation technology is carried out, so that full of the in the second opening
The oxide skin(coating) of the semi-conducting material of two open surfaces forms the semi-conducting materials of the first open surfaces on the surface of the first opening
Oxide skin(coating).
Semiconductor devices provided in an embodiment of the present invention and its manufacturing method are integrated there are two types of device, and a kind of device has
It is formed with cavity under the end of source region, insulating layer is formed under the end of the active area of another device, and is half under channel region
Conductor region.Such device architecture, while there is the respective advantage of body silicon device and SOI device, have low cost, electric leakage it is small,
Feature low in energy consumption, speed is fast, technique is relatively simple and integrated level is high.Meanwhile compared with SOI device, floater effect is eliminated
And self-heating effect.In addition, the device with cavity is with lower dielectric constant so that it can bear higher voltage.And
It is easy to integrated with the device of other structures, meets the needs of different circuit performances.
Description of the drawings
Above-mentioned and/or additional aspect and advantage of the invention will become from the following description of the accompanying drawings of embodiments
Obviously and it is readily appreciated that, wherein：
Fig. 1-Figure 11 shows the schematic diagram of each formation stages of semiconductor devices according to the ... of the embodiment of the present invention；
Figure 12 shows the flow chart of the manufacturing method of semiconductor devices according to the ... of the embodiment of the present invention.
Specific implementation mode
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, and is only used for explaining the present invention, and is not construed as limiting the claims.
The present invention is directed to propose a kind of semiconductor devices, with reference to shown in figure 10,11, which includes：
First device area 100：
Substrate 10；
First active area stacks, including the first semiconductor region 13-1,15 and the second semiconductor region 16- thereon on substrate
1 and cavity 22, cavity 22 be located at the first semiconductor region 13-1,15 end, the second semiconductor region 1-16 and substrate 10 it
Between；
First device 30 is located on the second semiconductor region 16-1, and its source-drain area 34 is located on cavity 22；
Second device area 200：
Substrate 10；
Second active area stacks, including the third semiconductor region 13-2 on substrate and the 4th semiconductor region 16-2 thereon,
And insulating layer 26, insulating layer 26 are located between end, the 4th semiconductor region 16-2 and the substrate 10 of third semiconductor region 13-2；
Second device 40 is located on the 4th semiconductor region 16-2, and its source-drain area 44 is located on insulating layer 26.
In the present invention, it integrates there are two types of device, cavity, another device is formed under a kind of end of the active area of device
It is formed with insulating layer under the end of the active area of part, and under channel region is semiconductor region.In this way, depositing due to insulating layer or cavity
, hence it is evident that the leakage current and power consumption for reducing device increase the integrated level of device.Compared with SOI device, below channel region
It is connected with substrate, there is better heat dissipation performance and avoids the generation of floater effect.Simultaneously as body silicon may be used in device
Substrate avoids the excessively high limitation of SOI wafer cost.Two kinds of devices are easily integrated, and meet the needs of different circuits.
In addition, the device of the present invention is applicable to the environment of intense radiation, such as strategic arms, due under raceway groove and non-oxidation
The insulating layer of silicon reduces radiation sensitive region area, and can be adjusted by backgate, discharges electricity caused by partial illumination
Sub- hole pair avoids irradiating caused floater effect.
The device architecture of the present invention is easy to integrated with the device of other structures, to meet the needs of different circuit performances, such as
Shown in Figure 11, it is also integrated with third device area 300, which includes：
Substrate 10；
Third device 50 is located on substrate 10.
In the present invention, third device is formed on substrate, i.e. the part-structure of its device, as doped region can be formed only
In the substrate, it can also be formed in other semiconductor layers on substrate, in an embodiment of the present invention, as shown in Figure 10,11,
Third device 50 is formed on semiconductor layer 16 on substrate, and the doped region of third device can form semiconductor on substrate
Layer in, can also be formed in the semiconductor layer on substrate and substrate, specifically, the semiconductor layer can be with first area and
The semiconductor layer that the semiconductor region of second area is formed together.
In the present invention, it can in a manufacturing process be needed according to device and the demand of device performance, select substrate, the
Semiconductor area, the second semiconductor region, third semiconductor region and the 4th semiconductor region material, may be used identical or different
Semi-conducting material.In the particular embodiment, the first semiconductor region includes the second semiconductor layer and the second semiconductor on substrate
Third semiconductor layer on layer, the second semiconductor region are the 4th semiconductor layer；Third semiconductor region be the second semiconductor layer, the 4th
Semiconductor region is the 4th semiconductor layer, and third device is formed on the 4th semiconductor layer.In a preferred embodiment of the invention, institute
It is body silicon substrate to state substrate, and the second semiconductor layer and third semiconductor layer are GexSi1-x, 0<x<1, the 4th semiconductor layer is silicon,
The selection of this semi-conducting material is convenient for by the semiconductor region for being epitaxially-formed crystal, device has superior performance.
In embodiments of the present invention, the first device area further includes oxide skin(coating) 19, which can be ultra-thin
Oxide skin(coating), thickness existsIt is formed on the surface of the semi-conducting material of cavity 22.Insulating layer may be oxygen
Compound material can be formed by self aligned mode together with the oxide skin(coating).
In addition, the present invention also provides the manufacturing methods of above-mentioned semiconductor device, skill in order to better understand the present invention
Art scheme and technique effect are described in detail specific embodiment below with reference to flow chart 12.
In step S01, substrate 10 is provided, the substrate 10 has first area 100 and second area 200, with reference to 1 institute of figure
Show.
The substrate is semiconductor substrate in the present invention, preferably can be the body substrate with single semi-conducting material,
Such as can be Si substrates, Ge substrates, SiGe substrate, can also be the lining for including other elements semiconductor or compound semiconductor
Bottom, such as GaAs, InP or SiC etc., in the present embodiment, the substrate are body silicon substrate, and the substrate also has third region
300。
In step S02, the first semiconductor region 13-1,15 and thereon the second half are formed on the first area of substrate 100
Conductor region 16-1, and third semiconductor region 13-2 and the 4th semiconductor region thereon are formed on the second area 200 of substrate
16-2, with reference to shown in figure 7.
In the present embodiment, specifically include the following steps：
Step S201, the second semiconductor layer of epitaxial growth 13 on first area 100 and second area 200, such as Fig. 3 institutes
Show.
In the particular embodiment, first, the first mask 11, for example, hard mask of silica are deposited on substrate 10；
Then, photosensitive etching agent 12-1 is formed on the third area；Then, it performs etching, goes under the cover of photosensitive etching agent 12-1
Except the first mask 11 of first area and second area, the first mask 11 is only formed on third region 300, and remove photosensitive quarter
Agent 12-1 is lost, as shown in Figure 2.Then, epitaxial growth Ge is carried outxSi1-xThe second semiconductor layer 13, wherein 0<x<1, due to
The substrate 10 in three regions 300 is covered by the first mask 11, is only formed on the substrate 10 of first area 100 and second area 200
Second semiconductor layer 13.
Step S202, the epitaxial growth third semiconductor layer 15 on the second semiconductor layer 13 of first area 100, reference chart
Shown in 4.
In the particular embodiment, first, the second mask 14 is formed on the second semiconductor layer 13 of second area 200,
Formation of the specific method with the first mask；Then, epitaxial growth Ge is carried outxSi1-xThird semiconductor layer 15, due to third area
The substrate in domain 300 is covered by the first mask 11, and the substrate 10 of second area 200 is covered by the second mask 14, only in first area
Third semiconductor layer 15 is formd on 100 the second semiconductor layer 13, the thickness of the third semiconductor layer 15 can be more than second
The thickness of semiconductor layer 13, as shown in Figure 4；Then, first mask 11 and the second mask 14 are removed.
Step S203 carries out epitaxial growth, the shape on the second semiconductor layer of third semiconductor layer 15 and second area 200
At the 4th semiconductor layer 16, with reference to shown in figure 5.
In the particular embodiment, the 4th semiconductor layer 16 that epitaxial growth Si can be carried out, in third semiconductor layer 15
The 4th semiconductor layer 16 is all formd on the second semiconductor layer of second area 200 and on the substrate 10 in third region 300,
As shown in Figure 5.
Step S204, is patterned, with reference to shown in figure 7.
In the particular embodiment, first, as shown in fig. 6, carrying out the deposit of third mask 17, third mask for example can be with
It is silicon nitride for silicon nitride, silica, silicon oxynitride or their combination, in the present embodiment；Then, in first area 100,
Two regions 200, third region 300 third mask 17 on form photosensitive etching agent 12-2；Then, photosensitive etching agent 12-2's
Masking is lower to carry out the patterning of third mask 17, and removes the photosensitive etching agent 12-2, with reference to shown in figure 7；Then, it is covered in third
Under the masking of film 17, the patterning of active area is carried out, it includes the second semiconductor layer 13-1 and third half to be formed in first area 100
First semiconductor region of conductor layer 15, and include the second semiconductor region of the 4th semiconductor layer 16-1, in 200 shape of second area
At including the second semiconductor layer 13-2 third semiconductor region and include the 4th semiconductor region of the 4th semiconductor layer 16-2,
The 4th semiconductor layer 16-3 is formd on the substrate in three regions 300, the opening of the 4th semiconductor layer both sides is isolated groove 20,
So far, the active area of each region and the groove of isolated area are formd, can be as needed in the etching for forming active area,
Can further etched portions thickness substrate, as shown in Figure 7.
In the present embodiment, the second semiconductor layer and third semiconductor layer are formed by the way of selective epitaxial growth,
In this way, the device area of first area can be made consistent with traditional devices, the presence due to second and third semiconductor layer is avoided
The reduction of device mobility caused by the additional stress brought, improves the performance of device.
Certainly, only it is that preferred embodiment in other embodiments of the invention can also be traditional by other herein
Technique forms the second semiconductor layer and third semiconductor layer on the first region, for example, depositing second, third semiconductor layer
Later, etch away second on the third semiconductor layer and third region of second area and the method for third semiconductor layer carry out shape
At.
In step S03, the first opening 22 and second is formed in the end of the first semiconductor region and third semiconductor region respectively
Opening 24；The second opening 24 is filled up, to form insulating layer 26, with reference to shown in figure 7-8.
In the present embodiment, wet etching, the second semiconductor of selective removal 100 part of first area may be used
The second semiconductor layer 13-2 of layer 13-1 and 200 part of third semiconductor layer 15 and second area, specifically, solvent can be with
Using 49% HF, 30%H2O2, 99.8% CH3COOH and H2The mixed solution of O, ratio 1:18:27:8, pass through control
Time removes the second semiconductor layer and third semiconductor layer of both ends part, in the present embodiment, the first of first area 100
Semiconductor region includes the second semiconductor layer 13-1 and third semiconductor layer 15, and thickness only includes more than second area 200
The thickness of the third semiconductor region of second semiconductor layer 13-2, after etching, the height of the first opening 22 of formation are more than second
The height of opening 24 highly refers to along substrate to the in order to form the different structures of cavity and insulating layer in two regions
The direction of three semiconductor regions.
Then, by oxidation technology, such as dry oxidation, to form insulating layer 26, by controlling the time of oxidation, such as Fig. 9
It is shown so that the oxide material after the semi-conducting material on each surface is fully oxidized in the second opening 24 is full of second opening,
Insulating layer 26 in second opening 24 is the semi-conducting material oxide of substrate, the second semiconductor layer and the 4th semiconductor layer,
In oxidation technology, semiconductor oxide nitride layer 20 is also all formd on the surface of isolated groove 20, first is open on 26 surface
Also form the oxide skin(coating) 19 of semi-conducting material.
In the present embodiment, by the different thickness of the first semiconductor region and the second semiconductor region come control the first opening and
The different height of second opening, in oxidation technology so that the second opening is filled up by oxide material, and the first opening is only
Oxide skin(coating) is formed on the surface.This method is simple and practicable, and is easy to integrated with traditional device technology, is forming insulating layer
Simultaneously so that the defect that the first opening and insulation surfaces are formed in etching process is all repaired.In other embodiments, also
Opening and insulating layer can be formed by other methods, such as first cover first area and third region, carry out second
The etching and fill insulating layer using oxidation technology that the second of region is open, then in the first opening for carrying out first area
Etching and oxidation technology.
In step S04, the first device and the second device are formed on the second semiconductor region and the 4th semiconductor region respectively.
Before forming device, first, isolated groove 20 is filled, to form isolation structure 28, as shown in Figure 10.
Isolation structure 28 can be formed by traditional handicraft, first carry out the deposit of dielectric material, such as silica then carries out flat
Change, such as carries out chemical mechanical grinding (CMP), the method that thickness monitor or terminal triggering can be passed through so that CMP stops at the
At the target thickness of three masks 17, in the CMP step, in the third of the first, second, and third region still member-retaining portion thickness
Mask 17, so that active area is injury-free in a cmp process, as shown in Figure 10；It then, can will be remaining with selective etch
Third mask 17 removes, with reference to shown in figure 11.
Then, the first device 30, the second device 40 and third device are respectively formed in the first, second, and third region respectively
50.Device can be formed according to traditional technique.In the present embodiment, as shown in figure 11, in the first device area 100, trap is mixed
Miscellaneous 31 are formed in the 4th semiconductor layer 16-1, third semiconductor layer 15, the second semiconductor layer 13-1 and partial substrate 10,
Gate structure 32 is formd on 4th semiconductor layer 16-1 of the first device area；It is formed on the side wall of the gate structure 32
Side wall 33；Source-drain area 34 is formd in the 4th semiconductor layer 16-1 of 32 both sides of gate structure, which is located at sky
On chamber 22；Metal silicide layer 35 is also formed on source-drain area 34.
In the second device area 200, trap doping 41 is formed in the 4th semiconductor layer 16-2, the second semiconductor layer 13-2 and portion
In the substrate 10 divided, gate structure 42 is formd on the 4th semiconductor layer 16-2 of the second device area；The grid knot
Side wall 43 is formd on the side wall of structure 42；Source-drain area 44 is formd in the 4th semiconductor layer 16-2 of 42 both sides of gate structure,
The source-drain area 44 is located on insulating layer 26；Metal silicide layer 45 is also formed on source-drain area 44.
In third device area 300, trap doping 51 is formed in the 4th semiconductor layer 16-3 and partial substrate 10, the
Gate structure 52 is formd on 4th semiconductor layer 16-3 of three device areas；It is formd on the side wall of the gate structure 52
Side wall 53；Source-drain area 54 is formd in the 4th semiconductor layer 16-3 of 52 both sides of gate structure, shape is gone back on source-drain area 54
At there is metal silicide layer 55.It in other embodiments, can be without forming the 4th semiconductor layer, third device on third region
It is formed directly on substrate, doped region is formed in the substrate, identical as common body silicon device.
Later, the other component of device, such as source and drain contact, gate contact and interconnection structure can also be formed.
So far, the integrated of three kinds of devices of the embodiment of the present invention, in the present embodiment, the shape by the way of extension are completed
At each semiconductor layer, in this way, the device area of the first device and the second device can be made consistent with traditional devices, avoid fifty-fifty
The presence of conductor layer may bring additional stress, the problem of causing device mobility to reduce, meanwhile, it is cavity and insulation under source and drain
The device of layer is fully combined together with conventional bulk silicon device technique, meets the multifarious requirement of circuit performance, while not influencing
The electric property of traditional devices.It, can be by adjusting the second semiconductor layer and third semiconductor layer in addition, in a manufacturing process
Thickness can be realized the adjusting of the thickness of insulating layer and the height of cavity, simple for process and be easily integrated.
The above described is only a preferred embodiment of the present invention, being not intended to limit the present invention in any form.
Although the present invention has been disclosed in the preferred embodiments as above, however, it is not intended to limit the invention.It is any to be familiar with ability
The technical staff in domain, without departing from the scope of the technical proposal of the invention, all using in the methods and techniques of the disclosure above
Appearance makes many possible changes and modifications to technical solution of the present invention, or is revised as the equivalent embodiment of equivalent variations.Therefore,
Every content without departing from technical solution of the present invention is made to the above embodiment any simple according to the technical essence of the invention
Modification, equivalent variations and modification, in the range of still falling within technical solution of the present invention protection.
Claims (8)
1. a kind of semiconductor devices, which is characterized in that including the first device area and the second device area, wherein
First device area includes：
Substrate；
First active area stacks, including the first semiconductor region on substrate and the second semiconductor region thereon and cavity, cavity
Between the end of the first semiconductor region, the second semiconductor region and substrate；
First device is located on the second semiconductor region, and its source-drain area is located on cavity；
Second device area includes：
Substrate；
Second active area stacks, including third semiconductor region on substrate and the 4th semiconductor region thereon and insulating layer, absolutely
Edge layer is located between end, the 4th semiconductor region and the substrate of third semiconductor region；
Second device is located on the 4th semiconductor region, and its source-drain area is located on insulating layer；
First semiconductor region includes the third semiconductor layer on the second semiconductor layer and the second semiconductor layer on substrate, and the second half
Conductor region is the 4th semiconductor layer；Third semiconductor region is the second semiconductor layer, and the 4th semiconductor region is the 4th semiconductor layer.
2. semiconductor devices according to claim 1, which is characterized in that further include third device area, the third device
Part region includes：
Substrate；
Third device is located at substrate.
3. semiconductor devices according to claim 1, which is characterized in that the substrate is body silicon substrate, the second semiconductor
Layer and third semiconductor layer are GexSi1-x, 0<x<1, the 4th semiconductor layer is silicon.
4. semiconductor devices according to claim 1, which is characterized in that the first device area further includes oxide skin(coating), shape
At on the surface of the semi-conducting material of cavity.
5. a kind of manufacturing method of semiconductor devices, which is characterized in that including step：
S01, provides substrate, and the substrate has first area and second area；
S02 forms the first semiconductor region and the second semiconductor region thereon on the first area of substrate, and the of substrate
Third semiconductor region and the 4th semiconductor region thereon are formed on two regions；
S03 forms the first opening and the second opening in the end of the first semiconductor region and third semiconductor region respectively；Fill up second
Opening, to form insulating layer；
S04 forms the first device and the second device on the second semiconductor region and the 4th semiconductor region respectively；
Step S02 is specifically included：
The second semiconductor layer of epitaxial growth on first area and second area；
The epitaxial growth third semiconductor layer on the second semiconductor layer of first area；
Epitaxial growth is carried out, forms the 4th semiconductor layer on the second semiconductor layer of third semiconductor layer and second area；
Perform etching, first area formed it is patterned include the second semiconductor layer and third semiconductor layer the first semiconductor
Area and the second semiconductor region for including the 4th semiconductor layer, it includes the of the second semiconductor layer to be formed patterned in second area
The opening of three semiconductor regions and the 4th semiconductor region for including the 4th semiconductor layer, the 4th semiconductor layer both sides is isolated groove.
6. manufacturing method according to claim 5, which is characterized in that the substrate also has third region；
In step S04, further include：Third device is formed on the substrate in third region.
7. manufacturing method according to claim 5, which is characterized in that the substrate also has third region；The progress
The step of epitaxial growth further includes：The 4th semiconductor layer is formed on the substrate in third region；
Described the step of performing etching further includes：Patterned 4th semiconductor layer is formed on the third area；
Further include in step S04：Third device is formed on the 4th semiconductor layer in third region.
8. manufacturing method according to claim 5, which is characterized in that the step of filling up the second opening specifically includes：It carries out
Oxidation technology, so that the oxide skin(coating) of the semi-conducting material of the second open surfaces is full of in the second opening, the table of the first opening
The oxide skin(coating) of the semi-conducting material of the first open surfaces is formed on face.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410339866.5A CN105304629B (en) | 2014-07-16 | 2014-07-16 | Semiconductor devices and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410339866.5A CN105304629B (en) | 2014-07-16 | 2014-07-16 | Semiconductor devices and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105304629A CN105304629A (en) | 2016-02-03 |
| CN105304629B true CN105304629B (en) | 2018-07-13 |
Family
ID=55201674
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410339866.5A Active CN105304629B (en) | 2014-07-16 | 2014-07-16 | Semiconductor devices and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105304629B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6448115B1 (en) * | 1999-10-12 | 2002-09-10 | Samsung Electronics Co., Ltd. | Semiconductor device having quasi-SOI structure and manufacturing method thereof |
| CN1542965A (en) * | 2003-05-02 | 2004-11-03 | 三星电子株式会社 | Integrated circuit devices having an epitaxial pattern with a void region formed therein and methods of forming the same |
| CN101924138A (en) * | 2010-06-25 | 2010-12-22 | 中国科学院上海微系统与信息技术研究所 | MOS (Metal Oxide Semiconductor) device structure for preventing floating-body effect and self-heating effect and preparation method thereof |
-
2014
- 2014-07-16 CN CN201410339866.5A patent/CN105304629B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6448115B1 (en) * | 1999-10-12 | 2002-09-10 | Samsung Electronics Co., Ltd. | Semiconductor device having quasi-SOI structure and manufacturing method thereof |
| CN1542965A (en) * | 2003-05-02 | 2004-11-03 | 三星电子株式会社 | Integrated circuit devices having an epitaxial pattern with a void region formed therein and methods of forming the same |
| CN101924138A (en) * | 2010-06-25 | 2010-12-22 | 中国科学院上海微系统与信息技术研究所 | MOS (Metal Oxide Semiconductor) device structure for preventing floating-body effect and self-heating effect and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105304629A (en) | 2016-02-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104124273B (en) | There is MOS device of strained buffer layer and forming method thereof | |
| KR101622007B1 (en) | Semiconductor strips with undercuts and methods for forming the same | |
| JP6153480B2 (en) | Passivated III-V or Ge fin-shaped field effect transistor | |
| US8835278B2 (en) | Method for forming a buried dielectric layer underneath a semiconductor fin | |
| US9305823B2 (en) | Semiconductor device including STI structure and fabrication method | |
| JP2010157723A (en) | Integrated circuit structure and method of manufacturing the same | |
| JP2005045258A (en) | MANUFACTURE OF SILICON-ON-NOTHING (SON) MOSFET USING SELECTIVE ETCHING OF Si1-xGex LAYER | |
| CN105097533B (en) | The forming method of semiconductor structure | |
| JP6629159B2 (en) | Method for manufacturing semiconductor device | |
| US20160293695A1 (en) | Semiconductor device and method for manufacturing the same | |
| CN105576027A (en) | Semiconductor substrate, semiconductor device and manufacture methods thereof | |
| CN102148183A (en) | Method for forming SOI (Silicon On Insulator) with stepped buried oxide layer | |
| CN105261587A (en) | Semiconductor device and manufacturing method thereof | |
| CN105304629B (en) | Semiconductor devices and its manufacturing method | |
| CN105280697A (en) | Semiconductor device and manufacturing method thereof | |
| CN105304628B (en) | Semiconductor devices and its manufacturing method | |
| US9306003B2 (en) | Semiconductor device and method for manufacturing the same | |
| CN105322012B (en) | Semiconductor devices and its manufacturing method | |
| KR19980083840A (en) | Device isolation by selective epitaxial growth | |
| CN105322010B (en) | The manufacturing method of semiconductor devices | |
| CN103794512B (en) | Double-Finfet transistor and preparation method thereof | |
| KR20090073032A (en) | Method for manufacturing semiconductor device | |
| JP2009177063A (en) | Method for manufacturing semiconductor device and semiconductor device | |
| CN105575877A (en) | Semiconductor substrate, semiconductor device and manufacture methods thereof | |
| CN105489546B (en) | A kind of semiconductor devices and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |