CN105304629A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN105304629A CN105304629A CN201410339866.5A CN201410339866A CN105304629A CN 105304629 A CN105304629 A CN 105304629A CN 201410339866 A CN201410339866 A CN 201410339866A CN 105304629 A CN105304629 A CN 105304629A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 264
- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 97
- 230000004888 barrier function Effects 0.000 claims description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 239000011248 coating agent Substances 0.000 claims description 12
- 238000000576 coating method Methods 0.000 claims description 12
- 238000005516 engineering process Methods 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 9
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- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 230000008569 process Effects 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 230000000694 effects Effects 0.000 description 10
- 239000003795 chemical substances by application Substances 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
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- 239000002184 metal Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000006185 dispersion Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
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Abstract
The invention provides a semiconductor device, which comprises a first device region: a substrate; a first active region stack including a first semiconductor region on the substrate and a second semiconductor region thereon, and a cavity between an end of the first semiconductor region, the second semiconductor region, and the substrate; the first device is positioned above the second semiconductor region, and the source-drain region of the first device is positioned above the cavity; a second device region: a substrate; a second active region stack including a third semiconductor region on the substrate and a fourth semiconductor region thereon, and an insulating layer between an end of the third semiconductor region, the fourth semiconductor region, and the substrate; and the second device is positioned on the fourth semiconductor region, and the source and drain regions of the second device are positioned on the insulating layer. The semiconductor device has the characteristics of low cost, small electric leakage, low power consumption, high speed, simpler process and high integration level.
Description
Technical field
The present invention relates to field of semiconductor devices, particularly a kind of semiconductor device and manufacture method thereof.
Background technology
Along with constantly reducing of device size, device count on unit are chip gets more and more, this can cause the increase of dynamic power consumption, simultaneously, device size constantly reduce the increase that must cause leakage current, and then cause the increase of quiescent dissipation, and along with the height of semiconductor device integrated, MOSFET channel length constantly shortens, a series of in MOSFET long raceway groove model negligible effect become more remarkable, even become the leading factor affecting device performance, this phenomenon is referred to as short-channel effect.The electric property of short-channel effect meeting deterioration of device, as caused, threshold voltage of the grid declines, power consumption increases and degradation problem under signal to noise ratio.
SOI substrate embedded in silicon dioxide layer in the below of silicon, and relative to body silicon device, the device that SOI substrate is formed can obviously reduce leakage current and power consumption, improves short-channel effect, has obvious performance advantage.But the cost of SOI substrate is higher, and need larger device area to avoid floater effect (FloatingBodyEffect), be difficult to meet the integrated requirement of element height, in addition, owing to embedded in silicon dioxide layer, the heat dispersion of its device is affected.
Summary of the invention
Object of the present invention is intended at least solve one of above-mentioned technological deficiency, provides a kind of semiconductor device and manufacture method thereof.
The invention provides a kind of semiconductor device, comprise the first device area and the second device area, wherein,
First device area comprises:
Substrate;
First active area is stacking, comprises the first semiconductor region on substrate and the second semiconductor region on it, and cavity, and cavity is in the end of the first semiconductor region, between the second semiconductor region and substrate;
First device, is positioned on the second semiconductor region, and its source-drain area is positioned on cavity;
Second device area comprises:
Substrate;
Second active area is stacking, comprises the 3rd semiconductor region on substrate and the 4th semiconductor region on it, and insulating barrier, and insulating barrier is in the end, the 4th of the 3rd semiconductor region between semiconductor region and substrate;
Second device, be positioned on the 4th semiconductor region, and its source-drain area is positioned on insulating barrier.
Optionally, also comprise the 3rd device area, described 3rd device area comprises:
Substrate;
3rd device, is positioned at substrate.
Optionally, the first semiconductor region comprises the second semiconductor layer on substrate and the 3rd semiconductor layer on the second semiconductor layer, and the second semiconductor region is the 4th semiconductor layer; 3rd semiconductor region is the second semiconductor layer, and the 4th semiconductor region is the 4th semiconductor layer.
Optionally, described substrate is body silicon substrate, and the second semiconductor layer and the 3rd semiconductor layer are Ge
xsi
1-x, 0<x<1, the 4th semiconductor layer is silicon.
Optionally, the first device area also comprises oxide skin(coating), is formed on the surface of the semi-conducting material of cavity.
In addition, the present invention also provides a kind of manufacture method of semiconductor device, comprises step:
S01, provides substrate, and described substrate has first area and second area;
S02, the first area of substrate is formed the first semiconductor region and the second semiconductor region on it, and on the second area of substrate, form the 3rd semiconductor region and the 4th semiconductor region on it;
S03, forms the first opening and the second opening in the end of the first semiconductor region and the 3rd semiconductor region respectively; Fill up the second opening, to form insulating barrier;
S04, forms the first device and the second device respectively on the second semiconductor region and the 4th semiconductor region.
Optionally, described substrate also has the 3rd region;
In step S04, also comprise: on the substrate in the 3rd region, form the 3rd device.
Optionally, step S02 specifically comprises:
At first area and second area Epitaxial growth second semiconductor layer;
At the second semiconductor layer Epitaxial growth the 3rd semiconductor layer of first area;
Carry out epitaxial growth, the second semiconductor layer of the 3rd semiconductor layer and second area forms the 4th semiconductor layer;
Etch, form first semiconductor region comprising the second semiconductor layer and the 3rd semiconductor layer of patterning in first area and comprise the second semiconductor region of the 4th semiconductor layer, form comprising the 3rd semiconductor region of the second semiconductor layer and comprising the 4th semiconductor region of the 4th semiconductor layer of patterning at second area, the opening of the 4th semiconductor layer both sides is isolated groove.
Optionally, described substrate also has the 3rd region; Describedly carry out epitaxially grown step and also comprise: on the substrate in the 3rd region, form the 4th semiconductor layer;
Described step of carrying out etching also comprises: the 4th semiconductor layer forming patterning on the third area;
Also comprise in step S04: on the 4th semiconductor layer in the 3rd region, form the 3rd device.
Optionally, the step of filling up the second opening specifically comprises: carry out oxidation technology, to make the oxide skin(coating) of the semi-conducting material being full of the second open surfaces in the second opening, and the oxide skin(coating) of the semi-conducting material of formation first open surfaces on the surface of the first opening.
The semiconductor device that the embodiment of the present invention provides and manufacture method thereof, be integrated with two kinds of devices, be formed with cavity under a kind of end of active area of device, be formed with insulating barrier, and under channel region be semiconductor region under the end of the active area of another kind of device.Such device architecture, has the respective advantage of body silicon device and SOI device simultaneously, has low cost, little, low in energy consumption, the speed of leaking electricity is fast, the comparatively simple and feature that integrated level is high of technique.Meanwhile, compared with SOI device, eliminate floater effect and self-heating effect.In addition, the device with cavity has lower dielectric constant, makes it can bear higher voltage.And be easy to integrated with the device of other structures, meet the needs of different circuit performance.
Accompanying drawing explanation
The present invention above-mentioned and/or additional aspect and advantage will become obvious and easy understand from the following description of the accompanying drawings of embodiments, wherein:
Fig. 1-Figure 11 shows the schematic diagram of each formation stages of the semiconductor device according to the embodiment of the present invention;
Figure 12 shows the flow chart of the manufacture method of the semiconductor device according to the embodiment of the present invention.
Embodiment
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not limitation of the present invention being interpreted as.
The present invention is intended to propose a kind of semiconductor device, and with reference to shown in Figure 10,11, this semiconductor device comprises:
First device area 100:
Substrate 10;
First active area is stacking, comprises the first semiconductor region 13-1 on substrate, 15 and the second semiconductor region 16-1 on it, and cavity 22, cavity 22 the first semiconductor region 13-1,15 end, between the second semiconductor region 1-16 and substrate 10;
First device 30, is positioned on the second semiconductor region 16-1, and its source-drain area 34 is positioned on cavity 22;
Second device area 200:
Substrate 10;
Second active area is stacking, comprises the 3rd semiconductor region 13-2 on substrate and the 4th semiconductor region 16-2 on it, and insulating barrier 26, and insulating barrier 26 is in the end of the 3rd semiconductor region 13-2, between the 4th semiconductor region 16-2 and substrate 10;
Second device 40, is positioned on the 4th semiconductor region 16-2, and its source-drain area 44 is positioned on insulating barrier 26.
In the present invention, be integrated with two kinds of devices, under a kind of end of active area of device, be formed with cavity, be formed with insulating barrier under the end of the active area of another kind of device, and under channel region, be semiconductor region.Like this, due to the existence of insulating barrier or cavity, substantially reduce leakage current and the power consumption of device, add the integrated level of device.Compared with SOI device, be connected with substrate below channel region, there is better heat dispersion and avoid the generation of floater effect.Meanwhile, because device can adopt body silicon substrate, the restriction of SOI wafer high cost is avoided.These two kinds of devices are easy to integrated, meet the demand of different circuit.
In addition, device of the present invention is applicable to the environment of intense radiation, as strategic arms etc., owing to there is no the insulating barrier of silica under raceway groove, reduce radiation sensitive region area, and can be regulated by backgate, the electron hole pair that release portion irradiation causes, avoids the floater effect that irradiation causes.
Device architecture of the present invention, is easy to integrated with the device of other structures, with the needs of satisfied different circuit performance, as shown in figure 11, is also integrated with the 3rd device area the 300, three device area and comprises:
Substrate 10;
3rd device 50, is positioned on substrate 10.
In the present invention, 3rd device is formed on substrate, the i.e. part-structure of its device, as doped region can only be formed in the substrate, also can be formed in other semiconductor layers on substrate, in an embodiment of the present invention, as Figure 10, shown in 11, 3rd device 50 is formed on the semiconductor layer 16 on substrate, the doped region of the 3rd device can be formed in the semiconductor layer on substrate, also can be formed in the semiconductor layer on substrate and substrate, particularly, this semiconductor layer can for the semiconductor layer together formed with the semiconductor region of first area and second area.
In the present invention, can need in a manufacturing process according to device and the demand of device performance, select the material of substrate, the first semiconductor region, the second semiconductor region, the 3rd semiconductor region and the 4th semiconductor region, identical or different semi-conducting material can be adopted.In the particular embodiment, the first semiconductor region comprises the second semiconductor layer on substrate and the 3rd semiconductor layer on the second semiconductor layer, and the second semiconductor region is the 4th semiconductor layer; 3rd semiconductor region is the second semiconductor layer, and the 4th semiconductor region is the 4th semiconductor layer, and the 3rd device is formed on the 4th semiconductor layer.In a preferred embodiment of the invention, described substrate is body silicon substrate, and the second semiconductor layer and the 3rd semiconductor layer are Ge
xsi
1-x, 0<x<1, the 4th semiconductor layer is silicon, and the semiconductor region being formed crystal by epitaxial growth is convenient in the selection of this semi-conducting material, and device has more excellent performance.
In embodiments of the present invention, the first device area also comprises oxide skin(coating) 19, and this oxide skin(coating) 19 can be ultra-thin oxide skin(coating), and thickness exists
be formed on the surface of the semi-conducting material of cavity 22.Insulating barrier also can be oxide material, can together be formed by self aligned mode with this oxide skin(coating).
In addition, present invention also offers the manufacture method of above-mentioned semiconductor device, technical scheme for a better understanding of the present invention and technique effect, be described in detail specific embodiment below with reference to flow process Figure 12.
In step S01, provide substrate 10, described substrate 10 has first area 100 and second area 200, shown in figure 1.
Described substrate is Semiconductor substrate in the present invention, preferably can for having the body substrate of single semi-conducting material, can be such as Si substrate, Ge substrate, SiGe substrate, it can also be the substrate comprising other elemental semiconductors or compound semiconductor, such as GaAs, InP or SiC etc., in the present embodiment, described substrate is body silicon substrate, and described substrate also has the 3rd region 300.
In step S02, the first area 100 of substrate is formed the first semiconductor region 13-1,15 and the second semiconductor region 16-1 on it, and on the second area 200 of substrate, form the 3rd semiconductor region 13-2 and the 4th semiconductor region 16-2 on it, shown in figure 7.
In the present embodiment, specifically to comprise the following steps:
Step S201, at first area 100 and second area 200 Epitaxial growth second semiconductor layer 13, as shown in Figure 3.
In the particular embodiment, first, deposit first mask 11 is over the substrate 10 such as the hard mask of silica; Then, photosensitive etching agent 12-1 is formed on the third area; Then, etch under the covering of photosensitive etching agent 12-1, remove the first mask 11 of first area and second area, only on the 3rd region 300, form the first mask 11, and remove photosensitive etching agent 12-1, as shown in Figure 2.Then, epitaxial growth Ge is carried out
xsi
1-xthe second semiconductor layer 13, wherein, 0<x<1, because the substrate 10 in the 3rd region 300 is covered by the first mask 11, only defines the second semiconductor layer 13 on the substrate 10 of first area 100 and second area 200.
Step S202, at the second semiconductor layer 13 Epitaxial growth the 3rd semiconductor layer 15 of first area 100, shown in figure 4.
In the particular embodiment, first, the second semiconductor layer 13 of second area 200 forms the second mask 14, concrete grammar is with the formation of the first mask; Then, epitaxial growth Ge is carried out
xsi
1-xthe 3rd semiconductor layer 15, because the substrate in the 3rd region 300 is covered by the first mask 11, the substrate 10 of second area 200 is covered by the second mask 14, only on the second semiconductor layer 13 of first area 100, define the 3rd semiconductor layer 15, the thickness of the 3rd semiconductor layer 15 can be greater than the thickness of the second semiconductor layer 13, as shown in Figure 4; Then, this first mask 11 and the second mask 14 is removed.
Step S203, carries out epitaxial growth, the second semiconductor layer of the 3rd semiconductor layer 15 and second area 200 forms the 4th semiconductor layer 16, shown in figure 5.
In the particular embodiment, the 4th semiconductor layer 16 of epitaxial growth Si can be carried out, on the second semiconductor layer of the 3rd semiconductor layer 15 and second area 200 and on the substrate 10 in the 3rd region 300, all define the 4th semiconductor layer 16, as shown in Figure 5.
Step S204, carries out patterning, shown in figure 7.
In the particular embodiment, first, as shown in Figure 6, carry out the deposit of the 3rd mask 17, the 3rd mask can be such as silicon nitride, silica, silicon oxynitride or their combination, is silicon nitride in the present embodiment, then, the 3rd mask 17 in first area 100, second area 200, the 3rd region 300 forms photosensitive etching agent 12-2, then, under the sheltering of photosensitive etching agent 12-2, carry out the patterning of the 3rd mask 17, and remove this photosensitive etching agent 12-2, shown in figure 7, then, under the sheltering of the 3rd mask 17, carry out the patterning of active area, the first semiconductor region comprising the second semiconductor layer 13-1 and the 3rd semiconductor layer 15 is formed in first area 100, and comprise second semiconductor region of the 4th semiconductor layer 16-1, formed at second area 200 and comprise the 3rd semiconductor region of the second semiconductor layer 13-2 and comprise the 4th semiconductor region of the 4th semiconductor layer 16-2, the substrate in the 3rd region 300 defines the 4th semiconductor layer 16-3, the opening of the 4th semiconductor layer both sides is isolated groove 20, so far, define the active area of regional and the groove of isolated area, in the etching being formed with source region, can be as required, can the substrate of etched portions thickness further, as shown in Figure 7.
In the present embodiment, the mode of selective epitaxial growth is adopted to form the second semiconductor layer and the 3rd semiconductor layer, like this, the device area of first area can be made consistent with traditional devices, avoid, due to second and the 3rd additional stress brought of the existence of semiconductor layer and the reduction of device mobility that causes, improving the performance of device.
Certainly, it is only preferred embodiment herein, in other embodiments of the invention, other traditional techniques can also be passed through, form the second semiconductor layer and the 3rd semiconductor layer on the first region, such as, after second, third semiconductor layer of deposit, the method etching away second on the 3rd semiconductor layer of second area and the 3rd region and the 3rd semiconductor layer is formed.
In step S03, form the first opening 22 and the second opening 24 in the end of the first semiconductor region and the 3rd semiconductor region respectively; Fill up the second opening 24, to form insulating barrier 26, shown in figure 7-8.
In the present embodiment, can wet etching be adopted, optionally remove the second semiconductor layer 13-1 and the 3rd semiconductor layer 15 of first area 100 part, and the second semiconductor layer 13-2 of second area 200 part, concrete, solvent can adopt HF, 30%H of 49%
2o
2, 99.8% CH
3cOOH and H
2the mixed solution of O, ratio is 1:18:27:8, pass through the control time, remove the second semiconductor layer and the 3rd semiconductor layer of two end portions, in the present embodiment, first semiconductor region of first area 100 includes the second semiconductor layer 13-1 and the 3rd semiconductor layer 15, its thickness is greater than the thickness only comprising the 3rd semiconductor region of the second semiconductor layer 13-2 of second area 200, after etching, the height of the first opening 22 formed is greater than the height of the second opening 24, so that form the different structure of cavity and insulating barrier in two regions, highly refer to the direction along substrate to the 3rd semiconductor region.
Then, pass through oxidation technology, as dry oxidation, form insulating barrier 26, by the time of controlled oxidization, as shown in Figure 9, oxide material after making the semi-conducting material on each surface in the second opening 24 fully oxidized is full of this second opening, insulating barrier 26 in second opening 24 is the semi-conducting material oxide of substrate, the second semiconductor layer and the 4th semiconductor layer, in oxidation technology, the surface that the surface of isolated groove 20 also all defines semiconductor oxide nitride layer 20, first opening 26 also form the oxide skin(coating) 19 of semi-conducting material.
In the present embodiment, the first opening height different with the second opening is controlled by the thickness that the first semiconductor region is different with the second semiconductor region, thus in oxidation technology, the second opening oxide material is filled up, and the first opening only forms oxide skin(coating) from the teeth outwards.The method is simple, and is easy to integrated with traditional device technology, and while formation insulating barrier, the defect that the first opening and insulation surfaces are formed in etching process is all repaired.In other embodiments, opening and insulating barrier can also be formed by other method, such as first first area and the 3rd region are covered, carry out the etching of the second opening of second area and utilize oxidation technology to fill insulating barrier, then carrying out the etching of the first opening and the oxidation technology of first area.
In step S04, on the second semiconductor region and the 4th semiconductor region, form the first device and the second device respectively.
Before formation device, first, isolated groove 20 is filled, to form isolation structure 28, as shown in Figure 10.Isolation structure 28 can be formed by traditional handicraft, first carry out the deposit of dielectric material, as silica, then carry out planarization, such as, carry out cmp (CMP), the method that can be triggered by thickness monitor or terminal, CMP is made to stop at the target thickness place of the 3rd mask 17, in this CMP step, the 3rd mask 17 of still reserve part thickness in first, second, and third region, to make active area injury-free in a cmp process, as shown in Figure 10; Then, can selective etch be removed by remaining 3rd mask 17, with reference to shown in Figure 11.
Then, the first device 30, second device 40 and the 3rd device 50 is formed respectively in first, second, and third region respectively.Technique traditionally can form device.In the present embodiment, as shown in figure 11, at the first device area 100, trap doping 31 is formed in the substrate 10 of the 4th semiconductor layer 16-1, the 3rd semiconductor layer 15, second semiconductor layer 13-1 and part, on the 4th semiconductor layer 16-1 of the first device area, define grid structure 32; The sidewall of described grid structure 32 defines side wall 33; In the 4th semiconductor layer 16-1 of grid structure 32 both sides, define source-drain area 34, this source-drain area 34 is positioned on cavity 22; Metal silicide layer 35 is also formed on source-drain area 34.
At the second device area 200, trap doping 41 is formed in the substrate 10 of the 4th semiconductor layer 16-2, the second semiconductor layer 13-2 and part, on the 4th semiconductor layer 16-2 of the second device area, define grid structure 42; The sidewall of described grid structure 42 defines side wall 43; In the 4th semiconductor layer 16-2 of grid structure 42 both sides, define source-drain area 44, this source-drain area 44 is positioned on insulating barrier 26; Metal silicide layer 45 is also formed on source-drain area 44.
At the 3rd device area 300, trap doping 51 is formed in the substrate 10 of the 4th semiconductor layer 16-3 and part, on the 4th semiconductor layer 16-3 of the 3rd device area, define grid structure 52; The sidewall of described grid structure 52 defines side wall 53; In the 4th semiconductor layer 16-3 of grid structure 52 both sides, define source-drain area 54, on source-drain area 54, be also formed with metal silicide layer 55.In other embodiments, the 3rd region can not have formation the 4th semiconductor layer, the 3rd device is formed directly on substrate, and doped region is formed in the substrate, identical with common body silicon device.
Afterwards, the miscellaneous part of device can also be formed, as source and drain contact, gate contact and interconnection structure etc.
So far, complete the integrated of three kinds of devices of the embodiment of the present invention, in the present embodiment, the mode of extension is adopted to form each semiconductor layer, like this, the first device can be made consistent with traditional devices with the device area of the second device, the existence avoiding each semiconductor layer may bring additional stress, cause the problem that device mobility reduces, simultaneously, for the device of cavity and insulating barrier and conventional bulk silicon device technique fully combine under source and drain, meet the multifarious requirement of circuit performance, while do not affect the electric property of traditional devices.In addition, in a manufacturing process, can be realized the adjustment of the thickness of insulating barrier and the height of cavity by the thickness of adjustment second semiconductor layer and the 3rd semiconductor layer, technique is simple and be easy to integrated.
The above is only preferred embodiment of the present invention, not does any pro forma restriction to the present invention.
Although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention.Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (10)
1. a semiconductor device, is characterized in that, comprises the first device area and the second device area, wherein,
First device area comprises:
Substrate;
First active area is stacking, comprises the first semiconductor region on substrate and the second semiconductor region on it, and cavity, and cavity is in the end of the first semiconductor region, between the second semiconductor region and substrate;
First device, is positioned on the second semiconductor region, and its source-drain area is positioned on cavity;
Second device area comprises:
Substrate;
Second active area is stacking, comprises the 3rd semiconductor region on substrate and the 4th semiconductor region on it, and insulating barrier, and insulating barrier is in the end, the 4th of the 3rd semiconductor region between semiconductor region and substrate;
Second device, be positioned on the 4th semiconductor region, and its source-drain area is positioned on insulating barrier.
2. semiconductor device according to claim 1, is characterized in that, also comprises the 3rd device area, and described 3rd device area comprises:
Substrate;
3rd device, is positioned at substrate.
3. semiconductor device according to claim 1, is characterized in that, the first semiconductor region comprises the second semiconductor layer on substrate and the 3rd semiconductor layer on the second semiconductor layer, and the second semiconductor region is the 4th semiconductor layer; 3rd semiconductor region is the second semiconductor layer, and the 4th semiconductor region is the 4th semiconductor layer.
4. semiconductor device according to claim 3, is characterized in that, described substrate is body silicon substrate, and the second semiconductor layer and the 3rd semiconductor layer are Ge
xsi
1-x, 0<x<1, the 4th semiconductor layer is silicon.
5. semiconductor device according to claim 1, is characterized in that, the first device area also comprises oxide skin(coating), is formed on the surface of the semi-conducting material of cavity.
6. a manufacture method for semiconductor device, is characterized in that, comprises step:
S01, provides substrate, and described substrate has first area and second area;
S02, the first area of substrate is formed the first semiconductor region and the second semiconductor region on it, and on the second area of substrate, form the 3rd semiconductor region and the 4th semiconductor region on it;
S03, forms the first opening and the second opening in the end of the first semiconductor region and the 3rd semiconductor region respectively; Fill up the second opening, to form insulating barrier;
S04, forms the first device and the second device respectively on the second semiconductor region and the 4th semiconductor region.
7. manufacture method according to claim 6, is characterized in that, described substrate also has the 3rd region;
In step S04, also comprise: on the substrate in the 3rd region, form the 3rd device.
8. manufacture method according to claim 6, is characterized in that, step S02 specifically comprises:
At first area and second area Epitaxial growth second semiconductor layer;
At the second semiconductor layer Epitaxial growth the 3rd semiconductor layer of first area;
Carry out epitaxial growth, the second semiconductor layer of the 3rd semiconductor layer and second area forms the 4th semiconductor layer;
Etch, form first semiconductor region comprising the second semiconductor layer and the 3rd semiconductor layer of patterning in first area and comprise the second semiconductor region of the 4th semiconductor layer, form comprising the 3rd semiconductor region of the second semiconductor layer and comprising the 4th semiconductor region of the 4th semiconductor layer of patterning at second area, the opening of the 4th semiconductor layer both sides is isolated groove.
9. manufacture method according to claim 8, is characterized in that, described substrate also has the 3rd region; Describedly carry out epitaxially grown step and also comprise: on the substrate in the 3rd region, form the 4th semiconductor layer;
Described step of carrying out etching also comprises: the 4th semiconductor layer forming patterning on the third area;
Also comprise in step S04: on the 4th semiconductor layer in the 3rd region, form the 3rd device.
10. manufacture method according to claim 1, it is characterized in that, the step of filling up the second opening specifically comprises: carry out oxidation technology, to make the oxide skin(coating) of the semi-conducting material being full of the second open surfaces in the second opening, the oxide skin(coating) of the semi-conducting material of formation first open surfaces on the surface of the first opening.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410339866.5A CN105304629B (en) | 2014-07-16 | 2014-07-16 | Semiconductor device and method for manufacturing the same |
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|---|---|---|---|
| CN201410339866.5A CN105304629B (en) | 2014-07-16 | 2014-07-16 | Semiconductor device and method for manufacturing the same |
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| Publication Number | Publication Date |
|---|---|
| CN105304629A true CN105304629A (en) | 2016-02-03 |
| CN105304629B CN105304629B (en) | 2018-07-13 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6448115B1 (en) * | 1999-10-12 | 2002-09-10 | Samsung Electronics Co., Ltd. | Semiconductor device having quasi-SOI structure and manufacturing method thereof |
| CN1542965A (en) * | 2003-05-02 | 2004-11-03 | 三星电子株式会社 | Integrated circuit devices having an epitaxial pattern with a void region formed therein and methods of forming the same |
| CN101924138A (en) * | 2010-06-25 | 2010-12-22 | 中国科学院上海微系统与信息技术研究所 | MOS (Metal Oxide Semiconductor) device structure for preventing floating-body effect and self-heating effect and preparation method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6448115B1 (en) * | 1999-10-12 | 2002-09-10 | Samsung Electronics Co., Ltd. | Semiconductor device having quasi-SOI structure and manufacturing method thereof |
| CN1542965A (en) * | 2003-05-02 | 2004-11-03 | 三星电子株式会社 | Integrated circuit devices having an epitaxial pattern with a void region formed therein and methods of forming the same |
| CN101924138A (en) * | 2010-06-25 | 2010-12-22 | 中国科学院上海微系统与信息技术研究所 | MOS (Metal Oxide Semiconductor) device structure for preventing floating-body effect and self-heating effect and preparation method thereof |
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