CN106558492B - A kind of manufacturing method of fin and semiconductor devices - Google Patents
A kind of manufacturing method of fin and semiconductor devices Download PDFInfo
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- CN106558492B CN106558492B CN201510624492.6A CN201510624492A CN106558492B CN 106558492 B CN106558492 B CN 106558492B CN 201510624492 A CN201510624492 A CN 201510624492A CN 106558492 B CN106558492 B CN 106558492B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000000463 material Substances 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 238000005516 engineering process Methods 0.000 claims abstract description 32
- 230000003647 oxidation Effects 0.000 claims abstract description 30
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 29
- 238000005530 etching Methods 0.000 claims description 8
- 230000000873 masking effect Effects 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 101
- 230000015572 biosynthetic process Effects 0.000 description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 8
- 239000001301 oxygen Substances 0.000 description 8
- 239000011435 rock Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 230000005669 field effect Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
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- 238000002955 isolation Methods 0.000 description 1
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- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The present invention provides a kind of manufacturing method of fin, comprising: provides substrate；Initial graph pattern layer is formed on the substrate, which is semiconductor material, and carries out oxidation technology, and to form initial oxide layer on the side wall of initial graph pattern layer, the initial graph pattern layer for being formed with initial oxide layer is first structure；Form the (n+1)th structure, comprising: the n-th side wall is formed on the side wall of the n-th structure, the n-th side wall is semiconductor material, and oxidation technology is carried out, the n-th oxide layer is formed on the side wall of the n-th side wall, the n-th side wall for being formed with the n-th oxide layer is the (n+1)th structure, n from 1 to N, N >=1 and be positive integer；Remove initial graph pattern layer and initial oxide layer and the first oxide layer to the n-th oxide layer；The pattern of first side wall to the n-th side wall is transferred in substrate, to form fin.This method forms the exposure mask of highdensity fin, and then improves the integrated level of fin, meanwhile, the fin of acquisition has better pattern.
Description
Technical field
The present invention relates to semiconductor devices and manufacturing field, in particular to the manufacturing method of a kind of fin and semiconductor devices.
Background technique
Highly integrated with semiconductor devices, MOSFET channel length constantly shortens, a series of in MOSFET long channel
Negligible effect becomes more significant in model, or even as the leading factor for influencing device performance, this phenomenon is referred to as
For short-channel effect.Short-channel effect can deteriorate the electric property of device, such as cause threshold voltage of the grid decline, power consumption increase with
And the problems such as signal-to-noise ratio decline.
Fully- depleted (Fully-Depleted) nonplanar device is 20 nanometers such as FinFET (fin FET)
And the ideal chose in following technology generation.Since effective control to the short-channel effect in extremely short channel may be implemented in FinFET,
The serious drain phenomenon in channel is substantially reduced, the S factor during reduction reduces device operating voltages, realizes low pressure and low consumption running.
Meanwhile the conducting channel of FinFET is capable of providing higher conductive current, dramatically increases device and circuit performance.
In the manufacturing process of FinFET, fin is usually formed by etched substrate, however, the limit by photoetching technique
System is difficult to form the high fin of integrated level in FinFET technique, it is difficult to further increase the integrated level of device.
Summary of the invention
In view of this, improving the collection of fin the purpose of the present invention is to provide the manufacturing method of a kind of fin and semiconductor devices
Cheng Du.
To achieve the above object, the present invention has following technical solution:
A kind of manufacturing method of fin, comprising:
Substrate is provided；
Initial graph pattern layer is formed on the substrate, which is semiconductor material, and carries out oxidation technology, first
Initial oxide layer is formed on the side wall of beginning pattern layer, the initial graph pattern layer for being formed with initial oxide layer is first structure；
Form the (n+1)th structure, comprising: the n-th side wall is formed on the side wall of the n-th structure, the n-th side wall is semiconductor material,
And oxidation technology is carried out, the n-th oxide layer is formed on the side wall of the n-th side wall, the n-th side wall for being formed with the n-th oxide layer is (n+1)th
Structure, n from 1 to N, N >=1 and be positive integer；
Remove initial graph pattern layer and initial oxide layer and the first oxide layer to the n-th oxide layer；
The pattern of first side wall to the n-th side wall is transferred in substrate, to form fin.
Optionally, before forming initial graph pattern layer, further includes: deposit the first hard mask layer on substrate；
The pattern of first side wall to the n-th side wall is transferred in substrate, to form fin the step of includes:
It is that masking performs etching with the first side wall to the n-th side wall, forms patterned first hard mask layer；
The first side wall is removed to the n-th side wall；
It is the etching that masking carries out substrate with the first hard mask layer, to form fin；
The first side wall is removed to the n-th side wall.
Optionally, the initial graph pattern layer and the first side wall semiconductor material having the same.
Optionally, the semiconductor material is polysilicon or amorphous silicon.
Optionally, before carrying out oxidation technology, the thickness range of the n-th side wall is 10~100nm.
Optionally, the thickness range of the n-th oxide layer is 5~50nm.
In addition, the present invention also provides a kind of manufacturing method of semiconductor devices, using the fin of any of the above-described method formation
To form fin formula field effect transistor device.
The manufacturing method of fin and semiconductor devices provided in an embodiment of the present invention forms the initial graph pattern layer of semiconductor material
And after being aoxidized, the side wall of semiconductor material is repeatedly formed on side wall, and carries out oxidation technology, and later, removal is initial
After pattern layer and oxide layer, remaining side wall is exposure mask, carries out the transfer of fin, in this way, the side wall formed by oxidation technology
Exposure mask has smooth sidewall profile, and the transfer of fin is carried out by the side wall pattern, and the fin of acquisition has better pattern, together
When, by the size of the easily controllable fin of the thickness of side wall, by the spacing between the easily controllable fin of oxidation technology, thus, it is convenient for
The exposure mask of highdensity fin is formed, and then improves the integrated level of fin.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is the present invention
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 shows the manufacturing method flow chart of fin according to embodiments of the present invention；
Fig. 2-Figure 14 show manufacturing method according to an embodiment of the present invention formed fin it is each during cross-section structure
Schematic diagram.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
Implemented using other than the one described here other way, those skilled in the art can be without prejudice to intension of the present invention
In the case of do similar popularization, therefore the present invention is not limited by the specific embodiments disclosed below.
Secondly, combination schematic diagram of the present invention is described in detail, when describing the embodiments of the present invention, for purposes of illustration only, table
Show that the sectional view of device architecture can disobey general proportion and make partial enlargement, and the schematic diagram is example, is not answered herein
Limit the scope of protection of the invention.In addition, the three-dimensional space of length, width and depth should be included in actual fabrication.
As the description of background technique, in order to improve the density of fin, and then the integrated level of device is improved, the invention proposes
A kind of manufacturing method of fin, refering to what is shown in Fig. 1, this method comprises:
Substrate is provided；
Initial graph pattern layer is formed on the substrate, which is semiconductor material, and carries out oxidation technology, first
The surface of beginning pattern layer forms initial oxide layer, and the initial graph pattern layer for being formed with initial oxide layer is first structure；
Form the (n+1)th structure, comprising: the n-th side wall is formed on the side wall of the n-th structure, the n-th side wall is semiconductor material,
And oxidation technology is carried out, the n-th oxide layer is formed on the surface of the n-th side wall, the n-th side wall for being formed with the n-th oxide layer is (n+1)th
Structure, n from 1 to N, N >=1 and be positive integer；
Remove initial graph pattern layer and initial oxide layer and the n-th oxide layer；
The pattern of n-th side wall is transferred in substrate, to form fin.
In the method for the invention, initial graph pattern layer is semiconductor material, after oxidation, in the side of initial graph pattern layer
Oxide layer is formed on wall, in turn, is formed the side wall of semiconductor material in the side wall of initial graph pattern layer, and aoxidized, is partly being led
The step of foring oxide layer on the side wall side wall of body material, repeatedly forming the side wall of semiconductor material and aoxidized,
Then, initial graph pattern layer and all oxide layers are removed, remaining side wall, can be with by side wall technique as the pattern for forming fin
The smaller pattern of size is formed, meanwhile, after oxidation technology, side wall pattern can be made more smooth, meanwhile, by that can pass through
Spacing between the thickness control fin of oxide layer, thus, convenient for forming the exposure mask of high density and the smooth fin of pattern, and then improve
The integrated level of fin, meanwhile, form the fin of high quality.The manufacturing process that the manufacturing method can use existing cmos device has been come
At the manufacture of the fin of small size, high integration, without being limited by photoetching technique, simple process and feasibility height.
Technical solution and technical effect in order to better understand the present invention, below with reference to specific flow diagram figure
1 pair of specific embodiment is described in detail.
Firstly, substrate 100 is provided, with reference to shown in Fig. 2 in step S01.
In embodiments of the present invention, the substrate be semiconductor substrate, can for Si substrate, Ge substrate, SiGe substrate,
SOI (silicon-on-insulator, Silicon On Insulator) or GOI (germanium on insulator, Germanium On Insulator)
Deng.In other embodiments, the semiconductor substrate can also be the lining for including other elements semiconductor or compound semiconductor
Bottom, such as GaAs, InP or SiC etc., can also be laminated construction, such as Si/SiGe etc., can with other epitaxial structures, such as
SGOI (silicon germanium on insulator) etc..In the present embodiment, the substrate is body silicon substrate.
Then, in step S02, initial graph pattern layer 110 is formed on substrate 100, which is semiconductor material
Material, and oxidation technology is carried out, initial oxide layer 114 is formed in initial graph pattern layer 110, is formed with the initial of initial oxide layer 447
Pattern layer 110 is first structure, with reference to shown in Fig. 4.
In the present embodiment, before the processing technology for carrying out first structure, the first hard exposure mask is first formed on substrate 100
Layer, the transfer of the pattern of fin of first hard mask layer for that will be subsequently formed, while substrate surface being covered, with to substrate into
Row protection.First hard mask layer can be single layer or laminated construction, can be according to the Etch selectivity between subsequent material
Suitable material is selected to form first hard mask layer, such as can be for silica, silicon nitride, silicon oxynitride or theirs folded
Layer, in the present embodiment, refering to what is shown in Fig. 2, first hard mask layer is the lamination of oxygen pad layer 102 and silicon nitride layer 104, pad oxygen
Layer 102 can reduce stress between silicon nitride and silicon substrate.
Then, first structure is formed.Specifically, firstly, deposition initial pattern material 106, may be used also on the original material layer
To be further formed cap rock 108, as shown in Fig. 2, the initial pattern material 106 is semiconductor material, initial pattern material example
It can be such as polysilicon, amorphous silicon or other suitable semiconductor materials, in the present embodiment, initial pattern material is polysilicon,
The cap rock can be silicon nitride or silicon oxynitride or their lamination, for protecting initial pattern, in the present embodiment, and the lid
Layer 108 is silicon nitride.
Then, the photosensitive etching agent of spin coating on the cap rock, and cap rock 108 and initial pattern material 106 are patterned, from
And initial graph pattern layer 110 is formed, it is covered with cap rock 112 in initial graph pattern layer, then, removes photosensitive etching agent, as shown in figure 3,
The width range of the initial graph pattern layer 110 can be 60~500nm, the initial graph pattern layer 110 determined substantially every group of fin it
Between spacing.
Then, oxidation technology is carried out, can be dry oxygen or wet oxygen technique, in the present embodiment, thermal oxidation technology can be used,
In this way, foring initial oxide layer 114, after oxidation technology, initial pattern on the side wall of the exposure of initial graph pattern layer 110
The side wall of layer 110 is more smooth, conducive to the pattern for being subsequently formed the smooth fin of pattern, can pass through the time of control oxidation technology
To form the oxide layer of required thickness.For ease of description, the initial graph pattern layer 110 after formation initial oxide layer 114 is denoted as
First structure.
Then, in step S03, form the (n+1)th structure, comprising: formed on the side wall of the n-th structure the n-th side wall 116,
120,124, the n-th side wall 116,120,124 is semiconductor material, and carries out oxidation technology, in the n-th side wall 116,120,124
The n-th oxide layer 118,122,126 is formed on side wall, the n-th side wall for being formed with the n-th oxide layer is the (n+1)th structure, and n is from 1 to N, N
>=1 and be positive integer, with reference to shown in figure 5-8.
Multiple sidewall structure is formed in this step, it can be according to device it needs to be determined that time of the sidewall structure of formation
Number is illustrated for forming 3 sidewall structures in the present embodiment namely N is 3.It is understood that time of N herein
Number is merely illustrative, the present invention to this and without limitation, can according to it is specific it needs to be determined that formation sidewall structure number.
Firstly, the formation of the second structure is carried out, specifically, firstly, forming the first side wall on the side wall of first structure
116, the first side wall 116 is semiconductor material, and the semiconductor material of the first side wall 116 can choose identical with initial graph pattern layer
Semiconductor material or different semiconductor materials, in the present embodiment, the selection of the first side wall 116 is identical with initial graph pattern layer partly to be led
Body material is all polycrystalline silicon material, can be by depositing the first spacer material, and the thickness of the first spacer material of deposition can be
10~100nm, then by RIE (reactive ion etching), thus, the first side wall 116 is formed on the side wall of first structure, such as
Shown in Fig. 5.Then, oxidation technology is carried out, can be dry oxygen or wet oxygen technique, in the present embodiment, thermal oxidation technology can be used,
After carrying out thermal oxide, the first oxide layer 118 is all formd on the side wall of the first side wall 116 exposure and upper surface, such as Fig. 6
Shown, the thickness of the first oxide layer 118 can be adjusted by controlling the time of thermal oxidation technology, the thickness of the first oxide layer 118
Degree can be 5~50nm, in this way, being formed the first side wall 116 for being formed with the first oxide layer 118 on side wall, have first
First side wall 116 of oxide layer 118 is denoted as the second structure.
Then, the formation for carrying out third structure, with the formation process of the second structure, firstly, on the side wall of the second structure
The second side wall 120 is formed, the second side wall 120 is semiconductor material, and the semiconductor material of the second side wall 120 can choose and first
Side wall identical semiconductor material is all polycrystalline silicon material in the present embodiment, can be deposited by depositing the second spacer material
The second spacer material thickness it is identical as the first side wall thicknesses, then by RIE (reactive ion etching), thus, second
The second side wall 120 is formed on the side wall of structure, as shown in Figure 7.Then, carry out oxidation technology, can be dry oxygen or wet oxygen technique,
In the present embodiment, thermal oxidation technology can be used, after carrying out thermal oxide, in the side wall and upper table of the exposure of the second side wall 120
The second oxide layer 122 is all formd on face, as shown in figure 8, the thickness of the second oxide layer 122 can be by controlling thermal oxidation technology
Time adjust, the thickness of the second oxide layer 122 is identical as the first oxidated layer thickness, formed in this way, being formed on side wall
There is the second side wall 120 of the second oxide layer 122, the second side wall 120 with the second oxide layer 122 is denoted as third structure.
Then, the formation for carrying out the 4th structure, with the formation process of third structure, firstly, on the side wall of third structure
Third side wall 122 is formed, specific method can be identical as the method for the second side wall is formed, and then, carries out oxidation technology, forms the
Three oxide layers 126, as shown in figure 8, specific method can be identical as the method for the second oxide layer is formed, in this way, being formed side
The third side wall 122 of third oxide layer 126 is formed on wall, the third side wall 122 with third oxide layer 126 is denoted as the 4th knot
Structure.
In the present embodiment, initial graph pattern layer and the first side wall to third side wall all use identical semiconductor material
Material is convenient for the selection and control of technique, it is, of course, understood that they can also use different semiconductor materials in this way.
In this step, the side wall of semiconductor material is formd, and then is aoxidized, in the side of the side wall of semiconductor material
Oxide layer is formed on wall, the region covered under side wall is the region that form fin, in this way, the thickness of side wall is substantially true after oxidation
The size of fin is determined, the thickness of oxide layer has determined the spacing between fin substantially, by this technique, on the one hand convenient for control fin
Size and fin between spacing can be realized using traditional technique highly integrated without being limited by photoetching technique
On the other hand the fin of degree after oxidation technology, so that the surface of side wall is more smooth, as the pattern of fin, advantageously forms pattern
Better fin.
Then, in step S04, initial graph pattern layer 110 and initial oxide layer 114 and the first oxide layer 118 are removed to the
N oxide layer 126, with reference to shown in Figure 11.
Specifically, it is possible, firstly, to using the cap rock 112 in the removal initial graph pattern layer 110 of TMAH wet etching selectivity,
As shown in Figure 9.Then, it can use dry or wet etch selectivities removal initial graph pattern layer 110, as shown in Figure 10.Then,
By all oxide layers 114,118,122,126, i.e. initial oxide layer 114, the first oxide layer 118, the second oxide layer 122 and
Three oxide layers 126, selective removal only retain the first side wall 116, the second side wall 120 and third side wall 124, these side walls will
As the pattern for forming fin.
Then, in step S04, the pattern of 116 to the n-th side wall 124 of the first side wall is transferred in substrate 100, to be formed
Fin 130, with reference to shown in Figure 14.
The pattern of 116 to the n-th side wall 124 of the first side wall can be transferred in substrate 100 using suitable technique, this reality
It applies in example, firstly, being that masking performs etching with 116 to the n-th side wall 124 of the first side wall, forms patterned first hard mask layer
104,102, the pattern of side wall is transferred in the first hard mask layer, as shown in figure 12.Then, the first side wall 116 to the n-th is removed
Side wall 124 as shown in figure 13, and is masking with the first hard mask layer 104,102, the etching of substrate 100 is carried out, to form fin
130, finally, the first hard mask layer 104,102 is removed, as shown in figure 14.
So far, the structure of the fin of the embodiment of the present invention is formd in the substrate.Half can be then continuously formed on the fin
Conductor device, i.e. fin formula field effect transistor device, can use preceding grid technique or rear grid technique, formed fin between isolation,
Grid, source and drain and contact etc., thus, form fin formula field effect transistor.
The above is only a preferred embodiment of the present invention, although the present invention has been disclosed in the preferred embodiments as above, so
And it is not intended to limit the invention.Anyone skilled in the art is not departing from technical solution of the present invention ambit
Under, many possible changes and modifications all are made to technical solution of the present invention using the methods and technical content of the disclosure above,
Or equivalent example modified to equivalent change.Therefore, anything that does not depart from the technical scheme of the invention, according to the present invention
Technical spirit any simple modification, equivalent variation and modification made to the above embodiment, still fall within the technology of the present invention side
In the range of case protection.
Claims (7)
1. a kind of manufacturing method of fin characterized by comprising
Substrate is provided；
Initial graph pattern layer is formed on the substrate, which is semiconductor material, and carries out oxidation technology, in initial graph
Initial oxide layer is formed on the side wall of pattern layer, the initial graph pattern layer for being formed with initial oxide layer is first structure；
Form the (n+1)th structure, comprising: the n-th side wall is formed on the side wall of the n-th structure, the n-th side wall is semiconductor material, is gone forward side by side
Row oxidation technology forms the n-th oxide layer on the side wall of the n-th side wall, and the n-th side wall for being formed with the n-th oxide layer is the (n+1)th knot
Structure, n from 1 to N, N >=1 and be positive integer；
Remove initial graph pattern layer and initial oxide layer and the first oxide layer to the n-th oxide layer；
The pattern of first side wall to the n-th side wall is transferred in substrate, to form fin.
2. the manufacturing method according to claim 1, which is characterized in that before forming initial graph pattern layer, further includes: serving as a contrast
The first hard mask layer is deposited on bottom；
The pattern of first side wall to the n-th side wall is transferred in substrate, to form fin the step of includes:
It is that masking performs etching with the first side wall to the n-th side wall, forms patterned first hard mask layer；
The first side wall is removed to the n-th side wall；
It is the etching that masking carries out substrate with the first hard mask layer, to form fin.
3. the manufacturing method according to claim 1, which is characterized in that the initial graph pattern layer and the first side wall are with identical
Semiconductor material.
4. manufacturing method according to claim 3, which is characterized in that the semiconductor material is polysilicon or amorphous silicon.
5. the manufacturing method according to claim 1, which is characterized in that before carrying out oxidation technology, the thickness model of the n-th side wall
It encloses for 10~100nm.
6. the manufacturing method according to claim 1, which is characterized in that the thickness range of the n-th oxide layer is 5~50nm.
7. a kind of manufacturing method of semiconductor devices, which is characterized in that use method shape of any of claims 1-6
At fin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510624492.6A CN106558492B (en) | 2015-09-25 | 2015-09-25 | A kind of manufacturing method of fin and semiconductor devices |
Applications Claiming Priority (1)
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| US20080023803A1 (en) * | 2006-07-31 | 2008-01-31 | Freescale Semiconductor, Inc. | Method for forming vertical structures in a semiconductor device |
| CN104022022A (en) * | 2013-02-28 | 2014-09-03 | 中芯国际集成电路制造(上海)有限公司 | Forming method of multigraph |
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| US20080023803A1 (en) * | 2006-07-31 | 2008-01-31 | Freescale Semiconductor, Inc. | Method for forming vertical structures in a semiconductor device |
| US7556992B2 (en) * | 2006-07-31 | 2009-07-07 | Freescale Semiconductor, Inc. | Method for forming vertical structures in a semiconductor device |
| CN104022022A (en) * | 2013-02-28 | 2014-09-03 | 中芯国际集成电路制造(上海)有限公司 | Forming method of multigraph |
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