CN100561752C - A kind of preparation method of quasi dual-gate MOS transistor - Google Patents
A kind of preparation method of quasi dual-gate MOS transistor Download PDFInfo
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- CN100561752C CN100561752C CNB2007101762074A CN200710176207A CN100561752C CN 100561752 C CN100561752 C CN 100561752C CN B2007101762074 A CNB2007101762074 A CN B2007101762074A CN 200710176207 A CN200710176207 A CN 200710176207A CN 100561752 C CN100561752 C CN 100561752C
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Abstract
The invention provides a kind of quasi dual-gate MOS transistor and preparation method thereof, belong to semiconductor integrated circuit manufacturing technology field.This quasi dual-gate MOS transistor is characterised in that, comprises a buried insulating layer on Semiconductor substrate, and described buried insulating layer is concave structure; Semiconductor source region and drain region embed two projection inboards of described concave structure buried insulating layer respectively, and channel region is positioned at buried insulating layer concavity place, and described semiconductor channel area two ends link to each other with the drain region with described source region respectively; Gate dielectric layer is positioned on the semiconductor channel area; Gate electrode is positioned on the gate dielectric layer; The gate electrode side wall medium layer is positioned at the gate electrode both sides, the top light dope of described channel region or not doping, its underpart heavy doping; Accurate gate electrode links to each other with the heavily doped region of channel region by contact hole.Compare with existing similar self-aligned double-gate, the limitation in bias voltage of MOS transistor of the present invention reduces, and ghost effect also greatly reduces.
Description
Technical field
The invention belongs to semiconductor integrated circuit and manufacturing technology field thereof, relate in particular to a kind of quasi dual-gate MOS transistor (MOSFET) and preparation method thereof.
Background technology
Since the integrated circuit invention, its performance steadily improves always.The raising of performance mainly is to realize by the size of constantly dwindling integrated circuit (IC)-components.At present, the characteristic size of integrated circuit (IC)-components has narrowed down to nanoscale.Under this yardstick, the various basic restrictions with reality begin to occur, and make the development that is based upon the integrated circuit technique on the silicon planar CMOS technology just suffer unprecedented challenge.It is generally acknowledged that through great efforts, the CMOS technology still might be advanced to 20 nanometers even 10 nm technology node, but after 45 nanometer nodes, traditional planar CMOS technology will be difficult to further develop, new technology must produce in good time.Therefore in recent years, the development activities of integrated circuit new technology is worldwide all very active.In the middle of the various new technologies that proposed, multiple-grid MOS device technology is considered to be hopeful most the technology that is applied after inferior 45 nanometer nodes.This be because, compare with the single gate device of tradition, the multiple-grid device has stronger short channel and suppresses ability, better subthreshold characteristic, higher driving force and can bring higher current densities.
At present, the double grid MOS device technology is considered to be hopeful most the technology that is applied after inferior 45 nanometer nodes.Compare with the single gate device of tradition, double-gated devices has stronger short channel and suppresses ability, better subthreshold characteristic, higher driving force and can bring higher current densities.
Dual-gate MOS transistor is usually structurally by two kinds of forms, a kind of is to be representative with FinFET, it is characterized in that the tagma of device (channel region) is perpendicular to the surface of silicon chip, another kind is a plane, it is characterized by the surface that tagma (channel region) still is parallel to silicon chip.The former, self-registered technology easily realizes, but device performance and uniformity are relatively poor, and the latter can make device obtain high-performance and high uniformity, but complicated process of preparation, self-registered technology is difficult to realize.
Summary of the invention
The object of the invention provides a kind of quasi dual-gate MOS transistor that adopts the self-registered technology preparation, this transistor performance height.
Above-mentioned purpose of the present invention is achieved by the following technical solution:
A kind of quasi dual-gate MOS transistor, comprise a source region, a drain region, a buried insulating layer, semi-conductive substrate, a gate electrode, gate electrode and gate dielectric layer, gate electrode side wall medium layer and semiconductor channel area surely, it is characterized in that: described buried insulating layer is on Semiconductor substrate, described semiconductor channel area, source region and drain region are positioned on the buried insulating layer, and described buried insulating layer is concave structure; Described semiconductor source region and drain region embed two projection inboards of described concave structure buried insulating layer respectively, and channel region is positioned at buried insulating layer concavity place, and described semiconductor channel area two ends link to each other with the drain region with described source region respectively; Described gate dielectric layer is positioned on the semiconductor channel area; Described gate electrode is positioned on the gate dielectric layer; Described gate electrode side wall medium layer is positioned at the gate electrode both sides, and the top of described channel region is light dope or does not mix that its underpart is heavy doping; Described accurate gate electrode links to each other with the heavily doped region of channel region by contact hole.
The width in described buried insulating layer concavity district is less than or equal to the length of described gate electrode.
Described gate electrode is polysilicon electrode and/or metal electrode.
A kind of preparation method of quasi dual-gate MOS transistor may further comprise the steps:
1) semi-conducting material of employing soi structure, it has one deck buried insulating layer, the layer of semiconductor film, semi-conductive substrate, buried insulating layer carries out highly doped to semiconductor film layer between semiconductive thin film and Semiconductor substrate;
2) adopt growth technology to form the new semiconductor lamella of one deck on highly doped semiconductor film layer, new semiconductor lamella does not mix or is low-doped;
3) photoetching and etching semiconductor film and semiconductor lamella are formed with the source region to buried insulating layer, described active area contain one with the vertical body contact zone that links to each other of channel region, the gate dielectric layer of growing then;
4) deposit gate electrode layer and sacrificial dielectric layer, and photoetching and etching sacrificial dielectric layer and gate electrode layer form gate electrode figure, and the top sacrificial dielectric layer on the gate electrode figure, this gate electrode figure and top sacrificial dielectric layer except that covering channel region, also nappe contact area;
5) deposit sacrificial dielectric layer once more, Hui Kehou forms the gate electrode side wall in the gate electrode both sides, with the gate electrode side wall and the top sacrificial dielectric layer that form is that mask corrosion falls the gate dielectric layer that the gate electrode figure both sides appear, and is not mixed in both sides or low-doped semiconductor film laminar surface exposes;
6) corrode not doping or the low-doped semiconductor lamella that is exposed, stop corrosion during to the high doping semiconductor thin layer;
7) further selective etching high doping semiconductor thin layer stops corrosion when arriving gate electrode figure covering place;
8) deposit dielectric is filled the cavity that corrosion forms, and returns and carves the dielectric of removing the surface;
9) erode another film dielectric layer of regrowth after gate electrode side wall and the top sacrificial dielectric layer;
10) ion implantation doping gate electrode figure, and make the semiconductor lamella of gate electrode figure both sides become source, drain region simultaneously, return then to engrave and state film dielectric layer to form new gate electrode side wall;
11) photoetching and be etched away the gate electrode part of nappe contact zone, and carry out ion implantation doping and make not doping or light doping section under it be transformed into heavily doped region, enter the conventional cmos later process at last, comprise deposit passivation layer, opening contact hole and metallization, so just make accurate double gate SOI MOS transistor.
In described step 1) semiconductive thin film is carried out ion implantation doping, the injection energy is 50～80KeV, and implantation dosage is 0.5 * 10
15～5 * 10
15Cm
-2
In described step 2) described in epitaxially grown semiconductor lamella be silicon fiml or germanium-silicon alloy film.
In described step 2) described between the thickness 10～50nm of epitaxially grown semiconductor lamella.
Thickness at the gate dielectric layer of growth described in the described step 3) is between 0.5～3nm.
In described step 7), described high doping semiconductor thin layer is a heavily doped silicon, the corroded high doping silicon layer, and etchant solution is hydrofluoric acid, nitric acid and acetate mixture, fills a prescription to be 40%HF: 70%HNO
3: 100%CH
3COOH mixes with volume ratio at 1: 3: 8.
Advantage of the present invention and good effect:
Between leaking, the body electrode of existing accurate gate electrode and source isolate by the pn knot, when pn became forward bias, leakage current and parasitic capacitance between leak in tagma and source were very big, and in order to prevent that pn from tying complete conducting, the bias voltage in tagma must be less than 0.7 volt, and its range of application is very limited like this.The buried insulating layer of MOS transistor of the present invention has concave structure, tagma (channel region) is positioned at recess, like this, be dielectric isolation as the heavy doping tagma of second gate electrode (accurate gate electrode) and source, between leaking, make that leakage current and the parasitic capacitance between this tagma and source or leakage greatly reduces.Compare with existing quasi dual-gate MOS transistor, the limitation in bias voltage of MOS transistor of the present invention is little.
Description of drawings:
Fig. 1 is the highly doped process sequence diagram of SOI silicon layer;
Fig. 2 is the process sequence diagram of epitaxial growth silicon fiml on high-doped zone;
Fig. 3 is the process sequence diagram of active area formation and growth gate dielectric layer, and wherein, b is the schematic diagram that photoetching and etching silicon fiml are formed with the source region, and a is the profile along the BB ' direction of figure b, and c is the profile along the AA ' direction of scheming b;
Fig. 4 is the process sequence diagram that gate electrode forms, and wherein, b is for forming the schematic diagram of polysilicon electrode, and a is the profile along the BB ' direction of figure b, and c is the profile along the AA ' direction of figure b;
Fig. 5 is the process sequence diagram that gate electrode side wall protection layer forms, and wherein, b is for forming the schematic diagram of gate electrode side wall, and a is the profile along the BB ' direction of figure b, and c is the profile along the AA ' direction of figure b;
Fig. 6 is the process sequence diagram that the silicon fiml corrosion forms the silicon groove, and wherein, b is the schematic diagram that the silicon fiml corrosion forms the silicon groove, and a is the profile along the BB ' direction of figure b, and c is the profile along the AA ' direction of figure b;
Fig. 7 is the process sequence diagram of the highly doped silicon layer of selective etching, and wherein, b is the schematic diagram of corroded high doping silicon layer, and a is the profile along the BB ' direction of figure b, and c is the profile along the AA ' direction of figure b;
Fig. 8 is the process sequence diagram of filling the silicon groove, and wherein, b is for filling the schematic diagram of silicon groove, and a is the profile along the BB ' direction of figure b, and c is the profile along the AA ' direction of figure b;
Fig. 9 is that the gate electrode side wall forms for the second time, leak in the source and the process sequence diagram of grid ion implantation doping and the formation of body contact zone, wherein, the schematic diagram that b forms for the body contact zone, a are the profile along the BB ' direction of figure b, and c is the profile along the AA ' direction of figure b;
Figure 10 is the metallization schematic diagram, and wherein, a is the schematic diagram that the accurate double gate SOI MOS transistor metal electrode that makes distributes, and b be the profile along the AA ' direction of figure a, and c be the profile that the BB ' direction of a is schemed on the edge.
Among the figure:
The 1-silicon substrate; The 2-oxygen buried layer; The 3-silicon fiml; The epitaxially grown silicon fiml of 4-; The 5-gate dielectric layer; 6-silicon nitride sacrifice layer; The 7-polysilicon; 8-silicon groove; The 9-cavity; 10-silicon dioxide; 11-silicon dioxide side wall 12-source region; The 13-drain region; 14-source electrode; The 15-drain electrode; 16-grid metal electrode; The accurate gate electrode of 17-; The 110-phosphorosilicate glass; The 120-contact hole.
Embodiment:
Following specific embodiment helps to understand the features and advantages of the present invention, but enforcement of the present invention never only is confined to described embodiment.
One specific embodiment of manufacture method of the present invention comprises Fig. 1 to Fig. 9:
1. as shown in Figure 1, used soi wafer is by silicon substrate 1, and oxygen buried layer 2 and monocrystalline silicon membrane 3 are formed.The crystal orientation of monocrystalline silicon membrane 3 is (100), is initially light dope, and thickness is 50～250nm.Then to carrying out BF on the silicon fiml 3
2Ion injects, and the injection energy is 50～80KeV, and implantation dosage is (0.5～5) * 10
15Cm
-2, make silicon fiml 3 become high doped materials.
2. as shown in Figure 2, the new silicon fiml 4 of epitaxial growth one deck on highly doped silicon fiml 3, this silicon fiml 4 is not doping or low-doped, thickness is 10～50nm.
3. as shown in Figure 3, photoetching and etching silicon fiml 4 and 3 are formed with the source region, and active area contains one contact zone 4 '.The heat growth silicon dioxide gate dielectric layer 5 then, and its thickness is 0.5～3nm.
4. deposit gate electrode polysilicon and sacrificial dielectric layer silicon nitride layer as shown in Figure 4; The thickness of polysilicon layer is 80～250nm, and the thickness of silicon nitride layer is 20～40nm.The sacrificial dielectric layer silicon nitride and the polysilicon layer of photoetching and the deposit of etching institute form gate electrode figure 7 and body contact zone coated electrode 7 '.
5. as shown in Figure 5, deposit one deck silicon nitride and time quarter (etch back) are the silicon nitride side wall of 25～150nm at polysilicon electrode 7 and 7 ' both sides formation width again.This side wall is formed gate electrode protective layer 6 with the top silicon nitride of previous growth.With this protective layer 6 is the exposed part that mask corrosion falls grid silicon dioxide layer 5.
6. as shown in Figure 6, be mask with silicon nitride protective layer 6, reactive ion etching (RIE) silicon fiml 4 forms silicon groove 8 to expose highly doped silicon layer 3, and the degree of depth of silicon groove 8 is 20～80nm.
7. as shown in Figure 7, adopt selective etching technology corroded high doping silicon layer 3, etchant solution is hydrofluoric acid, nitric acid and acetate mixture, fills a prescription to be 40%HF: 70%HNO
3: 100%CH
3COOH mixes with volume ratio at 1: 3: 8.By the control time, make corrosion arrive gate electrode 7 boundaries and stop, forming cavity 9 up to gate electrode 7 boundaries.
8. as shown in Figure 8, adopting CVD method deposit one layer thickness is the silicon dioxide of 100～200nm, silicon groove 8 and cavity 9 under leaking in order to the source of filling corrosion formation, and the insulating barrier 10 under the leakage of formation source returns and carves the silicon dioxide of removing the surface.
9. as shown in Figure 9, fall the sacrificial dielectric silicon nitride 6 of all gate electrode tops and both sides with hot phosphoric acid corrosion, and be the silica dioxide medium layer of 5～20nm with CVD another thickness of growing, and as resilient coating, the silicon layer part of twice ion implantation doping gate electrode and gate electrode both sides forms the source region 12 and the drain region 13 of dope gate electrode 7 and device respectively.Dopant is an arsenic, injects energy and is respectively 10～33KeV and 45～75KeV, and implantation dosage is (1～5) * 10
15Cm
-2The described ion of last anisotropic dry etch injects resilient coating to form silicon dioxide side wall 11 and the source region of device and drain region are exposed on the surface of gate electrode both sides.According to circumstances, the source leak can adopt epitaxy method to form the source-drain structure of raising.Then, photoetching and etching are removed the polysilicon segment 7 ' that covers tagma contact area 4 ', and carry out boron ion implantation doping, make the area of coverage under it all be transformed into heavily doped region 3 '.Inject energy 5～20KeV, implantation dosage (1～5) * 10
15Cm
-2
10. as shown in figure 10, enter the conventional cmos later process at last, the phosphorosilicate glass layer that comprises deposit one deck 200～500nm is as passivation layer (110), by photoetching and this passivation layer of etching respectively in the source 12, leak 13 and the contact zone 3 ' opening contact hole 120 of gate electrode 7, accurate gate electrode, and the aluminium film of deposit one deck 400～800nm and photoetching and etching form source electrode 14, drain electrode 15 and metal electrodes such as gate electrode 16 and accurate gate electrode 17.Accurate gate electrode 17 links to each other with heavily doped tagma 3 by contact hole 120 and heavily doped body contact zone 3 '.So far, just made the accurate double gate SOI MOS transistor of a described n raceway groove.
The preparation process of p channel device, except that doping condition should be adjusted accordingly, making step was identical.Wherein in the step 1, implanted dopant is As, and the injection energy is 5～50KeV, and implantation dosage is (1～5) * 10
15Cm
-2In the step 9, the source region 12 of gate electrode 7 and device and the implanted dopant in drain region 13 are BF
2, injecting energy and be respectively 5～33KeV and 45～75KeV, implantation dosage is (1～5) * 10
15Cm
-2In step 9, the implanted dopant of contact area 4 is As equally, injects energy 10～20KeV, implantation dosage (1～5) * 10
15Cm
-2
More than by specific embodiment quasi dual-gate MOS transistor provided by the present invention (MOSFET) and preparation method thereof has been described, those skilled in the art is to be understood that, in the scope that does not break away from essence of the present invention, can make certain deformation or modification to the present invention, its preparation method also is not limited to disclosed content among the embodiment.
Claims (6)
1, a kind of preparation method of quasi dual-gate MOS transistor may further comprise the steps:
1) semi-conducting material of employing soi structure, it has one deck buried insulating layer, the layer of semiconductor film, semi-conductive substrate, buried insulating layer carries out highly doped to semiconductor film layer between semiconductive thin film and Semiconductor substrate;
2) adopt growth technology to form the new semiconductor lamella of one deck on highly doped semiconductor film layer, new semiconductor lamella does not mix or is low-doped;
3) photoetching and etching semiconductor film and semiconductor lamella are formed with the source region to buried insulating layer, described active area contain one with the vertical body contact zone that links to each other of channel region, the gate dielectric layer of growing then;
4) deposit gate electrode layer and sacrificial dielectric layer, and photoetching and etching sacrificial dielectric layer and gate electrode layer, form gate electrode figure, and the top sacrificial dielectric layer on the gate electrode figure, this gate electrode figure and top sacrificial dielectric layer except that covering channel region, also nappe contact area;
5) deposit sacrificial dielectric layer once more, Hui Kehou forms the gate electrode side wall in the gate electrode both sides, with the gate electrode side wall and the top sacrificial dielectric layer that form is that mask corrosion falls the gate dielectric layer that the gate electrode figure both sides appear, and is not mixed in both sides or low-doped semiconductor film laminar surface exposes;
6) corrode not doping or the low-doped semiconductor lamella that is exposed, stop corrosion during to the high doping semiconductor thin layer;
7) further selective etching high doping semiconductor thin layer stops corrosion when arriving gate electrode figure covering place;
8) deposit dielectric is filled the cavity that corrosion forms, and returns and carves the dielectric of removing the surface;
9) erode another film dielectric layer of regrowth after gate electrode side wall and the top sacrificial dielectric layer;
10) ion implantation doping gate electrode figure, and make the semiconductor lamella of gate electrode figure both sides become source, drain region simultaneously, return then to engrave and state film dielectric layer to form new gate electrode side wall;
11) photoetching and be etched away the gate electrode part of nappe contact zone, and carry out ion implantation doping and make not doping or light doping section under it be transformed into heavily doped region, enter the conventional cmos later process at last, comprise deposit passivation layer, opening contact hole and metallization, so just make accurate double gate SOI MOS transistor.
2, the preparation method of quasi dual-gate MOS transistor as claimed in claim 1 is characterized in that: in the described step 1) semiconductive thin film is carried out ion implantation doping, the injection energy is 50～80KeV, and implantation dosage is 0.5 * 10
15～5 * 10
15Cm
-2
3, the preparation method of quasi dual-gate MOS transistor as claimed in claim 1 is characterized in that: in described step 2) described in epitaxially grown semiconductor lamella be silicon fiml or germanium-silicon alloy film.
4, as the preparation method of claim 1 or 3 described quasi dual-gate MOS transistors, it is characterized in that: in described step 2) described between the thickness 10～50nm of epitaxially grown semiconductor lamella.
5, the preparation method of quasi dual-gate MOS transistor as claimed in claim 1 is characterized in that: the thickness at the gate dielectric layer of growth described in the described step 3) is between 0.5～3nm.
6, the preparation method of quasi dual-gate MOS transistor as claimed in claim 1, it is characterized in that: in described step 7), described high doping semiconductor thin layer is a heavily doped silicon, the corrosion etchant solution that heavily doped silicon adopted is hydrofluoric acid, nitric acid and acetate mixture, and filling a prescription is 40%HF: 70%HNO
3: 100%CH
3COOH mixes with volume ratio at 1: 3: 8.
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| CN104576377A (en) * | 2013-10-13 | 2015-04-29 | 中国科学院微电子研究所 | Mosfet structure and manufacturing method thereof |
| CN103730405B (en) * | 2014-01-07 | 2016-09-14 | 上海华虹宏力半导体制造有限公司 | Soi structure and preparation method thereof |
| CN111952184B (en) * | 2020-08-21 | 2024-04-12 | 中国科学院上海微系统与信息技术研究所 | Preparation method of gate-all-around field effect transistor based on patterned buried dielectric layer |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0299185A2 (en) * | 1987-07-15 | 1989-01-18 | International Business Machines Corporation | Thin film field effect transistor |
| CN1300102A (en) * | 1999-10-25 | 2001-06-20 | 三星电子株式会社 | SOI semiconductor integrated circuit for eliminating floater effect and mfg. method thereof |
| US6452232B1 (en) * | 1998-12-03 | 2002-09-17 | Sharp Kabushiki Kaisha | Semiconductor device having SOI structure and manufacturing method thereof |
| CN1851930A (en) * | 2006-04-11 | 2006-10-25 | 北京大学深圳研究生院 | Partial consumption SOI MOS transistor and making method |
-
2007
- 2007-10-23 CN CNB2007101762074A patent/CN100561752C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0299185A2 (en) * | 1987-07-15 | 1989-01-18 | International Business Machines Corporation | Thin film field effect transistor |
| US6452232B1 (en) * | 1998-12-03 | 2002-09-17 | Sharp Kabushiki Kaisha | Semiconductor device having SOI structure and manufacturing method thereof |
| CN1300102A (en) * | 1999-10-25 | 2001-06-20 | 三星电子株式会社 | SOI semiconductor integrated circuit for eliminating floater effect and mfg. method thereof |
| CN1851930A (en) * | 2006-04-11 | 2006-10-25 | 北京大学深圳研究生院 | Partial consumption SOI MOS transistor and making method |
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