CN109671780B - Schottky barrier transistor and preparation method thereof - Google Patents
Schottky barrier transistor and preparation method thereof Download PDFInfo
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- CN109671780B CN109671780B CN201811436193.XA CN201811436193A CN109671780B CN 109671780 B CN109671780 B CN 109671780B CN 201811436193 A CN201811436193 A CN 201811436193A CN 109671780 B CN109671780 B CN 109671780B
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- 230000004888 barrier function Effects 0.000 title claims abstract description 55
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims abstract description 180
- 239000002184 metal Substances 0.000 claims abstract description 180
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 156
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 151
- 239000000758 substrate Substances 0.000 claims abstract description 83
- 239000007769 metal material Substances 0.000 claims description 50
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 30
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 30
- 229910052710 silicon Inorganic materials 0.000 claims description 30
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- 238000005036 potential barrier Methods 0.000 claims description 4
- 229910018250 LaSi Inorganic materials 0.000 claims description 3
- 229910008484 TiSi Inorganic materials 0.000 claims description 3
- 229910006249 ZrSi Inorganic materials 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 229910052735 hafnium Inorganic materials 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
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- 229910002601 GaN Inorganic materials 0.000 description 1
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- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66643—Lateral single gate silicon transistors with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7839—Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention provides a Schottky barrier transistor and a preparation method thereof. The schottky barrier transistor includes a substrate and a gate structure on the substrate, the schottky barrier transistor further including: a channel region on a surface of the substrate corresponding to the gate structure, the channel region including a first metal silicide layer; the source-drain region comprises a second metal silicide layer and a third metal silicide layer which are positioned at two sides of the channel region, the second metal silicide layer is positioned in the substrate, the third metal silicide layer is positioned on the surface of the substrate corresponding to the second metal silicide layer, and the work function of the second metal silicide layer is smaller than that of the third metal silicide layer. The Schottky barrier transistor has a high mobility channel, so that the on-state current of the device can be improved, and the off-state current of the transistor can be reduced, so that the current switching ratio of the device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a Schottky barrier transistor and a preparation method thereof.
Background
As the gate length of the device is reduced to nano-scale, schottky source-drain has a series of advantages, such as atomic-level abrupt junction, low source-drain series resistance and contact resistance, low source-drain process suitable for integrating high-K metal gate, etc., which become the most potential substitutes for doped source-drain transistors.
However, the conventional schottky barrier device has a problem of low current switching ratio because the schottky barrier height of the source/channel is high in the on state and the schottky barrier height of the drain/channel is low in the off state.
Disclosure of Invention
The invention mainly aims to provide a Schottky barrier transistor and a preparation method thereof, which are used for solving the problem of low current switching ratio of a Schottky barrier device in the prior art.
In order to achieve the above object, according to one aspect of the present invention, there is provided a schottky barrier transistor including a substrate and a gate structure on the substrate, the schottky barrier transistor further comprising: a channel region on a surface of the substrate corresponding to the gate structure, the channel region including a first metal silicide layer; the source-drain region comprises a second metal silicide layer and a third metal silicide layer which are positioned at two sides of the channel region, the second metal silicide layer is positioned in the substrate, the third metal silicide layer is positioned on the surface of the substrate corresponding to the second metal silicide layer, and the work function of the second metal silicide layer is smaller than that of the third metal silicide layer.
Further, the schottky barrier transistor is a PMOS transistor, and the material for forming the first metal silicide layer includes a first metal, preferably SiGe; the material for forming the second metal silicide layer comprises a second metal with a work function of 2.0-4.3 eV, preferably the second metal silicide layer is selected from HfSi x 、ZrSi x 、LaSi x 、TiSi x 、EuSi x And GdSi x Wherein x is more than or equal to 1 and less than or equal to 2; the material for forming the third metal silicide layer comprises a first metal and a third metal, the work function of the third metal is 4.3-5.65 eV, and the third metal silicide layer is preferably selected from Al 2 Si x Ge y 、Co 2 Si x Ge y 、Ir 2 Si x Ge y 、Ni 2 Si x Ge y 、Pd 2 Si x Ge y 、Pt 2 Si x Ge y And Ti is 2 Si x Ge y Wherein x is not less than 1 and not more than 2, and y is not less than 1 and not more than 2.
Further, a potential barrier between the first metal silicide layer and the third metal silicide layer is 0.5 to 1eV.
Further, the channel region further comprises a cap layer arranged between the first metal silicide layer and the gate structure, preferably the material forming the cap layer is Si, and preferably the thickness of the cap layer is 2-5 nm.
Further, the substrate is an SOI substrate including a silicon substrate, a buried oxide layer, and a silicon layer sequentially stacked, the first metal silicide layer is provided on a surface of the silicon layer, and the second metal silicide layer is provided in the silicon layer.
According to another aspect of the present invention, there is provided a method of manufacturing a schottky barrier transistor, comprising the steps of: s1, providing a substrate, sequentially forming a first metal silicide on the surface of the substrate and a gate structure on part of the surface of the first metal silicide, wherein the first metal silicide is formed by adopting a material comprising a first metal, a second metal silicide layer is formed in the substrate corresponding to two sides of the gate structure, a third metal silicide layer is formed in the first metal silicide corresponding to two sides of the gate structure, the work function of the second metal silicide layer is smaller than that of the third metal silicide layer, the second metal silicide layer and the third metal silicide layer form a structure in a source region and a drain region of the Schottky barrier transistor, and the rest of the first metal silicide forms the first metal silicide layer in a channel region of the Schottky barrier transistor.
Further, the substrate is an SOI substrate, the SOI substrate includes a buried oxide layer and a silicon layer located on a surface of the buried oxide layer, and the step of providing the substrate includes: the silicon layer is oxidized and the oxidation product is removed to thin the silicon layer, preferably by BOE etching, preferably with a thickness of 1-20 nm.
Further, after providing the substrate, step S1 includes the steps of: epitaxially forming a first metal silicide, preferably epitaxial SiGe, on a surface of the substrate to form the first metal silicide; and forming a grid electrode on the first metal silicide, forming a side wall covering the surface of the grid electrode, wherein the grid electrode and the side wall form a grid electrode structure, and the grid electrode is preferably a stacked structure formed by a high-k dielectric layer and a metal grid electrode.
Further, between the steps of forming the first metal silicide and forming the gate structure, step S1 further includes the steps of: and forming a cap layer on the surface of the first metal silicide, wherein the gate structure is positioned on the surface of the cap layer, preferably the material forming the cap layer is Si, and the thickness of the cap layer is preferably 2-5 nm.
Further, the step of forming the second metal silicide layer includes: depositing a second metal material on the gate structure and the first metal silicide, wherein the second metal material preferably has a work function of 2.0-4.3 eV, and more preferably the second metal material is selected from any one of Hf, zr, la, ti, eu and Gd; the second metal material is subjected to a first heat treatment to react a portion of the substrate located at both sides of the gate structure with the second metal material and remove unreacted second metal material to obtain a second metal silicide layer, and preferably the temperature of the first heat treatment is 250-400 ℃.
Further, through a first heat treatment, a part of the first metal silicide located at two sides of the gate structure reacts with the second metal material, and then the unreacted second metal material is removed, so that a third metal silicide layer is obtained.
Further, the step of forming the third metal silicide layer includes the steps of: depositing a third metal material, preferably having a work function of 4.3-5.65 eV, more preferably selected from Al, co, ir, ni, pd, pt and Ti, on the gate structure and the fourth metal silicide layer y Any one of them; and performing a second heat treatment on the third metal material to enable part of the fourth metal silicide layer positioned on two sides of the gate structure to react with the third metal material, and obtaining the third metal silicide layer after removing unreacted third metal material, wherein the temperature of the second heat treatment is preferably 400-700 ℃.
By applying the technical scheme of the invention, the Schottky barrier transistor is provided, and has a high mobility channel, so that the on-state current of the device can be improved; the low Schottky barrier at the upper layer in the source drain region can improve the on-state current of the transistor, the high Schottky barrier at the lower layer can improve the immunity of the device to the short channel effect, and the off-state current of the transistor is reduced, so that the current switching ratio of the device is improved; and the structure of the laminated silicide in the source and drain regions is completely compatible with the current CMOS technology.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention. In the drawings:
fig. 1 is a schematic cross-sectional view showing a schottky barrier transistor according to an embodiment of the present application;
fig. 2 is a schematic diagram showing a cross-sectional structure of a substrate after providing a substrate in the method for manufacturing a schottky barrier transistor according to the embodiment of the present application;
FIG. 3 is a schematic cross-sectional view showing a structure of a substrate after thinning the silicon layer shown in FIG. 2;
fig. 4 is a schematic view showing a cross-sectional structure of a base body after epitaxially forming a first metal silicide on the surface of the substrate shown in fig. 3;
fig. 5 is a schematic diagram showing a cross-sectional structure of a substrate after forming a gate structure on the first metal silicide shown in fig. 4 and forming a sidewall covering a surface of the gate structure;
FIG. 6 is a schematic diagram showing a cross-sectional structure of a substrate after deposition of a second metal material on the gate structure and the first metal silicide shown in FIG. 5;
FIG. 7 is a schematic diagram showing a cross-sectional structure of a substrate after obtaining a second metal silicide layer and a fourth metal silicide layer;
FIG. 8 is a schematic diagram showing a cross-sectional structure of a substrate after deposition of a third metal material on the gate structure and the fourth metal silicide layer shown in FIG. 7;
fig. 9 shows a schematic cross-sectional structure of the substrate after the third metal silicide layer is obtained.
Wherein the above figures include the following reference numerals:
10. a substrate; 110. an oxygen burying layer; 120. a silicon layer; 20', a first metal silicide; 20. a first metal silicide layer; 30. a gate; 40. a side wall; 50. a second metal material; 60. a second metal silicide layer; 70. a fourth metal silicide layer; 80. a third metal material; 90. and a third metal silicide layer.
Detailed Description
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other. The invention will be described in detail below with reference to the drawings in connection with embodiments.
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As described in the background art, the conventional schottky barrier device has a problem of low current switching ratio due to a higher schottky barrier height of the source/channel in the on state and a lower schottky barrier height of the drain/channel in the off state. The inventors of the present invention studied to solve the above problems and have proposed a schottky barrier transistor, as shown in fig. 1, including a substrate 10 and a gate structure on the substrate 10, the schottky barrier transistor further including: a channel region on the surface of the substrate 10 corresponding to the gate structure, the channel region including a first metal silicide layer 20; the source-drain region comprises a second metal silicide layer 60 and a third metal silicide layer 90 which are positioned at two sides of the channel region, the second metal silicide layer 60 is positioned in the substrate 10, the third metal silicide layer 90 is positioned on the surface of the substrate 10 corresponding to the second metal silicide layer 60, and the work function of the second metal silicide layer 60 is smaller than that of the third metal silicide layer 90.
The Schottky barrier transistor has a high mobility channel, so that the on-state current of the device can be improved; the low Schottky barrier at the upper layer in the source drain region can improve the on-state current of the transistor, the high Schottky barrier at the lower layer can improve the immunity of the device to the short channel effect, and the off-state current of the transistor is reduced, so that the current switching ratio of the device is improved; and the structure of the laminated silicide in the source and drain regions is completely compatible with the current CMOS technology.
The schottky barrier transistor may be a PMOS transistor or an NMOS transistor, and the PMOS transistor and the NMOS transistor may be applied to CMOS. The schottky barrier transistor provided by the present invention will be described in more detail below by taking a PMOS transistor as an example.
In the above schottky barrier transistor of the present invention, the raw material for forming the first metal silicide layer 20 may include a first metal having high mobility; and in order to secure high mobility of the channel, it is preferable that the first metal silicide layer 20 is formed of SiGe.
In order to ensure that the upper layer in the source drain region can form a low schottky barrier, preferably, the material forming the second metal silicide layer 60 includes a second metal having a work function of 2.0 to 4.3eV; also, in order to ensure that the lower layer in the source drain region can form a high schottky barrier, it is preferable that the material forming the third metal silicide layer 90 includes a first metal and a third metal, and the work function of the third metal is 4.3 to 5.65eV. More preferably, a potential barrier between the first metal silicide layer 20 and the third metal silicide layer 90 is 0.5 to 1eV.
Preferably, the second metal silicide layer 60HfSi x 、ZrSi x 、LaSi x 、TiSi x 、EuSi x And GdSi x Wherein x is more than or equal to 1 and less than or equal to 2; the third metal silicide layer 90 is selected from Al 2 Si x Ge y 、Co 2 Si x Ge y 、Ir 2 Si x Ge y 、Ni 2 Si x Ge y 、Pd 2 Si x Ge y 、Pt 2 Si x Ge y And Ti is 2 Si x Ge y Wherein x is not less than 1 and not more than 2, and y is not less than 1 and not more than 2. But is not limited toIn the above preferred classes, the person skilled in the art can choose reasonably the second metal and the third metal satisfying the above work functions according to the prior art.
In the schottky barrier transistor of the present invention, as shown in fig. 1, the gate structure may include a gate electrode 30 and a sidewall 40 surrounding the gate electrode 30, the gate electrode 30 may be a stacked structure formed by a high-k dielectric layer and a metal gate electrode, and in order to avoid degradation of an interface between the high-k dielectric layer and the first metal silicide layer 20, the channel region preferably further includes a cap layer (not shown) disposed between the first metal silicide layer 20 and the gate structure. More preferably, the cap layer is formed of Si; more preferably, the cap layer has a thickness of 2 to 5nm.
In the schottky barrier transistor of the present invention, the substrate 10 may be one of a silicon substrate, a germanium substrate, a gallium nitride substrate, a glass substrate, a silicon-on-insulator substrate (SOI substrate), a germanium-on-insulator substrate, and the like. Preferably, the substrate 10 is an SOI substrate including a silicon substrate, a buried oxide layer 110, and a silicon layer 120 sequentially stacked, and as shown in fig. 1, the first metal silicide layer 20 is disposed on a surface of the silicon layer 120, and the second metal silicide layer 60 is disposed in the silicon layer 120.
According to another aspect of the present invention, there is also provided a method for manufacturing a schottky barrier transistor, as shown in fig. 2 to 9, including the steps of: s1, providing a substrate 10, and sequentially forming a first metal silicide 20 ' on the surface of the substrate 10 and a gate structure on part of the surface of the first metal silicide 20 ', wherein the first metal silicide 20 ' is formed by adopting a material comprising a first metal; s2, forming a second metal silicide layer 60 in the substrate 10 corresponding to both sides of the gate structure, and forming a third metal silicide layer 90 in the first metal silicide 20 'corresponding to both sides of the gate structure, wherein the work function of the second metal silicide layer 60 is smaller than that of the third metal silicide layer 90, the second metal silicide layer 60 and the third metal silicide layer 90 constitute the structure in the source drain region, and the remaining first metal silicide 20' constitutes the first metal silicide layer 20 in the channel region.
The Schottky barrier transistor formed by the preparation method has a high mobility channel, so that the on-state current of the device can be improved; the low Schottky barrier at the upper layer in the source drain region can improve the on-state current of the transistor, the high Schottky barrier at the lower layer can improve the immunity of the device to the short channel effect, and the off-state current of the transistor is reduced, so that the current switching ratio of the device is improved; and the structure of the laminated silicide in the source and drain regions is completely compatible with the current CMOS technology.
Exemplary embodiments of a method of manufacturing a schottky barrier transistor provided according to the present invention will be described in more detail below. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It should be appreciated that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.
First, step S1 is performed: the substrate 10 is provided and a first metal silicide 20 ' on the surface of the substrate 10 and a gate structure on a portion of the surface of the first metal silicide 20 ' are sequentially formed, wherein the first metal silicide 20 ' is formed using a material including a first metal, as shown in fig. 2 to 5.
The substrate 10 may be an SOI substrate, as shown in fig. 2, where the SOI substrate includes a buried oxide layer 110 and a silicon layer 120 located on a surface of the buried oxide layer 110, and in this case, the step of providing the substrate 10 preferably includes: the silicon layer 120 is oxidized and oxidation products are removed to thin the silicon layer 120 as shown in fig. 3. More preferably, BOE etching is adopted to remove the oxidation products; more preferably, the thickness of the silicon layer 120 is 1 to 20nm.
In a preferred embodiment, after providing the substrate 10, the step S1 includes the steps of: epitaxially forming a first metal silicide 20' on the surface of the substrate 10, as shown in fig. 4; a gate electrode 30 is formed on the first metal silicide 20', and a sidewall 40 is formed to cover the surface of the gate electrode 30, where the gate electrode 30 and the sidewall 40 form the gate structure as shown in fig. 5.
In the above preferred embodiment, to ensure high mobility of the channel, more preferably SiGe is epitaxially formed to form the first metal silicide 20'. More preferably, the gate 30 is a stacked structure of a high-k dielectric layer and a metal gate.
When the gate electrode 30 is a stacked structure formed by a high-k dielectric layer and a metal gate electrode, in order to avoid degradation of the interface between the high-k dielectric layer and the first metal silicide layer 20, it is further preferable that the channel region further includes a cap layer (not shown) disposed between the first metal silicide layer 20 and the gate structure. Further preferably, the cap layer is formed of Si; further preferably, the thickness of the cap layer is 2 to 5nm.
After the above step S1 is completed, step S2 is performed: a second metal silicide layer 60 is formed in the substrate 10 corresponding to both sides of the gate structure, and a third metal silicide layer 90 is formed in the first metal silicide 20' corresponding to both sides of the gate structure, and the work function of the second metal silicide layer 60 is smaller than that of the third metal silicide layer 90, as shown in fig. 6 to 9.
The step of forming the second metal silicide layer 60 may include: a second metal material 50 is deposited over the gate structure and the first metal silicide 20', as shown in fig. 6; the second metal material 50 is subjected to a first heat treatment to react a portion of the substrate 10 located at both sides of the gate structure with the second metal material 50 and remove the unreacted second metal material 50 to obtain a second metal silicide layer 60, as shown in fig. 7.
In order to ensure that the upper layer in the source drain region can form a low schottky barrier, it is preferable that the work function of the second metal material 50 is 2.0 to 4.3eV; more preferably, the second metal material 50 is selected from any one of Hf, zr, la, ti, eu and Gd, but is not limited to the preferred species, and the person skilled in the art may reasonably select the second metal material 50 satisfying the work function according to the prior art. Preferably, the temperature of the first heat treatment is 250 to 400 ℃.
In a preferred embodiment, the first heat treatment is performed to react the portions of the first metal silicide 20' located on both sides of the gate structure with the second metal material 50, and then remove the unreacted second metal material 50, thereby obtaining a third metal silicide layer 90, as shown in fig. 9.
In another preferred embodiment, the step of forming the third metal silicide layer 90 by performing the first heat treatment to react the portions of the first metal silicide layer 20 located at both sides of the gate structure with the second metal material 50, and removing the unreacted second metal material 50 to obtain the fourth metal silicide layer 70 includes: a third metal material 80 is deposited over the gate structure and the fourth metal silicide layer 70, as shown in fig. 8; the third metal material 80 is subjected to a second heat treatment to react portions of the fourth metal silicide layer 70 located on both sides of the gate structure with the third metal material 80, and after removing the unreacted third metal material 80, a third metal silicide layer 90 is obtained, as shown in fig. 9.
In order to ensure that the lower layer in the source drain region can form a high schottky barrier, the work function of the third metal material 80 is preferably 4.3 to 5.65eV, and more preferably the third metal material 80 is selected from Al, co, ir, ni, pd, pt and Ti y Any one of them. But is not limited to the above preferred kind, and a person skilled in the art may reasonably select the third metal material 80 satisfying the above work function according to the prior art. Preferably, the temperature of the second heat treatment is 400 to 700 ℃.
From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects:
the Schottky barrier transistor has a high mobility channel, so that the on-state current of the device can be improved; the low Schottky barrier at the upper layer in the source drain region can improve the on-state current of the transistor, the high Schottky barrier at the lower layer can improve the immunity of the device to the short channel effect, and the off-state current of the transistor is reduced, so that the current switching ratio of the device is improved; and the structure of the laminated silicide in the source and drain regions is completely compatible with the current CMOS technology.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A schottky barrier transistor comprising a substrate (10) and a gate structure on the substrate (10), characterized in that the schottky barrier transistor further comprises:
a channel region on a surface of the substrate (10) corresponding to the gate structure, the channel region comprising a SiGe layer (20);
a source-drain region comprising a second metal silicide layer (60) and a third metal silicide layer (90) which are positioned at two sides of the channel region, wherein the second metal silicide layer (60) is positioned in the substrate (10), the third metal silicide layer (90) is positioned on the surface of the substrate (10) corresponding to the second metal silicide layer (60), the work function of the second metal silicide layer (60) is smaller than that of the third metal silicide layer (90),
the material for forming the second metal silicide layer (60) comprises a second metal with a work function of 2.0-4.3 eV,
the raw materials for forming the third metal silicide layer (90) comprise SiGe and a third metal, wherein the work function of the third metal is 4.3-5.65 eV, and the SiGe forming the third metal silicide layer (90) and the SiGe layer (20) in the channel region are all components of the SiGe layer formed on the surface of the substrate (10);
the substrate (10) is an SOI substrate, the SOI substrate comprises a silicon substrate, a buried oxide layer (110) and a silicon layer (120) which are sequentially stacked, the SiGe layer (20) is arranged on the surface of the silicon layer (120), the second metal silicide layer (60) is arranged in the silicon layer (120), the third metal silicide layer (90) is arranged on the surface of the silicon layer, and the thickness of the silicon layer (120) is 1-20 nm;
the schottky barrier transistor is a PMOS transistor,
the second metal silicide layer (60) is selected from HfSi x 、ZrSi x 、LaSi x 、TiSi x 、EuSi x And GdSi x Wherein x is more than or equal to 1 and less than or equal to 2;
the third metal silicide layer (90) is selected from Al 2 Si x Ge y 、Co 2 Si x Ge y 、Ir 2 Si x Ge y 、Ni 2 Si x Ge y 、Pd 2 Si x Ge y 、Pt 2 Si x Ge y And Ti is 2 Si x Ge y Wherein x is more than or equal to 1 and less than or equal to 2, and y is more than or equal to 1 and less than or equal to 2;
the potential barrier between the SiGe layer (20) and the third metal silicide layer (90) is 0.5-1 eV, and the second metal and the third metal are made of different materials.
2. The schottky barrier transistor of claim 1 wherein the channel region further comprises a cap layer disposed between the SiGe layer (20) and the gate structure, the cap layer being formed of Si and having a thickness of 2-5 nm.
3. A method of fabricating a schottky barrier transistor comprising the steps of:
s1, providing a substrate (10), and sequentially forming SiGe (20 ') on the surface of the substrate (10) and a gate structure on part of the surface of the SiGe (20 '), wherein the SiGe (20 ') is formed by adopting an epitaxial method;
s2, forming a second metal silicide layer (60) in the substrate (10) corresponding to two sides of the gate structure, and forming a third metal silicide layer (90) in the SiGe (20') corresponding to two sides of the gate structure, wherein the work function of the second metal silicide layer (60) is smaller than that of the third metal silicide layer (90),
the second metal silicide layer (60) and the third metal silicide layer (90) constitute structures in source and drain regions of the Schottky barrier transistor, and the remaining SiGe (20') constitutes a SiGe layer (20) in a channel region of the Schottky barrier transistor,
the substrate (10) is an SOI substrate, the SOI substrate comprises an oxygen burying layer (110) and a silicon layer (120) positioned on the surface of the oxygen burying layer (110), and the thickness of the silicon layer (120) is 1-20 nm;
after providing the substrate (10), the step S1 comprises the steps of:
epitaxially forming the SiGe (20') on a surface of the substrate (10);
forming a grid electrode (30) on the SiGe (20'), forming a side wall (40) covering the surface of the grid electrode (30), forming the grid electrode structure by the grid electrode (30) and the side wall (40),
the step of forming the second metal silicide layer (60) includes:
depositing a second metal material (50) on the gate structure and the SiGe (20'), the second metal material (50) having a work function of 2.0-4.3 eV;
performing a first heat treatment on the second metal material (50) to enable parts of the substrate (10) located on two sides of the gate structure to react with the second metal material (50) and remove unreacted second metal material (50) so as to obtain a second metal silicide layer (60),
-forming the third metal silicide layer (90) by said first heat treatment to react part of the SiGe (20') on both sides of the gate structure with the second metal material (50), after removing unreacted second metal material (50), to obtain a fourth metal silicide layer (70), comprising:
depositing a third metal material (80) on the gate structure and the fourth metal silicide layer (70), wherein the work function of the third metal material (80) is 4.3-5.65 eV;
performing a second heat treatment on the third metal material (80) to enable part of the fourth metal silicide layer (70) located on two sides of the gate structure to react with the third metal material (80), obtaining the third metal silicide layer (90) located on the surface of the silicon layer (120) after removing unreacted third metal material (80), wherein raw materials for forming the third metal silicide layer (90) comprise SiGe, siGe for forming the third metal silicide layer (90) and SiGe for forming the SiGe layer (20) in the channel region are all components of the SiGe layer formed on the surface of the substrate (10),
the second metal material (50) is selected from any one of Hf, zr, la, ti, eu and Gd,
the third metal material (80) is selected from Al, co, ir, ni, pd, pt and Ti y The potential barrier between the SiGe layer (20) and the third metal silicide layer (90) is 0.5-1 eV, and the second metal and the third metal are made of different materials.
4. A method of manufacturing according to claim 3, characterized in that the step of providing the substrate (10) comprises:
oxidizing the silicon layer (120), removing oxidation products to thin the silicon layer (120), and removing the oxidation products by BOE etching, wherein the thickness of the silicon layer (120) is 1-20 nm.
5. A method of manufacturing according to claim 3, characterized in that the gate electrode (30) is a stacked structure of a high-k dielectric layer and a metal gate electrode.
6. A method of manufacturing according to claim 3, characterized in that between the steps of forming the SiGe (20') and forming the gate structure, the step S1 further comprises the steps of:
and forming a cap layer on the surface of the SiGe (20'), wherein the gate structure is positioned on the surface of the cap layer, the cap layer is made of Si, and the thickness of the cap layer is 2-5 nm.
7. A method of manufacture according to claim 3, wherein the temperature of the first heat treatment is 250 to 400 ℃.
8. A method according to claim 3, characterized in that said third metal silicide layer (90) is obtained by said first heat treatment to react part of said SiGe (20') located on both sides of said gate structure with said second metal material (50) and then removing unreacted said second metal material (50).
9. A method of manufacture according to claim 3, wherein the temperature of the second heat treatment is 400-700 ℃.
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| CN1794469A (en) * | 2005-12-08 | 2006-06-28 | 北京大学 | Schockley barrier MOS transistor and its manufacturing method |
| CN102983163A (en) * | 2011-09-07 | 2013-03-20 | 中国科学院微电子研究所 | Metal-oxide -semiconductor field effect transistors (MOSFETs) capable of reducing source drain contact resistance and manufacturing method thereof |
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| CN102983163A (en) * | 2011-09-07 | 2013-03-20 | 中国科学院微电子研究所 | Metal-oxide -semiconductor field effect transistors (MOSFETs) capable of reducing source drain contact resistance and manufacturing method thereof |
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