CN1747163A - 半导体器件、引线框及其制造方法 - Google Patents

半导体器件、引线框及其制造方法 Download PDF

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CN1747163A
CN1747163A CNA2005100995720A CN200510099572A CN1747163A CN 1747163 A CN1747163 A CN 1747163A CN A2005100995720 A CNA2005100995720 A CN A2005100995720A CN 200510099572 A CN200510099572 A CN 200510099572A CN 1747163 A CN1747163 A CN 1747163A
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wire
lead
bar
semiconductor chip
lead frame
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小贺彰
福田敏行
松尾隆广
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Publication of CN1747163A publication Critical patent/CN1747163A/zh
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Abstract

一种半导体器件，将半导体芯片(1)装载在片座(2)上，用金属丝(5)连接芯片表面的电极(3)和配置在片座周围的引线(4)，用树脂(6)将半导体芯片、金属丝、以及引线的金属丝连接部分一起模压成形，并且其结构做成至少1条引线的前端部分以前端方低的方式形成阶梯部(8)，阶梯部的各级连接半导体芯片上同一或不同电极连接的多根金属丝。由于使同一引线上焊接的多根金属丝上下分离，可使连接稳定，同时还可将各引线设定成焊接1根金属丝所需的最小宽度，使其能仅按该宽度靠近半导体芯片排列。

Description

半导体器件、引线框及其制造方法
技术领域
本发明涉及半导体器件、引线框及其制造方法，尤其涉及使用引线框的集成电路的封装技术。
背景技术
近年来，作为使用引线框的多引脚半导体集成电路器件的形态，广泛采用方形扁平封装(下文称为QFP)。
图11是已有的普通QFP型半导体器件的截面图，图12是该半导体器件的丝焊部分的内部结构图。在这种QFP型半导体器件中，在片座(ダイパツド)2上装载形成集成电路的半导体芯片1，用金属丝5连接半导体芯片1的表面上形成的电极3和辐射状配置在片座2的周边的引线4的内引线4a部分，用密封树脂6将半导体芯片1、金属丝5、内引线4a模压成形后，形成树脂封装体7，并且在树脂封装体7的外部将连接内引线4a的外引线4b弯曲成鸥翼形状。片座支持件4b是将片座2保持在后文阐述的框架上的构件。
随着集成电路的高集成化和高密度化，QFP型半导体器件中一直在开展多引脚化、引线小间距化(参考例如香山晋、成濑邦彦主编的《VLSI封装技术(下)》，第165～第170页，日经股份公司BP，1993年5月31日发行)。然而，QFP型半导体器件的外形和引脚数已在业界加以标准化，因而为了保持高集成化的半导体芯片，将虽然可称为多引脚但数量有限的引脚中电源、接地电极等能共用的电极集中连接到1条内引线，从而谋求外引线少和电路稳定。图13是示出一条内引线4a连接来自多个电极3的金属丝5的状态的模式图。图13A中1条内引线4a连接2根金属丝5，图13B中1条内引线4a连接3根金属丝5。
1条引线4(具体为内引线4a)的前端部焊接多根金属丝5时，引线4的前端部由于以往将其加工成平面，必须沿引线4的宽度方向将各金属丝5平面状排列成不相互重叠，并且需要将引线4的前端部的宽度取成比焊接1根金属丝5时大。于是，为了确保该区域，必须将引线4的前端部配置成远离半导体芯片1。应连接多根金属丝5的引线4的数量越多，这种配置越显著。
另一方面，往往装载芯片规模和焊盘配置不同的多种半导体芯片1，并且共用1种引线框，因而需要限定连接多根金属丝5的引线4形成宽度大或不能限定时全部引线4形成宽度大。后一情况下，尤其必须将引线4的前端部配置成远离半导体芯片1。
然而，使引线4的前端部远离半导体芯片1的配置因长金属丝焊接技术和树脂封装技术而受制约，越是高密度化的小半导体芯片，越需要使引线4的前端部远离的配置，造成装载困难。半导体芯片的小型高密度化到达极限。
本发明使鉴于上述问题而完成的，其目的为：在同一引线连接来自半导体芯片的多根金属丝的连接结构中，实现小引线间距，紧凑且廉价地用高集成度、高密度、小型的半导体芯片构成高质量的半导体器件。
发明内容
为了解决上述课题，本发明的半导体器件，具有：半导体芯片、装载所述半导体芯片的片座、在所述片座的周围配置成前端部与片座对置的多条引线、以及连接所述半导体芯片的表面上形成的电极和所述引线的金属丝，并且将所述半导体芯片、金属丝和引线的金属丝连接部分一起用树脂模压成形，其中，至少1条所述引线的前端部分以前端方低的方式形成阶梯部，并且在所述引线的阶梯部的各级分别连接所述半导体芯片上同一或不同电极连接的多根金属丝。
根据上述组成，用阶梯使焊接在同一引线的多根金属丝的焊接部上下分离，以立体状分离配置多根金属丝。因此，各金属丝之间不接触，构成半导体芯片与引线的稳定连接。还可将各引线的宽度设定成焊接1条金属丝所需的最小宽度。换句话说，不必使连接多根金属丝的引线加大宽度，因而能将引线间距减小至极限。
这样，即便是连接多根金属丝的引线，也能排列在靠近半导体芯片的位置，因而小半导体芯片也能以短金属丝作稳定的丝焊和树脂密封成形，可实现质量极高且小型的半导体器件。又由于不必按连接的金属丝根数改变引线宽度和间距，即使芯片规模、电极配置、与多根电极连接的引线的位置不同，也能共用将片座和引线综合为一体地形成的引线框。
其结构可为：全部引线形成阶梯部，并且在至少1条所述引线的阶梯部连接多根金属丝。片座上装载的半导体芯片可为多块。其结构也可为：引线前端部的宽度不大于0.1mm，并且以相邻引线前端部中心的距离为不大于0.2mm的间隔进行排列。
本发明的半导体器件制造方法，进行：在片座上装载半导体芯片的装载工序、用金属丝连接所述半导体芯片的表面上形成的电极和在所述片座周围配置成与片座对置的多条引线的丝焊工序、以及将所述半导体芯片和金属丝和引线的金属丝连接部分一起用树脂模压成形的树脂封装工序，其中，在所述丝焊工序中，对前端部分以前端方低的方式形成阶梯部的至少1条所述引线，在所述阶梯部的各级分别连接所述半导体芯片上同一和不同电极连接的规定的多根金属丝。
丝焊工序中，通过利用丝焊法实施金属凸块，形成引线的阶梯部。
本发明的引线框，具有：上述半导体器件使用的片座和引线，并且综合为一体地形成装载半导体芯片的片座、在所述片座周围配置成前端部与片座对置的多条引线、连接所述多条引线的另一端部的框架、以及将所述片座保持在所述框架上的片座支持件，至少在一条所述引线的前端部分以前端方低的方式形成阶梯部。
本发明的引线框制造方法，该引线框具有上述半导体器件使用的片座和引线，该引线框制造方法利用蚀刻法或冲压法加工金属板，综合为一体地形成装载半导体芯片的片座、在所述片座周围配置成前端部与片座对置的多条引线、连接所述多条引线的另一端部的框架、以及将所述片座保持在所述框架上的片座支持件，并且在至少一条所述引线的前端部分以前端方低的方式形成阶梯部。
通过挤压引线的前端部，或通过对引线的前端部进行弯曲加工，或通过往垂直方向对引线的前端部进行压入，形成阶梯部。或利用刻除引线前端部的上层的蚀刻加工，或通过在引线的前端部部分设置凸部，适当形成阶梯部。
通过往垂直方向提升引线，或通过在引线上实施金属镀，或利用丝焊法实施金属凸块，适当形成凸部。
根据本发明，不拘一条引线连接的金属丝数量，总能使引线宽度和间距最小。因而，可将引线配置在较靠近半导体芯片的位置，尤其在构成使用引线框的多引脚封装半导体器件时，可形成对高集成化、高密度化的半导体芯片的短金属丝焊接，具有使金属丝线径小，并且防止金属丝在树脂封装工序中变形的极大效果。能实现高质量且小型的半导体器件。
由于不必按连接的金属丝根数改变引线宽度和间距，对芯片规模、电极配置、与多根电极连接的引线的位置不同的多种半导体芯片，能共用引线框。因此，能大批量生产多种半导体芯片可共用的引线框，质量非常高、紧凑且廉价地提供各种半导体器件。
附图说明
图1是本发明实施方式1的半导体器件的截面图。
图2A～2C是图1的半导体器件的丝焊部分的内部结构图和模式图。
图3A、图3B是用于制造图1的半导体器件的引线框的组成图。
图4A、图4B是作为图1的半导体器件的变换例的半导体器件的关键部分截面图和模式图。
图5是本发明实施方式2的半导体器件的关键部分截面图。
图6是本发明实施方式3的半导体器件的关键部分截面图。
图7是本发明实施方式4的半导体器件的关键部分截面图。
图8是本发明实施方式5的半导体器件的关键部分截面图。
图9是本发明实施方式6的半导体器件的关键部分截面图。
图10是本发明实施方式7的半导体器件的关键部分截面图。
图11是已有的普通QFP型半导体器件的截面图。
图12是图11的半导体器件的丝焊部分的内部结构图。
图13A、图13B是示出图11的结构的半导体器件中1条引线连接多根金属丝的状态的模式图。
具体实施方式
下面，参照附图说明本发明的实施方式。
实施方式1
图1是本发明实施方式1的半导体器件的截面图，图2A是该半导体器件的丝焊部分的内部结构图，图2B是该半导体器件的丝焊部分的模式图。
图1和图2所示的半导体器件中，在片座2上装载形成集成电路的半导体芯片1，用金属丝5连接半导体芯片1的表面上形成的电极3和辐射状配置在片座2的周边的引线4，用密封树脂6将半导体芯片1、金属丝5、引线4的内引线4a模压成形后，形成树脂封装体7，并且在树脂封装体7的外部将连接内引线4a的外引线4b弯曲成鸥翼形状。
此半导体器件与上述已有半导体器件的不同点是：至少1条引线4(具体为内引线4a)的前端部分以前端方低的方式形成阶梯部8，并且在各级的平坦丝焊区8a、8b分别连接金属丝5。
下面，说明上述半导体器件的制造方法。
(1)利用蚀刻法或冲压法加工金属板，制造图3A、图3B所示的引线框9。为了同时(或依次)形成多个半导体器件，引线框9按左右、上下排列多个用框架11连接与各半导体器件对应的矩形的图案10。
各图案10的结构为：将上述片座2配置在中央，框架11上连接多条引线(内引线4a、外引线4b)的外端部，并且利用片座支持件12将片座2保持在框架11上。各图案10的至少1条内引线4a的前端部形成所述阶梯部8。后文详述此引线框9，尤其详述阶梯部8。
(2)在引线框9的各图案10的片座2上装载半导体芯片1。
(3)利用丝焊法以金属丝5连接半导体芯片1的表面的电极3和内引线4a。这时，对形成阶梯部8的内引线4a引入半导体芯片1上的同一或不同电极3连接的规定的多条金属丝5，分别连接到阶梯部8的各级丝焊区8a、8b。
(4)用树脂6将半导体芯片1、金属丝5和内引线4a(即引线框架11的内侧部分)一起模压成形，形成树脂封装体7。
(5)切割各引线4之间的挡板16。最后，沿外引线4b的外端部分的切断线进行切断，分离成单件，同时还将外引线4b加工成规定的形状，从而获得半导体器件的成品。
引线框9最好采用由铜合金或铁镍合金构成的厚度在0.05mm～0.3mm范围的金属板材料。内引线4a的前端部宽度以焊接1根金属丝5所需的宽度为最小宽度。该宽度取决于金属丝5的线径，但其范围以0.03mm～0.1mm为佳。内引线4a的间距根据加工技术水平，可设定在0.08mm～0.25mm，最好设定成不大于0.2mm。
为了在内引线4a形成阶梯部8，对内引线4a的前端部从丝焊面方进行蚀刻，或进行冲压加工，将其锻塌，从而形成低于前端方的平坦丝焊区8a，并将后续于丝焊区8a的非加工部分作为平坦的丝焊区8b。此阶梯部8的形成方法不必与整个引线框9的加工方法相同，也可例如对以蚀刻加工成形的引线框9利用冲压加工使丝焊区8a形成阶梯状。
丝焊区8a与8b的阶梯高低，相差最好取为各自焊接的金属丝5不相互干扰以免发生焊接欠佳的程度。该阶梯高度取决于金属丝5的线径，但其范围以0.01mm～0.15mm为佳。考虑金属丝5之间的干扰和焊接工具与丝焊区8a、8b的阶梯高度的干扰等，丝焊区8a、8b的长度的范围以0.2mm～1.5mm为佳。
如这里所示，阶梯部8不仅形成在焊接多根金属丝5的规定的内引线4a，而且可形成在不焊接的内引线4a。如图2C所示的丝焊部分内部结构图那样，在全部内引线4a形成阶梯部8，则芯片规模、电极位置、电极3和内引线4a的布线图案不同的半导体芯片1也能连接适当的内引线4a的阶梯部8，因而可共用引线框9。
形成阶梯部8的内引线4a仅焊接1根金属丝5时，可连接丝焊区8a和8b中的任一方。然而，由于防止变形等原因，金属丝5以短的为佳，最好焊接在前端方丝焊区8a。
如图4A、图4B所示，可使阶梯部8形成3级(或3级以上)，并且各级丝焊区8a、8b、8c各自连接金属丝5。从该图4可知，即使1条内引线4a连接的金属丝5的根数比图1～图3所示的半导体器件中增多，内引线4a的宽度和间距也可与该器件中的相同。
综上所述，通过在内引线4a设置阶梯部8(丝焊区8a、8b、8c……)，1条内引线4a焊接多根金属丝5时，可立体状分离，使金属丝5之间不接触，半导体芯片1与内引线4a能稳定连接。还可使各内引线4a减小到焊接1根金属丝5所需的最小宽度、最小间距。
这样，即便是连接多根金属丝5的内引线4a，也可排列在靠近半导体芯片1的位置，对高集成化、高密度化的小半导体芯片1，可作短金属丝焊接，在减小金属丝线径或树脂封装工序中防止金属丝变形方面具有极大的效果。
又由于不必根据连接的金属丝5的根数改变内引线4a的宽度和间距，可使引线框9对芯片规模、电极3的配置、连接多个电极3的内引线4a的位置不同的多种半导体芯片1通用。
因此，能大批量生产多种半导体芯片1可共用的引线框9，质量非常高、紧凑且廉价地制造多种半导体器件。
实施方式2
图5是示出本发明实施方式2的半导体器件的丝焊部分结构的关键部分截面图。
此实施方式2的半导体器件与上述实施方式1的半导体器件的不同点是：形成内引线4a的阶梯部8时，以使用冲压模的弯曲加工形成与丝焊区8a相应的前端梯级部。
利用此方法，能抑制内引线4a的前端梯级部的灰度和宽度的偏差。实施方式1的方法中，如上文所述，从丝焊面方利用蚀刻加工或冲压加工使与丝焊区8a相应的前端梯级部厚度变薄，因而能将阶梯前后的边界部等(即内引线4a的前端方部的丝焊区8a与后端方部的丝焊区8b的边界部等)限定成较短，因而能将第2根及其后的金属丝5的长度设定得短。反之，实施方式1中，蚀刻加工时厚度控制稍微困难，冲压加工时挤压塑性形变部分的延展量控制和引线前端的斜度控制稍微困难，但实施方式2的方法具有消除该困难的优点。
引线框材料和厚度的设定、内引线前端部丝焊区宽度、长度和阶梯高的设定、应用的内引线述的设定、仅连接1根金属丝的内引线的丝焊点选择等其它一系列制造方法与实施方式1中相同。
因此，能廉价地实现优于实施方式1的高质量半导体器件。
实施方式3
图6是示出本发明实施方式3的半导体器件的丝焊部分结构的关键部分截面图。
此实施方式3的半导体器件与上述实施方式1的半导体器件的不同点是：形成内引线4a的阶梯部8时，以用冲压模往垂直方向压入的方式形成与丝焊区8a相应的前端梯级部。
利用此方法，与实施方式2相比，不仅能抑制内引线4a的梯级部的厚度和宽度的偏差，而且能将第2根及其后的金属丝5的长度设定得短。实施方式2由于用冲压模仅作弯曲加工，引线长度方向需要弯曲加工用的区域，也就是说，形成不能丝焊的倾斜部分，必须使引线加长该部分的份额，从而第2根及其后的金属丝5的长度变长。消除这问题，是实施方式3的优点。
引线框材料和厚度的设定、内引线前端部丝焊区宽度、长度和阶梯高的设定、应用的内引线述的设定、仅连接1根金属丝的内引线的丝焊点选择等其它一系列制造方法与实施方式1和实施方式2中相同。
因此，能廉价地实现优于实施方式1的高质量半导体器件。
实施方式4
图7是示出本发明实施方式4的半导体器件的丝焊部分结构的关键部分截面图。
此实施方式4的半导体器件与上述实施方式1的半导体器件的不同点是：形成内引线4a的阶梯部8时，在前端部至少确保利用丝焊法仅连接金属丝5的平坦丝焊区部8a，并且在比该部靠近外引线4b的位置形成上表面成为丝焊区8b的凸部13。
作为在内引线4a形成凸部13的方法：通过冲压加工往垂直方向提升成为丝焊区8b的部分，而留下成为丝焊区8a的平坦部。该凸部13的形成方法未必与整个引线框9的加工方法相同，也可例如对用蚀刻加工成形的引线框9利用冲压加工使成为丝焊区8b的部分鼓起。
凸部13的长度只要保证丝焊所需的平坦区即可，最好设定在0.2mm～1.0mm的范围。凸部13的高度最好形成各自焊接的金属丝5b部不相互干扰以免发生焊接欠佳的高低差。该高度取决于金属丝5b的线径，但以0.01mm～0.15mm的范围为佳。
引线框材料和厚度的设定、内引线前端部丝焊区宽度、长度和阶梯高的设定、应用的内引线述的设定、仅连接1根金属丝的内引线的丝焊点选择等其它一系列制造方法与实施方式1中相同。
因此，能廉价地实现优于实施方式1的高质量半导体器件。
实施方式5
图8是示出本发明实施方式5的半导体器件的丝焊部分结构的关键部分截面图。
此实施方式5的半导体器件与上述实施方式1的半导体器件的不同点是：形成内引线4a的阶梯部8时，在前端部至少确保利用丝焊法仅连接金属丝5的平坦丝焊区部8a，并且在比该部靠近外引线4b的位置，通过实施金属镀形成上表面成为丝焊区8b的凸部14。金属镀的材料(例如镀银或镀金)可不同于引线框9的材料(例如铁—镍合金或铜合金)。
引线框材料和厚度的设定、内引线前端部丝焊区宽度、长度和阶梯高的设定、应用的内引线述的设定、仅连接1根金属丝的内引线的丝焊点选择等其它一系列制造方法与实施方式1中相同。
因此，能廉价地实现优于实施方式1的高质量半导体器件。
实施方式6
图9是示出本发明实施方式5的半导体器件的丝焊部分结构的关键部分截面图。
此实施方式6的半导体器件与上述实施方式1的半导体器件的不同点是：形成内引线4a的阶梯部8时，在前端部至少确保利用丝焊法仅连接金属丝5的平坦丝焊区部8a，并且在比该部靠近外引线4b的位置，利用丝焊法(球焊法)形成凸部(凸块)15，并且将其上表面作为丝焊区8b。
最好在实施方式1说明的丝焊工序中进行凸部15的形成。凸部15的材料最好与用于连接电极3和内引线4a的金属丝5的材料相同，一般使用金线或铜合金线。
利用这样在丝焊工序形成凸部15的方法，不必如实施方式1～5那样，预先在引线框9的内引线4a形成凸部。由于能自由选择仅对要连接多根金属丝5形成凸部15，可仍旧使用已有类型的引线框9，进一步提高材料的共用性。
引线框材料和厚度的设定、内引线前端部丝焊区宽度、长度和阶梯高的设定、应用的内引线述的设定、仅连接1根金属丝的内引线的丝焊点选择等其它一系列制造方法与实施方式1中相同。
因此，能廉价地实现优于实施方式1的高质量半导体器件。
实施方式7
图10是本发明实施方式7的半导体器件的截面图。
此实施方式7的半导体器件中，在片座2装载多块半导体芯片1a、1b、1c，使其重叠，并且各半导体芯片1a、1b、1c的电极3连接同一的内引线4a的阶梯部8。此组成中，也存在阶梯部8，因而能取得与实施方式1～6中说明的半导体器件相同的效果。
这里叠置3级半导体芯片1a、1b、1c，但叠置2级或不少于4级时，或者不是叠置而是平面状配置时，同样能连接同一内引线4a的阶梯部8。
这里利用金属丝5将分开的半导体芯片1a、1b、1c上存在的电极3连接到同一内引线4a，但利用金属丝5将1块半导体芯片1a(或1b或1c)分别连接到同一内引线4a，或这两种连接方法的组合，也有效。
工业上的实用性
根据本发明，能用高集成度、高密度的半导体芯片，构成方形扁平封装等的多引脚半导体集成电路器件。

Claims (16)

1、一种半导体器件，包括
半导体芯片(1)、
装载所述半导体芯片的片座(2)、
在所述片座的周围配置成前端部与片座对置的多条引线(4)、以及
连接所述半导体芯片的表面上形成的电极(3)和所述引线的金属丝(5)，
并且将所述半导体芯片、金属丝和引线的金属丝连接部分一起用树脂模压成形，其特征在于，
至少1条所述引线(4)的前端部分以前端方低的方式形成阶梯部(8)，并且在所述引线(4)的阶梯部(8)的各级分别连接所述半导体芯片上同一或不同电极(3)连接的多根金属丝(5)。
2、如权利要求1中所述的半导体器件，其特征在于，
全部引线形成阶梯部，并且在至少1条所述引线的阶梯部连接多根金属丝。
3、如权利要求1中所述的半导体器件，其特征在于，
片座上装载的半导体芯片有多块。
4、如权利要求1中所述的半导体器件，其特征在于，
引线前端部的宽度不大于0.1mm，并且以相邻引线前端部中心的距离为不大于0.2mm的间隔进行排列。
5、一种半导体器件制造方法，进行
在片座(2)上装载半导体芯片(1)的装载工序、
用金属丝(5)连接所述半导体芯片的表面上形成的电极(3)和在所述片座周围配置成与片座对置的多条引线(4)的丝焊工序、以及
将所述半导体芯片和金属丝和引线的金属丝连接部分一起用树脂模压成形的树脂封装工序，其特征在于，
在所述丝焊工序中，对前端部分以前端方低的方式形成阶梯部(8)的至少1条所述引线(4)，在所述阶梯部(8)的各级分别连接所述半导体芯片上同一或不同电极(3)连接的规定的多根金属丝(5)。
6、如权利要求5中所述的半导体器件制造方法，其特征在于，
丝焊工序中，通过利用丝焊法实施金属凸块(15)，形成引线的阶梯部。
7、一种引线框，其特征在于，
该引线框(9)具有权利要求1中所述的半导体器件使用的片座和引线，并且综合为一体地形成
装载半导体芯片的片座、
在所述片座周围配置成前端部与片座对置的多条引线、
连接所述多条引线的另一端部的框架(11)、以及
将所述片座保持在所述框架上的片座支持件(12)，
并且至少在一条所述引线的前端部分以前端方低的方式形成阶梯部。
8、一种引线框制造方法，其特征在于，
该引线框具有权利要求1中所述的半导体器件使用的片座和引线，该引线框制造方法利用蚀刻法或冲压法加工金属板，并且综合为一体地形成
装载半导体芯片的片座、
在所述片座周围配置成前端部与片座对置的多条引线、
连接所述多条引线的另一端部的框架、以及
将所述片座保持在所述框架上的片座支持件，
并且在至少一条所述引线的前端部分以前端方低的方式形成阶梯部。
9、如权利要求8中所述的引线框制造方法，其特征在于，
通过挤压引线的前端部形成阶梯部。
10、如权利要求8中所述的引线框制造方法，其特征在于，
通过对引线的前端部进行弯曲加工，形成阶梯部。
11、如权利要求8中所述的引线框制造方法，其特征在于，
通过往垂直方向对引线的前端部进行压入，形成阶梯部。
12、如权利要求8中所述的引线框制造方法，其特征在于，
利用刻除引线前端部的上层的蚀刻加工，形成阶梯部。
13、如权利要求8中所述的引线框制造方法，其特征在于，
通过在引线的前端部部分设置凸部(13、14、15)，形成阶梯部。
14、如权利要求13中所述的引线框制造方法，其特征在于，
通过往垂直方向提升引线，形成凸部(13)。
15、如权利要求13中所述的引线框制造方法，其特征在于，
通过在引线上实施金属镀，形成凸部(14)。
16、如权利要求13中所述的引线框制造方法，其特征在于，
利用丝焊法实施金属凸块，形成凸部(15)。
CNA2005100995720A 2004-09-06 2005-09-06 半导体器件、引线框及其制造方法 Pending CN1747163A (zh)

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