CN1729564A - 在低－k电介质上形成具有消反射特性的盖层的方法 - Google Patents

在低－k电介质上形成具有消反射特性的盖层的方法 Download PDF

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CN1729564A
CN1729564A CNA2003801073194A CN200380107319A CN1729564A CN 1729564 A CN1729564 A CN 1729564A CN A2003801073194 A CNA2003801073194 A CN A2003801073194A CN 200380107319 A CN200380107319 A CN 200380107319A CN 1729564 A CN1729564 A CN 1729564A
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low
silicon
dielectric
rich
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CN100437971C (zh
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H·吕尔克
J·霍哈格
W·托马斯
F·毛厄斯贝格尔
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GlobalFoundries Inc
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Advanced Micro Devices Inc
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Abstract

本发明公开了一种在低－k介电层(206)上形成多层堆叠(230)的方法，其中多层堆叠(230)具有改善消反射的效果并在化学机械抛光过程中加强保护下面的低－k介电材料。多层堆叠(230)包括可以通过高效率的、不昂贵的等离子增强沉积方法来形成的以二氧化硅为基的子层(231，232，233)，其中可通过在沉积过程中改变硅烷和氧化氮的比例来调节光学特性。

Description

在低-K电介质上形成具有消反射特性的盖层的方法
技术领域
本发明一般涉及集成电路的形成，特别是涉及形成包括有嵌入到低介电常数介电材料中的金属的金属化层以增强装置性能。
背景技术
在现代集成电路中，诸如场效应晶体管沟道长度的最小特征尺寸已达深亚微米的范围，由此稳步提高了这些电路在速度和能耗方面的性能。随着单个电路元件的尺寸明显减小，由此改善诸如晶体管元件的开关速度(switching speed)，电连接单个电路元件的互连线的可用面积也减少。因此，必需减小这些互连线的尺寸以弥补可用面积的减少和每片芯片上电路元件数目的增加。在最小尺寸约为0.35μm的集成电路中，装置性能的一个限制因素是晶体管元件的开关速度所造成的信号传输延迟。由于这些晶体管元件的沟道长度现已达到0.18μm及以下，故信号传输延迟不再由场效应晶体管决定，而由于电路封装密度增加，受限于互连线的极其接近，因为线对线电容增加并且因线路横截面积减小而导致其电导率降低。如果不引入形成金属化层的新型材料，将不易弥补由于线对线电容的增加和线路电阻的增大而增大的寄生RC时间常数。
传统上，金属化层由介电层堆叠形成，包括诸如二氧化硅和/或氮化硅并以铝作为典型的金属。由于铝在较高电流密度时具有明显的电迁移现象，因此被具有明显较低电阻、较高热导率和较高抗电迁移性的铜所取代。虽然将铜做为金属化金属可明显改善装置的特性，但对于特征尺寸为0.13μm及以下的装置而言，成熟和熟知的介电材料，二氧化硅(k≈4.2)和氮化硅(k＞5)，不得不被所谓的低-k介电材料所取代以有效地降低互连线的信号传输延迟。然而，从熟知和成熟的铝/二氧化硅金属化层到低-k电介质/铜金属化层的转变仍有许多要解决的问题。
例如，诸如化学气相沉积的成熟沉积方法无法有效地沉积较大量的铜。此外，铜无法通过各向异性蚀刻过程有效地形成图形，因此采用所谓的镶嵌技术(damascene technique)来形成含铜的金属化层。一般地，在镶嵌技术中，先沉积介电层然后再形成沟槽和通孔图形，随后用诸如电镀法(electroplating)或化学镀法(electroless plating)的电镀方法(plating methods)将铜填充到沟槽和通孔中。为了可靠地填充沟槽和通孔，需要一定数量的“过度填充(overfill)”并需要随后去除过量的铜。化学机械抛光法(CMP)已被证明是一种去除过量的铜并由此又平坦化金属化层表面的可行过程技术，尽管在不过度影响下面材料层的情况下以足够高的去除速率从基片表面去除一种或多种材料是一项相当复杂的任务。
当用低-k介电材料取代熟知的二氧化硅时情况将变得更为复杂，因为低-k介电材料的性能，特别当涉及到机械稳定性时，通常明显地有别于二氧化硅的性能。由于铜极易在多种介电材料内扩散，所以在沉积铜之前通常提供一个或多个阻挡层(barrier layers)，并且这些阻挡层必须和铜一起去除以提供电绝缘的互连线和通孔。诸如钽和氮化钽的典型阻挡材料具有显著高于铜的硬度，所以至少在CMP过程的最后步骤，要选择各个过程参数以得到足够高的去除率，由此却损害了下面的软低-k介电材料。由于需要一定程度的过度抛光以使单个沟槽和导线之间可靠地相互绝缘，所以低-k介电层和铜可能发生明显的抛光，尤其当去除速率沿基片表面变化时。最终的沟槽和通孔由于其横截面积的变动而呈现出不理想的电阻变化，因而需要设定相应较宽的加工限度(process margins)。
将低-k介电层形成图形的进一步问题涉及光刻技术，因为尤其是镶嵌技术需要在可能包括高反射铜区域的低-k介电材料上形成准确定位的沟槽和通孔。因此，通常在低-k介电材料上形成消反射涂层(anti-reflective coating，ARC)以将进入ARC层上的光刻胶层中的光的背反射减至最少。
参照图1a-1c，现在说明将低-k介电材料形成图形的典型常规过程技术。在图1 a中，半导体结构100包含基片101，该基片101包括具有多个窄金属区域103和一个宽金属区域104的第一介电层102。基片101可包括多个电路元件(未显示)，其一部分或全部可能被电连接至金属区域103和104中的一个或多个。金属区域可包含任何适当的材料，诸如铝、铜、钽、钛、钨等。第一介电层102可包含任何适当的绝缘材料，并且在复杂的集成电路中，第一介电层102可包含低-k介电材料。在第一介电层102和金属区域103、104上形成蚀刻终止层105，接着形成基本上包含低-k介电材料的第二介电层106，在第二介电层106中将形成高导电的互连线和通孔。适当的低-k材料可包括含氢的碳氧化硅(SiCOH)或其它含硅的材料，诸如SiLK。其它适合的低-k材料有MSQ、HSQ等。消反射涂层107位于第二介电层106上，并在消反射涂层107上形成抗蚀剂掩模108。抗蚀剂掩模108包含开口109和110，其尺寸基本上相当于将要形成在第二介电层106中的线路和通孔的尺寸。
形成图1a所示的半导体结构100的典型过程可包括下列的步骤。在基片101上形成第一介电层102并在其中形成金属区域103、104之后，其中第一介电层102和金属区域103、104的形成可包含与后面将描述的基本上相同的过程步骤，再通过例如化学气相沉积来形成蚀刻终止层105。通常，蚀刻终止层105由低-k材料形成以便不会过度损害最终形成的绝缘层的整体特性。适当的材料有碳化硅和掺氮的碳化硅。对于低精确度的应用，蚀刻终止层105可包含氮化硅和具有相对较高k的其它介电材料。其后，依赖于所使用的低-k材料的类型，利用先进的沉积方法或旋涂技术形成第二介电层106。不论以何种方法形成第二介电层106，其机械性能一般显著不同于诸如二氧化硅的常规介电材料。在形成低-k介电层106之后形成消反射涂层107，其中调节其光学特性以便在其后的光刻步骤中将对特定波长的背反射减至最少。例如，消反射涂层107可包含富硅的氮氧化物，可通过控制在沉积过程中进入层膜107中的硅含量来调节其光学特性，通过在层膜107的沉积过程中提供特定比例的前体气体(precursor gases)以达到特定的折射率和消光系数(extinction coefficient)。另外控制层膜107的厚度以使其光学特性最终符合下面的材料层和用于形成抗蚀剂掩模108的光刻胶。在高反射的金属区域103、104之上形成沟槽和通孔时，对消反射涂层107的适当改进尤为重要。接着，在消反射涂层107上形成一层光刻胶，其中选择光刻胶的厚度和成分以符合用于曝光光刻胶和下面的消反射涂层107的波长。曝光之后，显影光刻胶以形成包含开口109和110的抗蚀剂掩模108。
图1b示意了在进一步制造阶段中的半导体结构100。在金属区域103和104之上的蚀刻终止层105、第二介电层106和消反射涂层107内分别形成开口113和114。在消反射涂层107上和开口113和114内形成例如包含钽和/或氮化钽的阻挡层111。并且，用铜112填充开口113和114，其中在开口113和114的外部也提供过量的铜。
从图1a的构造开始，进行各向异性蚀刻过程以形成在消反射涂层107、低-k介电层106和蚀刻终止层105内的开口113、114。由于这些层膜极其不同的特性，因此可选择不同的蚀刻参数以最终得到开口113、114。特别地，蚀刻终止层105具有比低-k介电层106明显较低的蚀刻速率以使蚀刻过程可靠地终止于蚀刻终止层105之上和其中，然后通过不同的蚀刻过程来蚀刻该蚀刻终止层105。在进行一次或多次清洗步骤之后，例如清洗区域103、104暴露的金属表面，通过先进的溅射沉积技术来沉积阻挡层111，其中依据层膜106的材料类型和填充入开口113、114内的金属来选择阻挡层111的适当成分。在以铜作为填充金属的硅基的层膜106中，常常使用钽/氮化钽双层作为阻挡层111。其后，当使用铜作为金属时，将铜种子层(seed layer)(未显示)溅射沉积于阻挡层111上，然后通过电化学技术沉积体铜(bulk copper)。
图1c示意了具有完整的金属化层120的半导体结构100，该完整的金属化层120包含低-k介电层106和用铜填充的沟槽113、114。如前所述，图1b所示的层膜112的过量的铜是通过CMP去除的，其中通常进行多步骤过程以有效地去除过量的铜并将结构100的表面平坦化。在去除过量的铜的过程中，位于沟槽113和114之外的阻挡层111也被去除掉，以将相邻的沟槽相互电绝缘。另外，通常具有相对较高k值的消反射涂层107被去除掉，以便不过度损害金属化层120的低-k特性。在去除阻挡层111和消反射涂层107的过程中，可能也会去除一定量的层膜106的介电材料和沟槽113、114中的铜，其中过度抛光的程度依赖于结构的类型、其在基片表面上的位置，因为去除率可能沿基片直径而变化等。在图1c中，在间隔相对较近的沟槽113处的去除率可能高于隔离沟槽114附近的基片位置处的去除率。由于低-k介电层106的机械稳定性降低，可能会因侵蚀(erosion)而产生层膜厚度的显著变化，如121所示，而最终导致沟槽113的线电阻的相应变化。如前所述，不完全去除消反射涂层107并不是好的选择，因为相对较高的k值会造成寄生RC时间常数在去除消反射涂层107最少的区域的明显变化。
因此建议在消反射涂层107形成之前先提供一层特殊的盖层(caplayer)，可以在CMP过程中保护下面的低-k介电层。然而，相应形成额外的盖层和消反射涂层增加了额外的复杂性和成本。
鉴于上述已确定的问题，因此需要一种将低-k介电材料形成图形的改进技术。
发明内容
本发明一般涉及一种形成盖层的方法，该盖层在化学机械抛光中充分保护低-k介电层，并且还允许在一个沉积室内调节其光学特性而不过度增加沉积过程的复杂性。
根据本发明的一个示意性实施例，一种方法包括通过在低-k介电层上形成二氧化硅层而在包含低-k介电材料的介电层上形成多层堆叠。此外，在形成二氧化硅层的过程中形成富硅的氮氧化物层，由此调节多层堆叠的至少一种光学特性以减少来自低-k介电层的背反射。
根据本发明的另一个示意性实施例，在低-k介电材料内形成金属区域的一种方法包括在等离子环境下在包含低-k介电材料的层膜上沉积二氧化硅基的多层膜。通过光刻形成凹槽部分(recessed portion)，其中多层膜可减少背反射。然后用金属填充凹槽部分。最后，利用化学机械抛光去除过量的金属和多层膜的一部分。
附图说明
通过参照下面的说明和附图可了解本发明，其中相同的参考数字代表相同的组件，以及其中：
图1a-1c示意了包含低-k介电层的半导体结构的横截面图，根据常规的工艺流程将该低-k介电层形成图形；
图2a-2c示意了根据本发明的示意性实施例将包含低-k介电材料的介电层形成图形期间的横截面图；以及
图3示意了一种用于等离子增强化学气相沉积(PECVD)的沉积工具，该沉积工具适于形成如图2a-2c所示的多盖层。
虽然本发明易受到许多不同的变更和其它形式的影响，但是其特定的实施例已在图中示例显示并在此给予了详细说明。然而，应了解的是，此处对特定实施例的说明并不是要限制本发明于所公开的特定形式，相反，本发明意在涵括由随附的权利要求所界定的在本发明精神和范围之内的所有变更、等效及选择。
具体实施方式
下面说明本发明的示意性实施例。为了清楚起见，本说明书并未将实际实施本发明的所有特征都作了说明。当然，应当了解，在开发任何此种实际的实施例时，必须做出许多与实施相关的决定以达到开发者的特定目标，诸如符合与系统相关和与商业相关的限制条件，而这些限制条件会随着实施的不同而有所变化。此外，应当了解，这种开发工作可能是复杂而又耗时的，然而，对从本发明的公开中获益的本领域的普通技术人员而言，不过是一种常规的工作。
现在参照附图来说明本发明。虽然图中的半导体装置的不同区域和结构具有非常准确、明显的外形与轮廓，但是本领域的技术人员知道，实际上，这些区域和结构并不象图中所示的那么准确。此外，相比于所制造的装置上的那些特征或区域的尺寸，图中所画出的种种特征和掺杂区的相对尺寸可能会被夸大或缩小。因此，附图只是用以说明与解释本发明的示意性实施例。应以相关领域的技术人员所认定的意义来理解和解释本文中的词汇与措词。本文前后一致使用的术语和措词并非暗示该术语或措词的特别的定义，也就是与本领域的技术人员理解的普通惯用的含义所不同的定义。如果一个术语或措词具有特别的含义，也就是不同于技术人员所理解的含义时，本说明书将会以定义的方式来清楚地阐明这样一个特别的定义，直接且明确地提供该术语或措词的特别的定义。
现在参考图2a-2c及图3说明本发明的示意性实施例。在图2a中，半导体结构200包括含有介电层202的基片201，该介电层202包含介电材料，诸如二氧化硅、氮化硅等的标准材料或低-k介电材料。介电层202可包括其上将形成沟槽或通孔的金属区域203。如前参考图1a-1c所述，基片201可包含多个电路元件，其一个或多个可能被电连接至金属区域203。在介电层202和金属区域203上形成蚀刻终止层205，其中蚀刻终止层205可包含任何适当的材料，该适当的材料相对于基本上包含低-k介电材料的上面的介电层206具有高蚀刻选择性。用于介电层206的适当材料包括含氢的碳氧化硅(SiCOH)、多孔的SiCOH、SiLK、多孔的SiLK、HSQ、MSQ等。在介电层206上形成多层堆叠230，其中，在一个实施例中，多层堆叠230包括基本上包含二氧化硅的第一层膜231、基本上包含富硅的氮氧化物的第二层膜232和具有明显较少量氮原子的保护层233。多层堆叠230由于其中含有的二氧化硅以及下面将要说明的形成顺序也被称为二氧化硅基的层膜。
多层堆叠230的第一层膜、第二层膜和保护层231、232和233具有各自的厚度234、235和236。多层堆叠230的光学特性取决于各层膜各自的厚度和成分。特别地，可通过相应选择其中的硅含量和氮含量来调节第二层膜232的光学特性，诸如折射率和消光系数。其中形成有开口210的光刻胶掩模208形成在多层堆叠230之上。开口210的尺寸基本上相当于将要形成在低-k介电层206内的沟槽或通孔的尺寸。
参考图2a以及图3，现在说明根据示意性实施例形成半导体结构200的工艺流程。依赖于所考虑的金属化层的类型，介电层202和金属区域203可依据熟知和成熟的技术来形成。例如，若介电层202和金属区域203代表与诸如晶体管的下面电路元件的接触部分，那么形成顺序可包括诸如沉积二氧化硅和做为接触金属的钨以获得层膜202和金属区域203的过程步骤。若介电层202代表低-k介电层，那么相应的过程步骤可包括下面谈到介电层206的形成和形成图形时将说明的类似过程。其次，可通过例如等离子增强化学气相沉积(PECVD)从适当的前体气体(precursor gases)来沉积蚀刻终止层205。
图3以简化的方式示意了PECVD工具300。沉积工具300包括处理室301，该处理室301包含连接到诸如RF发生器的电源303的等离子激发装置302。前体气体源304通过可控的阀组件305与处理室301相连。出口306与合适的装置(未显示)相连，配置该合适的装置以从处理室301中去除气体和副产品并维持处理室301内所需的压力。此外，沉积工具300包括基片架307，用于接收和支撑诸如图2a所示的基片201的基片。基片架307可包括可控的加热器308以将基片201的温度维持在特定的范围内。
在将基片201安装在基片架307之后，通过激活RF发生器303并给处理室301供应适当的前体气体和载气来在处理室301内建立等离子环境。若蚀刻终止层205基本上包含碳化硅和/或氮化的碳化硅层，那么可提供诸如3MS(三甲基硅烷)和氨的各自的前体气体。
接着，从适当的前体气体形成低-k介电层206，例如通过PECVD，因而利用如图3所示的沉积工具。例如，硅基的低-k介电材料可依据熟知的处理配方利用3MS来沉积。在其它的实施例中，可通过旋涂技术形成介电层206，从而形成例如MSQ层或HSQ层(hydrogensisquioxane，氢硅倍半氧烷)。应注意本发明并不限于低-k材料的类型并且可使用任何类型的低-k材料，而与介电层206的制造方法无关。接着，可将基片201置于诸如工具300的沉积工具内，或当通过PECVD沉积了低-k介电层206后将其保存在处理室301内。在一个特殊的实施例中，从硅烷和氧化氮(N2O)形成基本上包含二氧化硅的第一层膜231。在沉积二氧化硅的过程中，处理室301内的压力可维持在约2-4托的范围内，并且硅烷∶氧化氮的比例约在1/45∶1/55的范围内。因而，氧化氮的流速可调整至约3500-4500sccm，硅烷的流速可调整至约60-100sccm。供应到等离子激发装置302的RF电能可维持在约150-450瓦的范围内，其中基片201的温度维持在约350-450℃的范围内。在上述特定参数的范围内，可获得约为2.5-4nm/秒的沉积率，下文中也称之为低沉积率过程。由于事先可得知足够准确的沉积率，例如通过进行一次或多次的试运行，所以可通过调整沉积时间来控制层膜231的厚度234。在其它的实施例中，可利用适当测量工具(未显示)进行的原位测量来控制厚度234，诸如光耦合到处理室301的椭偏仪(ellipsometer)。
在进一步的示意性实施例中，称之为高沉积率过程，可通过下列的过程参数来获得较高的沉积率。硅烷的流速被调整至约100-400sccm，硅烷氧化氮(N2O)的比例约在1/10至1/20的范围，而其余的参数可调整至上述低沉积率过程中所指定的值。用这种参数设定可获得约10-30nm/秒的沉积率。
在形成第二层膜232之前，可进行抽吸步骤以去除先前沉积过程的残留气体和副产品。因此，压力调整到约4-8托的范围，同时以约7000-9000sccm的流速供应氮气作为载气。此外，硅烷/氧化氮的比例增加至约2-3，其中典型的硅烷流速在400-600sccm的范围内，并且相应调整氧化氮的流速。当RF电源在约300-600瓦的范围内并且基片温度基本上维持在与前述沉积步骤相同的范围内时，可获得约8-12nm/秒的沉积率。如前所示，可通过调整各层膜的各自厚度、特别是通过改变第二层膜232中的硅和氮的含量来调整多层堆叠230的光学特性。当硅烷∶氧化氮(N2O)的比例在上述指定范围内时，对于248nm的曝光波长，第二层膜232的折射率可调整至2.20-2.60且消光系数可调整至约0.80-0.90。反之，基本上包含二氧化硅的第一层膜231则呈现出相对均匀的光学特性，对于673nm的波长其折射率在约1.40-1.47的范围内，仅有轻微的变化。因此，对于根据其后进行的CMP过程的要求而选择的第一层膜231的所需厚度，多层堆叠230的消反射特性可通过控制第二层膜232的光学特性和/或厚度而适当地调节。在一些示意性实施例中，第一层膜231的厚度234在约20-120nm的范围内调节，其中对于约20-50nm的范围可使用低沉积率过程，对于约50-120nm的范围可使用高沉积率过程，而第二层膜232的厚度235调节至约30-90nm的范围。
在一个特殊的实施例中，形成在第二层膜232上的保护层233的氮浓度显著降低，特别是在其表面237，该表面237与其上形成的光刻胶层相接触。保护层233中降低的氮含量，特别是在表面237，显著地减少或甚至基本上完全避免了光刻胶和氮之间的相互作用，否则会在光刻胶显影后形成光刻胶残留物。
保护层233的形成可通过氧化氮(N2O)环境下的等离子处理，压力约为3.0-5.0托、温度约为350-450℃、利用约50-200瓦的RF功率，其中氧化氮(N2O)的流速设定在约250-600sccm。在上述指定的参数设置下，获得的保护层233的厚度236在约1-4nm的范围内，其中大部分的硅氮键被硅氧键所取代，特别是在表面237。可在沉积第二层膜232之后立即形成保护层233。
接着，将一层光刻胶沉积在多层堆叠230之上，其中选择与光刻要求相符的光刻胶的膜厚及其类型和成分。如前所述，诸如折射率和消光系数的光学特性以及多层堆叠的各个厚度234、235和236必须符合所使用的光刻胶，以便获得临界尺寸的最小变化。其后，曝光并显影光刻胶层而形成开口210，其中，在曝光期间，背反射进入邻近开口210的光刻胶区域中的光减至最少。依此方法，可减少或甚至完全避免开口210内的抗蚀剂残留物，也称为固基(footing)和聚渣(scumming)。
图2b示意了具有形成在多层堆叠230、低-k介电层206和蚀刻终止层205内的开口213的半导体结构200。在多层堆叠230上和开口213内形成阻挡层211，并在结构200上形成例如含铜的金属层212，以便基本上完全填充开口213。
可通过一系列类似参照图1b所述的各向异性蚀刻过程来形成开口213，然后通过溅射沉积来沉积阻挡层211，该阻挡层211可包括两个或多个子层，例如包含钽/氮化钽层。其后，溅射沉积一薄层种子层(未显示)，然后通过熟知的电化学沉积方法沉积体金属。
其后，通过化学机械抛光去除层膜212的过量的金属，其中也去除开口213之外的阻挡层211。在CMP过程中，也可能会部分去除多层堆叠230，其中，基本上包含二氧化硅的第一层膜231能可靠地保护下面的具有较低机械稳定性的低-k介电材料。在一个示意性实施例中，保护层233和第二层膜232基本上完全被去除。由于含氮量高而具有相对较高介电常数的第二层膜232已被去除，因此，最终所获的层内电介质(intra-layer dielectric)的整体介电常数基本上取决于低-k介电层206。此外，第一层膜231的一部分也可能被去除，以便进一步将整体介电常数减至最小。由于第一层膜231在铜CMP过程中呈现出相对较低的去除率，所以下面的层膜206的低-k介电材料被可靠地保护，即便在CMP过程中发生轻微的过程变化。因此，基本上可避免低-k介电材料的不想要的去除，由此可显著减少用金属填充的开口213的尺寸变化及其电阻率变化。
图2c示意了完成上述CMP过程之后的半导体结构200。厚度减小的二氧化硅层，由231a所示，仍形成在低-k介电层206之上，故层膜206因CMP所造成的损伤减至最少。在一个实施例中，层膜231a的厚度可减至20nm及以下，以便获得所需的层内电介质较低的总介电常数。
应注意在上述的实施例中，说明了单镶嵌处理技术，其中本发明也可应用于镶嵌技术的任何处理方案，诸如双镶嵌方法等。
由此，根据本发明提供了用于将低-k电介质形成图形的多层堆叠，其中多层堆叠优选具有高生产率的相对不昂贵的等离子增强沉积方法原位形成，例如每小时可处理80个基片或更多，其中在去除过量的金属的CMP过程期间可有效地保护低-k介电材料，并且同时可获得有效的消反射效果，从而可将低-k介电材料形成图形而基本上不会造成“固基和聚渣”结果。由于在CMP过程中有效地保护了低-k介电层，所以可显著降低对材料的损伤，特别是在包含高密度间隔结构的区域中。因此，相应金属结构的薄层电阻的波动也显著降低。在CMP过程期间通过减薄多层堆叠，可将介电常数的有效值保持在极低，而可基本上避免对寄生RC时间常数的有害影响。
上面所公开的特定的实施例仅仅用于示意，因为可以用不同而又等效的方式来修改和实施本发明，而这些方式对于已从本说明中获益的本领域的技术人员而言是显而易见的。例如，上面提出的过程步骤可以用不同的顺序来进行。另外，除了下面的权利要求中说明的之外，并不欲对其中所示的构建或设计的细节作限制。因此，很明显，可以改变或修改上面所公开的特定的实施例，而所有此等变化都被认为是在本发明的精神和范围之内。因此，在此寻求如下面的权利要求的保护。

Claims (18)

1.一种方法，包括：
通过在低-k介电层上形成二氧化硅层231而在包含低-k介电材料的介电层206上形成多层堆叠230；以及
在形成所述二氧化硅层期间形成富硅的氮氧化物层232，由此调节所述多层堆叠230的至少一种光学特性以减少来自所述低-k介电层的背反射。
2.如权利要求1所述的方法，其中用硅烷沉积所述二氧化硅层231。
3.如权利要求1所述的方法，其中在形成所述二氧化硅层231之后通过改变沉积气体环境来形成所述富硅的氮氧化物层232。
4.如权利要求1所述的方法，其中形成在所述介电层206上的所述二氧化硅层231的厚度在约20-120nm的范围内。
5.如权利要求1所述的方法，其中所述富硅的氮氧化物层232的厚度在约30-90nm的范围内。
6.如权利要求1所述的方法，其中通过改变所述富硅的氮氧化物层232内的硅含量来调节所述光学特性。
7.如权利要求6所述的方法，其中通过调节沉积气体环境中的硅烷/氧化氮(N2O)比例来改变所述硅含量。
8.如权利要求1所述的方法，进一步包括在所述富硅的氮氧化物层232的表面区域形成耗氮的保护层233。
9.如权利要求8所述的方法，其中通过暴露于氧化氮(N2O)等离子环境来形成所述保护层233。
10.如权利要求9所述的方法，其中通过在沉积所述富硅的氮氧化物层232期间中断硅烷的供应来建立所述氧化氮(N2O)等离子环境。
11.如权利要求8所述的方法，其中所述保护层233的厚度在约1-5nm的范围内。
12.如权利要求1所述的方法，进一步包括在所述富硅的氮氧化物层232上形成抗蚀剂掩模208。
13.如权利要求12所述的方法，进一步包括用所述抗蚀剂掩模208将所述介电层206形成图形而在所述介电层206内形成凹槽。
14.一种在低-k介电材料中形成金属区域的方法，所述方法包括：
在等离子环境下在包含所述低-k介电材料的层膜206上沉积二氧化硅基的多层膜230，同时控制所述二氧化硅基的多层膜的光学特性；
形成凹槽部分213，其中所述多层膜230减少对于一种特定波长的背反射；
用金属212填充所述凹槽部分；以及
通过化学机械抛光去除过量的金属和所述多层膜的一部分。
15.如权利要求14所述的方法，其中所述二氧化硅基的多层膜230至少部分从硅烷沉积。
16.如权利要求14所述的方法，其中通过在形成所述二氧化硅基的多层膜230期间改变沉积气体环境来在多层膜230中形成富硅的氮氧化物层232。
17.如权利要求14所述的方法，其中所述富硅的氮氧化物层232的厚度在约30-90nm的范围内。
18.如权利要求16所述的方法，其中通过改变所述富硅的氮氧化物层232内的硅含量来调节所述光学特性。
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