TWI349307B - Method of forming a cap layer having anti-reflective characteristics on top of a low-k dielectric - Google Patents
Method of forming a cap layer having anti-reflective characteristics on top of a low-k dielectricInfo
- Publication number
- TWI349307B TWI349307B TW092133968A TW92133968A TWI349307B TW I349307 B TWI349307 B TW I349307B TW 092133968 A TW092133968 A TW 092133968A TW 92133968 A TW92133968 A TW 92133968A TW I349307 B TWI349307 B TW I349307B
- Authority
- TW
- Taiwan
- Prior art keywords
- dielectric
- forming
- low
- cap layer
- reflective characteristics
- Prior art date
Links
- 230000003667 anti-reflective effect Effects 0.000 title 1
Classifications
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- H—ELECTRICITY
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
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- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L21/314—Inorganic layers
- H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/7684—Smoothing; Planarisation
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/948—Radiation resist
- Y10S438/952—Utilizing antireflective layer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10260619A DE10260619B4 (de) | 2002-12-23 | 2002-12-23 | Verfahren zur Herstellung einer Deckschicht mit antireflektierenden Eigenschaften auf einem Dielektrikum mit kleinem ε |
US10/463,910 US7030044B2 (en) | 2002-12-23 | 2003-06-16 | Method of forming a cap layer having anti-reflective characteristics on top of a low-k dielectric |
Publications (2)
Publication Number | Publication Date |
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TW200416881A TW200416881A (en) | 2004-09-01 |
TWI349307B true TWI349307B (en) | 2011-09-21 |
Family
ID=32519313
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW092133968A TWI349307B (en) | 2002-12-23 | 2003-12-03 | Method of forming a cap layer having anti-reflective characteristics on top of a low-k dielectric |
Country Status (4)
Country | Link |
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US (1) | US7030044B2 (zh) |
CN (1) | CN100437971C (zh) |
DE (1) | DE10260619B4 (zh) |
TW (1) | TWI349307B (zh) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
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DE102006046364A1 (de) * | 2006-09-29 | 2008-04-03 | Advanced Micro Devices, Inc., Sunnyvale | ARC-Schicht mit geringerer Neigung zum Ablösen und Verfahren zur Herstellung derselben |
KR100790452B1 (ko) * | 2006-12-28 | 2008-01-03 | 주식회사 하이닉스반도체 | 다마신 공정을 이용한 반도체 소자의 다층 금속배선형성방법 |
US7704885B2 (en) * | 2007-05-24 | 2010-04-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method for fabricating the same |
US20080299747A1 (en) * | 2007-05-30 | 2008-12-04 | Asm Japan K.K. | Method for forming amorphouse silicon film by plasma cvd |
US8618663B2 (en) | 2007-09-20 | 2013-12-31 | International Business Machines Corporation | Patternable dielectric film structure with improved lithography and method of fabricating same |
US8084862B2 (en) * | 2007-09-20 | 2011-12-27 | International Business Machines Corporation | Interconnect structures with patternable low-k dielectrics and method of fabricating same |
US7709370B2 (en) * | 2007-09-20 | 2010-05-04 | International Business Machines Corporation | Spin-on antireflective coating for integration of patternable dielectric materials and interconnect structures |
US8048813B2 (en) * | 2008-12-01 | 2011-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of reducing delamination in the fabrication of small-pitch devices |
JP2010171064A (ja) * | 2009-01-20 | 2010-08-05 | Panasonic Corp | 半導体装置及びその製造方法 |
US8575019B2 (en) * | 2010-09-30 | 2013-11-05 | Institute of Microelectronics, Chinese Academy of Sciences | Metal interconnection structure and method for forming metal interlayer via and metal interconnection line |
US8629559B2 (en) | 2012-02-09 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stress reduction apparatus with an inverted cup-shaped layer |
JP6134727B2 (ja) | 2013-11-08 | 2017-05-24 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
CN104952697B (zh) * | 2014-03-25 | 2018-03-27 | 中芯国际集成电路制造(上海)有限公司 | 一种mim结构的制备方法 |
US9627215B1 (en) * | 2015-09-25 | 2017-04-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for interconnection |
US20190157213A1 (en) | 2017-11-20 | 2019-05-23 | Globalfoundries Inc. | Semiconductor structure with substantially straight contact profile |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
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US6380096B2 (en) * | 1998-07-09 | 2002-04-30 | Applied Materials, Inc. | In-situ integrated oxide etch process particularly useful for copper dual damascene |
US6156640A (en) * | 1998-07-14 | 2000-12-05 | United Microelectronics Corp. | Damascene process with anti-reflection coating |
US6103456A (en) | 1998-07-22 | 2000-08-15 | Siemens Aktiengesellschaft | Prevention of photoresist poisoning from dielectric antireflective coating in semiconductor fabrication |
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-
2002
- 2002-12-23 DE DE10260619A patent/DE10260619B4/de not_active Expired - Fee Related
-
2003
- 2003-06-16 US US10/463,910 patent/US7030044B2/en not_active Expired - Fee Related
- 2003-11-06 CN CNB2003801073194A patent/CN100437971C/zh not_active Expired - Fee Related
- 2003-12-03 TW TW092133968A patent/TWI349307B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
DE10260619A1 (de) | 2004-07-15 |
US7030044B2 (en) | 2006-04-18 |
CN100437971C (zh) | 2008-11-26 |
TW200416881A (en) | 2004-09-01 |
CN1729564A (zh) | 2006-02-01 |
US20040121621A1 (en) | 2004-06-24 |
DE10260619B4 (de) | 2011-02-24 |
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