CN1729538A - 磁阻式随机存取存储器技术中改善磁堆栈表面粗糙度的双层化学机械抛光方法 - Google Patents
磁阻式随机存取存储器技术中改善磁堆栈表面粗糙度的双层化学机械抛光方法 Download PDFInfo
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Abstract
本发明公开了一种用以制造磁阻式随机存取存储器(MRAM)单元的方法,其可解决因隧道接合层与磁性层间界面粗糙而产生的尼尔耦合问题。所述方法包含了在导体上沉积第一与第二阻障层,其中该第一阻障层的抛光速率与该第二阻障层的抛光速率不同;接着利用化学机械抛光(CMP)方式本质上移除该第二阻障层,而留下非常平滑且均匀的第一阻障层。当接着在经抛光的第一阻障层上形成磁性堆栈时,界面粗糙度便不会转移至该隧道接合层,因此不会产生磁化改变。
Description
技术领域
本发明主要涉及磁阻式随机存取存储器(MRAM)单元的制造,特别地,本发明涉及一种利用双层化学机械抛光(CMP)制程以改善磁性层间界面粗糙度的MRAM单元的制造方法。
背景技术
相较于传统的动态随机存取(DRAM)与闪速存储(FLASH)存储器,磁阻式随机存取存储器(Magnetoresistive Random Access Memory,MRAM)单元具有非易失性、可封装为三维单元、低功率消耗、制程简单及便宜等优点,MRAM的结构包括多个存储器单元、或存储器单元数组以及多个数字(digit)与位线交叉点;一般所使用的MRAM单元是由一磁性隧道接合(MagneticTunnel Junction,MTJ)、绝缘晶体管、以及数字与位线交叉点所构成,交叉点堆栈将该绝缘晶体管连接至该MTJ装置、连接至该位线、以及连接至用于产生部分磁场以编程该MRAM单元的该数字线。
MRAM是利用铁磁材料的磁化相对取向来存储信息,磁阻式隧道接合装置需要平滑的隧道阻障(tunnel barrier)以呈现最佳的性能;表面粗糙度将改变磁化相对取向,磁化相对取向的此一改变(corruption)即为熟知的“尼尔耦合(Neel coupling)”,且为界面表面粗糙度所导致的残余磁性,如图1所示。粗糙的隧道阻障会诱生尼尔耦合而使该磁阻式装置产生切换磁场偏移,降低了在存储器数组中的该装置的操作容限(operatingmargin);此外,若隧道接合的厚度是落在表面粗糙度的尺度范围内时,在磁性堆栈沉积期间则可能经由该隧道接合而产生金属短路。实际上,尽管在沉积该磁性隧道接合金属堆栈之前,先利用化学机械抛光(CMP)处理基板,仍会产生这样的粗糙度。
在CMP后的平滑度与阻障层所使用的材料类型有关,在此处,所谓的阻障层是与此层至接线导体金属污染的扩散阻值(diffusion resistance)有关,其使此阻障层的功能与该装置电子阻障层得以有所区别。此阻障层常用的一种材料是氮化钽(TaN),其它常用的材料则为钌(Ru)、钽(Ta)与氮化钛(TiN)等单一膜层,或是由上述材料组合而成的膜层,以产生平滑的表面,因而减少尼尔耦合的有害效应。
在该金属堆栈下方的缓冲层的一个实际应用是,在该装置图案化(patterning)期间必须移除该缓冲层。然举例而言,由于对下方介电材料、或是对磁阻装置下方的导线层中所使用的曝露铜的高度选择性,因而一般皆难以蚀刻氮化钛;此外,亦难以均匀抛光一薄金属层以在晶圆表面上产生既平滑、而残余厚度又均匀的表面。
因此,在此领域中仍需要一种可以降低此一表面粗糙度的MRAM单元制造方法,以消除上述的尼尔耦合与金属短路等问题;在此领域中亦需要一种在降低残余金属厚度的不均匀性时仍可提供平滑表面的制程。
发明内容
经由利用本发明即可克服上述问题。本发明是直接与一种制造磁阻式随机存取存储器单元的制作方法有关,该方法包含下列步骤:一种用以制造一磁阻式随机存取存储器单元的方法,包含下列步骤:提供一半导体基板,其包含至少一导体,该导体是嵌埋于一介电材料中,所述导体的上表面与所述介电材料的上表面共面;在所述导体与所述介电材料上沉积一第一材料;在所述第一材料上沉积一第二材料,其中所述第二材料的抛光速率与所述第一材料不同;利用化学机械抛光方式实质上移除所述第二材料;沉积一第一磁性层、一非磁性隧道接合阻障层与一第二磁性层;以及利用光显影制程图案化所述第一材料、所述第一磁性层、所述非磁性隧道接合阻障层与所述第二磁性层。
附图说明
本发明的新颖特征以及本发明的组件特性特别于附录的权利要求书中加以说明,附图仅为说明之用而非以实际尺度绘制;此外,在附图中相同的附图标记表示相似的特征。而关于本发明本身的组织结构与操作方法,皆可参考下述详细说明与伴随的参考附图而被了解,其中:
图1a至图1b为一部份制造完成的MRAM单元截面示意图,其说明了由于界面粗糙度所产生的相对磁化取向的改变;
图2a至图2e说明了一种已知的MRAM单元形成方法;
图3a至图3d说明了根据本发明一较佳实施例的一种MRAM单元形成方法。
具体实施方式
本发明将通过参考附图而加以说明;在附图中利用简单的方式显示并示意说明了不同的结构构想,以更详细地说明本发明,举例而言,所述附图并不代表实际尺度;此外,附图中以矩形为例说明了不同构想的结构的垂直截面,然而本领域的技术人员足可了解实际结构的较细部特征,同时,本发明并不受限于任何特定形状的结构。
图1a表示一部份制造完成的MRAM单元,其说明了由于界面粗糙度所产生的相对磁化取向的改变。详细而言,图1a显示一部份制造完成的MRAM单元,该MRAM单元包含形成该MRAM单元下电极的非磁性导体2,还包含了阻障层3、固定磁性层4、非磁形隧道阻障层5与自由磁性层6;而该隧道阻障层5表面则常产生界面粗糙7的问题。由此一表面粗糙度对磁化相对取向造成的改变(corruption)即为熟知的“尼尔耦合(Neel coupling)”,且其导致与主要磁矩(Dominant Magnetic Moment)方向不同的残余磁矩(Remnant Magnetic Moment),如图1b所示。此一尼尔耦合效应产生了该磁阻式装置的切换磁场偏移,而降低了在存储器阵列中的该装置的操作容限(operating margin)。
尽管在沉积该磁性隧道接合金属堆栈之前,先利用化学机械抛光(CMP)处理基板,仍会产生这样的界面粗糙度。图2a至图2e说明了一种磁性隧道接合金属堆栈的典型制程;图2a说明一部份制造完成金属堆栈,其中介电层10已图案化(patterned)并蚀刻(etched)而形成沟渠,以衬材11作为所述沟渠的衬层后再沉积导电性材料12于其中;一般而言,传导性材料12为铜,而衬材11为氮化钽(TaN)。
图2b说明了在以化学机械抛光方式移除多余的导电性材料12与衬材11后所形成的部分制造完成的金属堆栈;在图2c中,在介电材料10与导体12上全面沉积一阻障层13,一般的阻障层13为氮化钽(TaN),且一般沉积厚度为500。
接着利用CMP处理使阻障层13变得平滑,以提供磁阻式金属堆栈沉积的一平滑表面;然而,不均匀的抛光速率经常导致剩余阻障层13的厚度变化,如图2d所示。在接下来蚀刻阻障层13时,阻障层13的某些部分会因而蚀刻不足而导致导体间短路,而阻障层13的其它部分则因过度蚀刻而破坏了下方的界电层10。
从图2e即可了解所述问题,其表示在蚀刻阻障层13、沉积剩余的金属堆栈层(总称为膜层15)、以光显影方式而利用金属罩幕16来蚀刻罩幕16暴露区域中的阻障层13与其它金属堆栈层15后所形成的部分制造完成的MRAM。在图2e所示的部分制造完成的MRAM的区域a中,CMP后的阻障层13太厚,因此无法蚀刻完全,而剩下会形成导体间短路的阻障层13a;在图2e所示的区域b中,CMP厚的阻障层13则太薄,因此会被过度蚀刻而导致介电材料10自导体间被移除。此外,经抛光的导体12的表面粗糙度会转移至该隧道阻障层与所述磁性层间的界面,导致图1所示的界面粗糙7。
通过使用本发明的方法即可减轻与导体与阻障层抛光相关的上述问题。图3a至图3d说明了本发明的一项实施例;在图3a中,导体112已形成于介电材料110中,而在导体112与介电材料110间,一般皆沉积一衬材111;在通过CMP方式将导体112平面化之后,即全面性沉积一第一阻障层113,并接着在第一阻障层113上全面沉积一第二阻障层114。
第一阻障层113最好是由与第二阻障层114不同的材料所形成;较佳为,第一阻障层113的抛光速率明显比第二阻障层114更低,以形成关于第一阻障层113的一抛光选择性。换言之,第一阻障层113的抛光速率最好是每分钟200至300,而第二阻障层114的抛光率最好是每分钟800至1200,因而形成约1∶4的抛光选择性。
同样应对第一阻障层113的材料加以选择以于抛光时获得非常平滑的表面;在一较佳实施例中,第一阻障层113是氮化钽(TaN),而第二阻障层114是钽(Ta);在另一较佳实施例中,第一阻障层113可为通过化学气相沉积(CVD)方式所沉积而得的氮化钛(TiN),而第二阻障层114则为由物理气相沉积(PVD)沉积而成的氮化钛(TiN)。
利用较佳的CMP条件来达成下述的不同抛光速率:向下力约1至5psi、载台旋转速度约30至80rpm、以及载体旋转速度约30至80rpm;且可使用如SubaIVTM上的IC1000TM、或IC1000TMk型沟槽上的IC1000TM等型号的抛光垫(Rodel,Inc.所提供的产品型号)以及商用的硅研磨浆料。
在图3c中,利用CMP方式抛光并本质上移除第二阻障层114,以暴露第一阻障层113并于第一阻障层113上产生非常平滑的一表面;而在遗留一部份的第一阻障层113时,最好是完全移除第二阻障层114。在图3d中,金属堆栈层115是沉积在阻障层113上,且利用光显影方式来移除由该金属罩幕116所暴露区域中的金属堆栈115与阻障层113。由于阻障层113已被均匀抛光,因此不会产生阻障层113蚀刻不足而导致导体112间短路的区域,亦不会产生阻障层113过度蚀刻而导致介电材料110过度被移除的区域。此外,由于阻障层113已被抛光地非常均匀,因此在金属堆栈115中的隧道阻障层与磁性层间的界面处便不会出现界面粗糙,藉以消除上述的尼尔耦合的问题。
本发明已结合一较佳实施例与其它替代实施例而加以说明,本发明可由本领域的技术人员施以修饰,并不脱离本发明与如附权利要求所述的保护范围。
附图标记说明
2 非磁性导体
3 阻障层
4 固定磁性层
5 非磁性隧道阻障层
6 自由磁性层
7 界面粗糙
Dominant Magnetic Moment 主要磁矩
Remnant Magnetic Moment 残余磁矩
10 介电质
10b
11 衬材
12 导电性材料
13 阻障层
13b 阻障层
15 金属堆栈层
16 金属罩幕
110 介电材料
111 衬材
112 导体
113 第一阻障层
114 第二阻障层
115 金属堆栈层
116 金属罩幕
Claims (10)
1.一种用以制造一磁阻式随机存取存储器单元的方法,包含下列步骤:
提供一半导体基板,其包含至少一导体,该导体是嵌埋于一介电材料中,所述导体的上表面与所述介电材料的上表面共面;
在所述导体与所述介电材料上沉积一第一材料;
在所述第一材料上沉积一第二材料,其中所述第二材料的抛光速率与所述第一材料不同;
利用化学机械抛光方式实质上移除所述第二材料;
沉积一第一磁性层、一非磁性隧道接合阻障层与一第二磁性层;以及
利用光显影制程图案化所述第一材料、所述第一磁性层、所述非磁性隧道接合阻障层与所述第二磁性层。
2.如权利要求1所述的方法,其中所述第一材料是氮化钽,而所述第二材料是钽。
3.如权利要求1所述的方法,其中所述第一材料是氮化钽且以一化学气相沉积制程沉积而成,而所述第二材料是氮化钛且以一物理气相沉积制程沉积而成。
4.如权利要求1所述的方法,其中所述导体是由铜形成。
5.如权利要求1所述的方法,其中所述基板还包含一衬材,其位于所述导体与所述介电材料之间。
6.如权利要求1所述的方法,其中所述第二材料是通过化学机械抛光方式移除,其移除速率约为所述第一材料的移除速率的4倍。
7.如权利要求1所述的方法,其中所述化学机械抛光方式是以向下力约1~5psi、载台旋转速度约30~80rpm、以及载体旋转速度约30~80rpm的方式实施。
8.如权利要求1所述的方法,其中所述第二材料是通过化学机械抛光方式移除,而其速率为每分钟约800~1200。
9.如权利要求1所述的方法,其中所述第一材料的一部份也同样由所述化学机械抛光方式移除。
10.如权利要求9所述的方法,其中所述第一材料是通过化学机械抛光方式移除,而其速率为每分钟约200~300。
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US10/289,488 US6743642B2 (en) | 2002-11-06 | 2002-11-06 | Bilayer CMP process to improve surface roughness of magnetic stack in MRAM technology |
US10/289,488 | 2002-11-06 |
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US (1) | US6743642B2 (zh) |
EP (1) | EP1559107B1 (zh) |
KR (1) | KR100694566B1 (zh) |
CN (1) | CN1729538A (zh) |
DE (1) | DE60311131T2 (zh) |
TW (1) | TWI231562B (zh) |
WO (1) | WO2004042735A1 (zh) |
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CN109216541A (zh) * | 2017-06-30 | 2019-01-15 | 中电海康集团有限公司 | Mram与其的制作方法 |
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2002
- 2002-11-06 US US10/289,488 patent/US6743642B2/en not_active Expired - Fee Related
-
2003
- 2003-10-29 TW TW092130147A patent/TWI231562B/zh not_active IP Right Cessation
- 2003-11-05 DE DE60311131T patent/DE60311131T2/de not_active Expired - Fee Related
- 2003-11-05 EP EP03810441A patent/EP1559107B1/en not_active Expired - Fee Related
- 2003-11-05 WO PCT/EP2003/012353 patent/WO2004042735A1/en active IP Right Grant
- 2003-11-05 KR KR1020057008075A patent/KR100694566B1/ko not_active IP Right Cessation
- 2003-11-05 CN CNA2003801028273A patent/CN1729538A/zh active Pending
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CN104050976B (zh) * | 2013-03-12 | 2018-06-05 | 希捷科技有限公司 | 用于化学-机械抛光的方法和装置 |
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CN109844972B (zh) * | 2016-10-14 | 2023-09-01 | 应用材料公司 | 形成用于沉积磁隧道结的极平滑底电极表面的方法 |
CN109216541A (zh) * | 2017-06-30 | 2019-01-15 | 中电海康集团有限公司 | Mram与其的制作方法 |
CN109216541B (zh) * | 2017-06-30 | 2022-05-17 | 中电海康集团有限公司 | Mram与其的制作方法 |
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TW200414400A (en) | 2004-08-01 |
EP1559107B1 (en) | 2007-01-10 |
US20040087038A1 (en) | 2004-05-06 |
US6743642B2 (en) | 2004-06-01 |
KR20050088997A (ko) | 2005-09-07 |
KR100694566B1 (ko) | 2007-03-13 |
WO2004042735A1 (en) | 2004-05-21 |
EP1559107A1 (en) | 2005-08-03 |
DE60311131D1 (de) | 2007-02-22 |
DE60311131T2 (de) | 2007-10-18 |
TWI231562B (en) | 2005-04-21 |
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