CN1711639A - 折叠的柔性无接合引线的多芯片功率封装 - Google Patents

折叠的柔性无接合引线的多芯片功率封装 Download PDF

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CN1711639A
CN1711639A CNA2003801030201A CN200380103020A CN1711639A CN 1711639 A CN1711639 A CN 1711639A CN A2003801030201 A CNA2003801030201 A CN A2003801030201A CN 200380103020 A CN200380103020 A CN 200380103020A CN 1711639 A CN1711639 A CN 1711639A
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S·哈奎
G·布伦宁
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Adeia Semiconductor Technologies LLC
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Abstract

一种多芯片无引线接合的集成电路和功率管芯封装基于折叠的单层柔性电路。此封装由倒装接合到图形化的柔性衬底的金属钉头凸点功率管芯以及IC组成。柔性衬底的延伸部分被折叠并附着到管芯的背面，以便进行电接触和/或热接触。I/O引脚沿着封装的外围，以便进行标准的SMT安装，散热器同时被附着到封装的二侧，以便进行双面冷却。

Description

折叠的柔性无接合引线的多芯片功率封装
本发明涉及到集成功率模块，确切地说是涉及到用于大功率密度的折叠的柔性无接合引线的多芯片功率模块。诸如微处理器、汽车电子产品、以及通信所用调压器之类的要求大功率转换的应用，已经引起了以更低的成本来获得更高的功率密度的倾向。因此，为了满足将来的功率密度要求，就要求集成功率模块的解决方案而不是传统的分立解决方案。但模块形式的功率电子元件(例如器件、IC、无源元件等)的集成由于模块中存在各种各样的材料而被复杂化。
仅仅在最近才出现了二种市售的用于DC-DC功率转换的现有技术多芯片功率封装，提供了一种集成系统解决方案。用于调压器的第一种市售封装涉及到采用球网格阵列(BGA)技术的封装结构。采用BGA技术的模块，将例如多层印刷电路板(PCB)衬底上的二个金属氧化物半导体场效应晶体管(MOSFET)、一个驱动器芯片、以及一些无源元件安置在11mm×11mm的小的占地面积中。图1A是这种封装101的局部剖面，它包括多层PCB 104上的MOSFET 102以及无源元件103。在封装101内部，用引线接合105，形成到MOSFET 102的互连，且铜轨线106被连接到封装101背面上的BGA焊料凸点107，以便附着PCB。利用多层PCB 104的铜层来对BGA焊料凸点107进行连接。模塑料108填充了封装101。封装的厚度为3mm或以上。
第二种市售封装在10mm×10mm的区域内包含MOSFET和IC，提供了微处理器用调压器的一种集成解决方案。此封装的设计基础是采用诸如宾州West Chester的Amkor Technology公司的MicroLeadFrameTH(MLF)技术之类的腐蚀到衬底中的引线框。图1B是采用MLF的封装109，管芯附着材料112被安装到暴露的管芯叶片113。用引线接合114和115来得到封装内部的器件互连。铜引线框116上的接触(未示出)被一直引到其上安装封装109的PCB。模塑料117填充了封装109。此封装的厚度为0.9mm或以上。
功率MOSFET管芯包含3个端子(栅、源、以及漏)，因而在封装层面处仅仅需要少量端子连接。但诸如图1A和图1B之类的多芯片解决方案分别使用了诸如132焊料凸点BGA和68引线MLF之类的标准封装。图2A示出了第二种市售封装的68引线MLF引脚连接和线路板布局设计。在图2A中，MLF封装201包含分裂的引线框202和MLF引脚203。在图2B中，焊料凸点BGA封装204具有BGA焊料球阵列205。如可以看到的那样，确切地说是从图2A和2B可见，功率器件的这些标准IC封装导致了大量的连接冗余。而且，这些设计已经达到了线路板布局的间距要求极限。例如，采用MLF技术的市售封装的引线连接要求0.5mm的间距，这对于在厚度大于2oz的任何铜平面上进行图形来说是不可能的。而且，这些封装的复杂的引线连接和紧密的间距要求也使板上的热通道设计复杂化，而板上的热通道设计对于适当的热安排是很重要的。
二种目前可得到的市售封装都采用每个器件的多重引线接合以及IC互连来降低引线接合的高电阻效应。但加入更多的平行引线来降低电阻最终达到了极限(2-3mΩ)，且工艺变得非常昂贵。
目前有一些方面可以对市售封装的设计进行改善。模块的结构可以被适配成提供更好的热安排。模块可以被制作得更薄。更多的器件可以被容纳。提供多个引线接合来降低电阻的代价能够被降低或避免。若引脚连接或引线的数目被减少，则能够简化封装的装配。
因此，本发明的目的是改进传热、减小多芯片功率模块的厚度、在功率模块封装内允许更高的功能集成、消除引线接合、使设计能够无引线、以及简化I/O引脚连接。
当考虑本发明的下列详细描述时，本发明的这些和其它的目的将变得显而易见。
因此，本发明提供了一种电子装配件或模块，它包括基于折叠的单层柔性电路的无引线框的多芯片半导体封装。倒装芯片钉头凸点(studbump)半导体功率管芯以及IC被附着到图形化的柔性衬底；柔性衬底的延伸部分被折叠，并被附着到管芯的背面，以便电接触和热接触。整个封装被注塑，仅仅柔性衬底底部处的铜接触焊盘被暴露，以便进行到任何线路板的标准表面安装附着。
倒装芯片钉头凸点半导体管芯是这样一种管芯，其中，通过管芯表面上的导电“凸点”，管芯被电连接到封装载体，致使封装载体提供从管芯到封装外部的连接。此封装载体例如可以是衬底或引线框。
在本发明中，钉头凸点为器件连接提供了很短的或低阻(小于1mΩ)通路。而且，具有钉头凸点的器件的封装电感与引线接合的1nH相比，能够被降低到0.1nH。因此，在高频应用中，本发明的封装产生的噪声显著地低于现有技术解决方案的噪声。
本发明较之现有解决方案显著地改善了热安排。封装中的器件被附着到连续柔性的衬底。与分裂引线框(图2A所示MLF模块)不同，安装在连续柔性的衬底上的各个器件产生的热具有更宽广的散热面积。
本发明还由于其三维封装结构而能够双面冷却。功率MOSFET在管芯背面上具有漏连接。在常规的封装方法(例如BGA和MLF封装)中，管芯面向上被附着在衬底上，以便能够通过漏焊盘散热。用来附着源和栅焊盘(在管芯的顶面上)的引线接合仅仅提供了从管芯顶侧取出热量的有限沟道。在本发明的一个实施方案中，器件被面朝下(倒装芯片)置于在源和栅上具有金的金属凸点的衬底上，从而提供更迅速的到线路板的散热路径。柔性的衬底还被折叠和附着到漏接触，从而增加了另一到衬底的散热沟道。由于其三维构造，此封装在非常小的板面积内提供了改进的从器件二侧的散热。散热器可以被附着到此封装的任何一侧或二侧。同时，与常规引线接合封装相比，倒装芯片钉头凸点提供了更短的互连，从而降低了电阻发热以及寄生噪声。
具有其倒装芯片凸点器件的本发明的结构，提供了比目前可得到的市售封装薄得多的多芯片功率模块封装。常规功率模块的厚度主要决定于引线接合互连的环路高度。利用倒装芯片凸点器件和折叠柔性，本发明能够达到小于0.6mm的封装外形，较之采用BGA技术的封装的3mm以及MLF封装的0.9mm厚度，这是一个显著的改进。
与现有解决方案相比，线路板附着所要求的引脚连接的数目也被显著地减少了。
本发明的铜焊盘可以厚于2oz，使得引线连接的间距可以更大。更大的焊盘和间距(1mm或以上)使得SMT(表面安装技术)更容易操作。
从此处所述实施方案，本发明的这些或其它的情况将显而易见。
附图的简要说明
在这些附图中：
图1A示出了市场可购得的采用BGA技术的产品。
图1B示出了市场可购得的采用MLF技术的产品。
图2A示出了市场可购得的MLF基封装的引脚连接/板布局设计。
图2B示出了市场可购得的BGA基封装的引脚连接/板布局设计。
图3是本发明的一个实施方案的内部图。
图4是安装在图形化柔性衬底衬底上的面朝下(倒装芯片)管芯的平面图。
图5示出了柔性衬底的折叠和到管芯背面的附着。
图3是根据本发明的折叠柔性无接合引线多芯片功率封装的一个实施方案的内部图。包括半导体功率管芯以及IC管芯的各个器件301、301’、301”、301等被附着到连续柔性衬底302的主体部分306。各个器件管芯表面上的器件301、301’、301”、301等具有带有倒装芯片凸点的器件焊盘(未示出)。柔性衬底302的延伸部分303和303’被分别折叠在器件301和301’以及器件301”和301上。此柔性衬底在其底部表面上配备有铜接触焊盘(图3中看不到)以及用来附着线路板的连接304。模塑料以细长矩形箱的形状305被形成在封装的周围。用于半导体封装的柔性衬底是一些叠层，它典型地包括焊料掩模层、铜层、以及聚合物层，例如E.I duPont de Nemoursand Co.所出售的商标为Kapton的聚酰亚胺。
图4是附着到图形化柔性衬底上的面朝下(倒装芯片)管芯的平面图。图形化的柔性衬底402具有用来附着线路板的连接404，并具有用来附着管芯背面的延伸部分403和403’。延伸部分403和403’分别具有第一部分406和406’以及第二部分407和407’。第一部分406和406’各具有相邻和平行于图形化柔性衬底402的主体部分409的边沿的边沿，器件管芯401的顶面被附着到此主体部分409。各个第一部分406和406’被焊料掩模覆盖。第二部分407和407’具有至少部分地暴露的衬底402的铜层，并与其各自的第一部分406和406’连接，且从第一部分406和406’延伸到各自延伸部分403和403’的末端，离图形化柔性衬底402主体部分409最远。
一开始，倒装芯片凸点(例如金栓塞)被制作在器件管芯401表面上的器件焊盘上。此制作在晶片层面处完成。
如从图4和图5可见，制造封装结构的方法包括3个步骤。
如图4所示，首先，凸点器件管芯401被附着到图形化柔性衬底402。导热的环氧树脂被分散在图形化的衬底上。然后利用拾放机将凸点器件管芯401降低到环氧树脂，并准确地置于衬底的接触焊盘上。热压工艺被用来建立钉头凸点到柔性衬底上铜焊盘的物理接触。此热压工艺还用作导热环氧树脂的固化工艺，从而仅仅在一个加工步骤中就得到与下方填料的坚固的倒装芯片互连。
第二，如图5中箭头508和508’所示，柔性衬底延伸部分的第二部分(图4中的407和407’以及图5中的507和507’)被折叠。第三，用例如环氧树脂或焊料，延伸部分的第二部分(图4中的407和407’以及图5中的507和507’)被附着到管芯背面501。延伸的柔性衬底第二部分的图形化轨线使MOSFET管芯与其它器件管芯的背面501保持隔离。
诸如银填充的环氧树脂之类的导电环氧树脂在本发明中用来将延伸部分507和507’附着到管芯背面501，使封装能够不包含引线。
然后，如图5所示，用模塑料包封此结构，覆盖从柔性衬底到至少表面的整个厚度。仅仅柔性衬底背面上的连接被暴露，以便进行标准的SMT板附着工艺。
对封装实体进行一些改变是可能的。也可以在器件上采用焊料凸点代替金钉头凸点来得到所述结构中的器件互连。在此情况下，可以用焊料回流和下方填充工艺来将器件附着到柔性衬底。虽然如此，但焊料凸点要求在器件的铝接触焊盘上淀积可焊接的金属化(例如Ti-Ni-Au/Ag)。
封装实体中的另一改变例子是用环氧树脂或焊料将柔性铜带附着到各个器件的漏，来代替折叠衬底的图形化延伸部分。这些铜带将把MOSFET的漏焊盘连接到它们在柔性衬底上的各自接触焊盘。“包含”并不排除其它的元件或步骤。“一个”并不排除多个。单个处理器或其它的单元可以满足权利要求所述的几个装置的功能。

Claims (20)

1.一种电子装配件，它包含：
包含柔性衬底(302)的封装载体，
此衬底(302)包含在聚合物层与焊料掩模层之间的至少一个铜层；
此衬底(302)具有主体部分(306)和至少一个延伸部分(303)；
安装在衬底(302)的主体部分(306)的表面上的至少一个半导体管芯(301)，
此至少一个半导体管芯(301)具有钉头凸点电连接；且
此至少一个延伸部分(303)被折叠成在部分衬底(302)上方延伸，所述部分包括此至少一个半导体管芯(301)。
2.权利要求1的电子装配件，还包含一个或多个电接触焊盘，所述接触焊盘由一部分铜层形成，所述部分在衬底(302)的主体部分(306)的第二表面上暴露于装配件外部，所述接触焊盘是装配件外部上仅有的电接触。
3.权利要求1的电子装配件，其中，装配件的厚度小于0.9mm。
4.权利要求3的电子装配件，其中，装配件的厚度为0.6mm或更小。
5.权利要求1的电子装配件，还包含一个或多个电接触焊盘，所述接触焊盘由在衬底(302)的主体部分(306)第二表面上暴露于装配件外部的一部分铜层形成，至少一个半导体管芯(301)和接触焊盘被互连而无需引线接合。
6.权利要求1的电子装配件，其中，至少一个延伸部分(303)不在衬底(302)的所有主体部分(306)上方延伸。
7.权利要求1的电子装配件，还包含第二延伸部分(303’)，第二延伸部分(303’)被折叠成在衬底(302)主体部分(306)的第二部分上方延伸，第二至少一个半导体管芯(301”)被安装在所述第二部分上。
8.权利要求7的电子装配件，其中，至少一个延伸部分(303)和第二延伸部分(303’)不在衬底(302)的所有主体部分(306)上方延伸。
9.一种电子装配件，包含：
柔性衬底(402)，它具有主体部分(409)和至少一个延伸部分(403)，此至少一个延伸部分(403)包含第一部分(406)和第二部分(407)，第一部分(406)位于第二部分(407)与衬底(402)的主体部分(409)之间；以及
至少一个半导体管芯(401)，具有顶面和背面，顶面与背面相对并被安装在衬底(402)主体部分(409)的表面上，
第一部分(406)被折叠，且第二部分(407)在衬底(402)的表面上被附着至半导体管芯(401)的背面。
10.权利要求9的电子装配件，其中，此至少一个半导体管芯(401)是包含源、栅、以及漏连接的MOSFET，源和栅连接位于顶面上，而漏连接位于背面上。
11.权利要求9的电子装配件，其中，此至少一个半导体管芯(401)包含电连接，所述电连接是钉头凸点。
12.权利要求9的电子装配件，其中，衬底(402)包含位于聚合物层与焊料掩模层之间的至少一个铜层，此衬底(402)还包含一个或多个电接触焊盘，所述接触焊盘由一部分铜层形成，所述部分在衬底(402)主体部分(409)的第二表面上暴露于装配件的外部，所述表面平行于顶面延伸，且所述接触焊盘是装配件外部上仅有的接触焊盘。
13.权利要求9的电子装配件，其中，装配件的厚度小于0.9mm。
14.权利要求13的电子装配件，其中，装配件的厚度为0.6mm或更小。
15.权利要求9的电子装配件，其中，衬底(402)包含位于聚合物层与焊料掩模层之间的至少一个铜层，此衬底(402)包含一个或多个电接触焊盘，所述接触焊盘由一部分铜层形成，所述部分在衬底(402)主体部分(409)的第二表面上暴露于装配件的外部，所述表面平行于顶面延伸，且所述接触焊盘被互连而无需引线接合。
16.权利要求9的电子装配件，其中，不提供引线框。
17.一种装配电子模块的方法，包含：
将凸点器件管芯(401)在凸点器件管芯(401)的第一表面处附着到柔性衬底(402)；
将柔性衬底(402)的第一延伸部分(406)折叠成使柔性衬底的第二延伸部分(407)在凸点器件管芯(401)的第二表面上方；并将第二延伸部分(407)附着到凸点器件管芯(401)的第二表面。
18.权利要求17的方法，其中，凸点器件管芯(401)包含金钉头凸点。
19.权利要求17的方法，其中，凸点器件管芯(401)包含焊料凸点。
20.权利要求17的方法，还包含将模块包封在模塑料中。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101919033B (zh) * 2008-01-22 2011-11-23 Nxp股份有限公司 制造包括至少一个微电子器件在内的微电子封装的方法
CN101582403B (zh) * 2008-05-15 2012-04-04 捷敏服务公司 以夹在金属层之间的倒装管芯为特征的半导体封装
CN102448277A (zh) * 2011-10-13 2012-05-09 烽火通信科技股份有限公司 通信设备单板上多个xfp光模块的散热装置
CN113299564A (zh) * 2021-05-21 2021-08-24 广东佛智芯微电子技术研究有限公司 一种板级扇出柔性封装基板的封装结构及其制备方法

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005235825A (ja) * 2004-02-17 2005-09-02 Renesas Technology Corp 電子回路モジュール
US7868468B2 (en) 2004-11-12 2011-01-11 Stats Chippac Ltd. Wire bonding structure and method that eliminates special wire bondable finish and reduces bonding pitch on substrates
US7675166B2 (en) * 2005-05-11 2010-03-09 Maxim Integrated Products, Inc. Integrated circuit package device comprising electrical contacts making solderless and bondless electrical-mechanical connection
US7768075B2 (en) * 2006-04-06 2010-08-03 Fairchild Semiconductor Corporation Semiconductor die packages using thin dies and metal substrates
JP5165214B2 (ja) * 2006-06-26 2013-03-21 オンセミコンダクター・トレーディング・リミテッド 半導体装置
US7816778B2 (en) * 2007-02-20 2010-10-19 Micron Technology, Inc. Packaged IC device comprising an embedded flex circuit on leadframe, and methods of making same
US9093360B2 (en) 2013-01-11 2015-07-28 Analog Devices, Inc. Compact device package
US9363071B2 (en) 2013-03-07 2016-06-07 Qualcomm Incorporated Circuit to recover a clock signal from multiple wire data signals that changes state every state cycle and is immune to data inter-lane skew as well as data state transition glitches
US9374216B2 (en) 2013-03-20 2016-06-21 Qualcomm Incorporated Multi-wire open-drain link with data symbol transition based clocking
US9755818B2 (en) 2013-10-03 2017-09-05 Qualcomm Incorporated Method to enhance MIPI D-PHY link rate with minimal PHY changes and no protocol changes
US9203599B2 (en) 2014-04-10 2015-12-01 Qualcomm Incorporated Multi-lane N-factorial (N!) and other multi-wire communication systems
US9735948B2 (en) 2013-10-03 2017-08-15 Qualcomm Incorporated Multi-lane N-factorial (N!) and other multi-wire communication systems
EP3114792B1 (en) * 2014-03-06 2021-06-09 Qualcomm Incorporated Clock recovery circuit for multiple wire data signals
US9332940B1 (en) 2015-01-05 2016-05-10 Analog Devices, Inc. Compact wearable biological sensor modules
WO2018164628A1 (en) * 2017-03-10 2018-09-13 Fingerprint Cards Ab Fingerprint sensor module comprising a fingerprint sensor device and a substrate connected to the sensor device
EP4063878A1 (en) 2021-03-25 2022-09-28 Nxp B.V. Integrated circuit and associated method

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3105089B2 (ja) * 1992-09-11 2000-10-30 株式会社東芝 半導体装置
US5637922A (en) * 1994-02-07 1997-06-10 General Electric Company Wireless radio frequency power semiconductor devices using high density interconnect
US6121676A (en) * 1996-12-13 2000-09-19 Tessera, Inc. Stacked microelectronic assembly and method therefor
JPH10189855A (ja) * 1996-12-17 1998-07-21 Samsung Aerospace Ind Ltd マルチチップパッケージ用のリードフレーム及びその製造方法
US6208521B1 (en) * 1997-05-19 2001-03-27 Nitto Denko Corporation Film carrier and laminate type mounting structure using same
US6300679B1 (en) * 1998-06-01 2001-10-09 Semiconductor Components Industries, Llc Flexible substrate for packaging a semiconductor component
JP3186700B2 (ja) * 1998-06-24 2001-07-11 日本電気株式会社 半導体装置及びその製造方法
US6486544B1 (en) * 1998-09-09 2002-11-26 Seiko Epson Corporation Semiconductor device and method manufacturing the same, circuit board, and electronic instrument
US6111761A (en) * 1999-08-23 2000-08-29 Motorola, Inc. Electronic assembly
CN1297252A (zh) * 1999-11-22 2001-05-30 沈明东 多芯片模组装置及其制造方法
JP2001308260A (ja) * 2000-04-25 2001-11-02 Seiko Epson Corp 半導体装置
US6590282B1 (en) * 2002-04-12 2003-07-08 Industrial Technology Research Institute Stacked semiconductor package formed on a substrate and method for fabrication

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101919033B (zh) * 2008-01-22 2011-11-23 Nxp股份有限公司 制造包括至少一个微电子器件在内的微电子封装的方法
CN101582403B (zh) * 2008-05-15 2012-04-04 捷敏服务公司 以夹在金属层之间的倒装管芯为特征的半导体封装
CN102448277A (zh) * 2011-10-13 2012-05-09 烽火通信科技股份有限公司 通信设备单板上多个xfp光模块的散热装置
CN113299564A (zh) * 2021-05-21 2021-08-24 广东佛智芯微电子技术研究有限公司 一种板级扇出柔性封装基板的封装结构及其制备方法

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