CN1702867A - Semiconductor memory device - Google Patents
Semiconductor memory device Download PDFInfo
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- CN1702867A CN1702867A CN 200510074348 CN200510074348A CN1702867A CN 1702867 A CN1702867 A CN 1702867A CN 200510074348 CN200510074348 CN 200510074348 CN 200510074348 A CN200510074348 A CN 200510074348A CN 1702867 A CN1702867 A CN 1702867A
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Abstract
An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes. Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.
Description
Technical field
The present invention relates to semiconductor storage unit, particularly have the semiconductor storage unit of the mode that makes the non-volatile memory architecture effective action.
Background technology
Having a kind of in the integral semiconductor storage in the LSI that packs into is nonvolatile memory.Even being the power supply that cuts off LSI, it also keeps the element of stored information, owing in various application, use LSI, so become very important element.
About the nonvolatile memory of semiconductor element, in non-patent literature 1, can find the record of the memory of so-called floating gate type memory and use dielectric film.Wherein, known to the dielectric film lamination as record, and the memory of stored charge under the catching in its interface and dielectric film etc., compare with floating gate type, needn't form new conductive layer, can form the memory good with the matching of CMOSLSI technology.
But, with regard to stored charge in the dielectric film up to now, seek to carry out simultaneously the injection and the release of electric charge, and have enough electric charge retentivities, so be difficult to realize.To this, propose to replace discharge electric charge, and carry out the rewriting (rewriting) of stored information by the electric charge that injection has a distinct symbols.About this action, can consult non-patent literature 3.In this structure, separately form polysilicon gate that makes the memory action and the grid that carries out the selection of unit.In addition, same record is found in patent documentation 1 and patent documentation 2.
This memory cell structure is two following placements of transistor of base stage basically with NMOS: memory transistor is attached at the configuration of so-called " vertical folded " selects transistorized next door.Is Fig. 1 C with it as the figure shown in the equivalent electric circuit.Have, Figure 1A and Figure 1B represent the plane graph and the profile of the memory element corresponding with circuit shown in Fig. 1 C respectively as an example again.In addition, use the configuration structure example under the situation of this memory cell and forming array to be shown in Fig. 2.Select the grid of transistor and memory transistor to constitute the word line of representing with SGL, MGL respectively, select transistorized diffusion layer to become bit line (BL), and the diffusion layer of memory transistor becomes source electrode line (SL).
In Fig. 3, Fig. 4, the representativeness that illustrates this memory cell writes the erasing move operation.Gate insulating film 950 usefulness of storage grid are formed by the structure of silicon oxide film clamping silicon nitride film, become so-called MONOS structure (Metal-Oxide-Nitride-Oxide Semiconductor (Silicon)).Selecting the gate insulating film 900 of grid is silicon oxide film.Diffusion layer electrode 200,300 will select grid and storage grid to form mask (mask) respectively.Elemental motion as this memory cell has that (1) writes, wipe (2), (3) keep, (4) read four kinds of states.But the common name of these four kinds of states is used as representational, for writing and wiping, also can form opposite call.In addition, motion action also uses representational operation (operation) to illustrate that various maneuver is arranged.Here, discussed the memory cell that forms with the NMOS type for explanation, even but the PMOS type also can similarly form on the principle.
(1) to writing the fashionable Fig. 3 that schematically is shown in.Provide positive potential to storage grid side diffusion layer 200, provide the earth potential identical with substrate 100 to selecting gate electrode side diffusion layer 300.By storage grid 550 being applied the gate overdrive voltage that is higher than substrate 100, making the raceway groove under the storage grid is conducting state.Here, by being reached than high 0.1 to 0.2V the value of threshold value, the current potential of selecting grid becomes conducting state.At this moment, at the strongest electric field of boundary vicinity generation of two grids, thus produce a lot of hot electrons, and be injected into the storage grid side.The generation situation of the charge carrier that bombarding ionization is caused illustrates as 800.Electronics represents that with blank circle mark the hole is represented with having hatched circle.This phenomenon is injected (Source side injection:SSI) as source and by known to the people, about this phenomenon, can consult people's such as A.T.Wu in the non-patent literature 4 record.The memory cell of floating gate type has been adopted in the record here, but injecting mechanism also is same in the insulation membranous type.As the speciality that the hot electron under this mode injects, electric field concentrates on selects grid and storage grid boundary vicinity, so inject in the concentrated area, selection gate electrode side end of storage grid.In addition, in floating gate type, electric charge keeps layer to be made of electrode, and in the insulation membranous type, is stored in the dielectric film, so hot electron is maintained in the very narrow zone.
(2) schematically be shown in Fig. 4 when wiping.Provide negative potential to storage grid 550, provide positive potential, thereby, produce counter-rotating by force, cause the interband tunnel(l)ing, and can generate the hole in the storage grid and the diffusion layer overlapping areas of diffusion layer end to storage grid side diffusion layer 200.It is illustrated with 810.Relevant this interband tunnel(l)ing for example can be consulted the argumentation of people such as T.Y.Chan in the non-patent literature 5.In this memory cell, quicken to channel direction in the hole of generation, and the bias voltage by storage grid produces drawing and is injected in the MONOS film, thereby carries out erasing move.In addition, the situation of the electron-hole pair that the hole produced of generation illustrates with 820.These charge carriers also are injected in the MONOS film.That is, can reduce the threshold value of the storage grid that the electric charge because of electronics rises by the electric charge in the hole that is injected into.
When (3) keeping, electric charge keeps as the electric charge that is injected into the charge carrier among the dielectric film MONOS.Charge carrier in the dielectric film moves very slow, so even do not apply voltage on the electrode, also can keep well.
When (4) reading, provide positive potential, provide positive potential to selecting grid 500, thereby select the raceway groove under the grid to be in conducting state selecting gate electrode side diffusion layer 200.Here, according to write, erase status provides the suitable storage grid current potential that can judge the threshold difference of the storage grid that provided (promptly, the intermediate potential of the threshold value of write state and the threshold value of erase status), thus the charge information that keeps can be read as electric current.
No. 005969383 specification of [patent documentation 1] United States Patent (USP)
No. 6477084 specifications of [patent documentation 2] U.S. Pat
[non-patent literature 1] S.Sze work, ' Physics of SemiconductorDevices, 2nd edition ', Wiley-Interscience pub., p.496～506
[non-patent literature 2] S.Sze work, ' Physics of SemiconductorDevices, 2nd edition ', Wiley-Interscience pub., p.447
[non-patent literature 3] ' 1997 Symposium on VLSI Technology ', 1997, p.63～64
[non-patent literature 4] ' 1986 IEEE, International Electron DeviceMeeting, Technical Digest ', 1986, p.584～587
[non-patent literature 5] ' 1987 IEEE, International Electron DeviceMeeting, Technical Digest ', p.718～721
[non-patent literature 6] ' 2001 IEEE, International Electron DeviceMeeting, Technical Digest ', p.719～722
Adopt the feature of the memory cell of this motion action to be, use the electric charge of dipolar charge carrier, so can greatly change the setting threshold of memory transistor.Fig. 5 is that transverse axis represents that storage grid voltage, the longitudinal axis represent the figure of cell read current.During mensuration, adopt above-mentioned reading state.Compare with the I-V characteristic of initial condition, the situation that improves threshold value by the injection electronics is that write state is ' H '.And inject the situation that reduces threshold value by the hole is erase status ' L '.For example, with the injection of electronics, discharge when changing threshold value, can not utilize initial condition to change threshold value at minus side.Therefore, need write and initial condition between move.On the contrary, by using bipolarity, can realize big changes of threshold.Thus, have under erase status, can obtain the feature of big reading unit electric current.In addition, even this wide many-valued action of operating space polarity also is effective.
On the other hand, in the unit that uses the hole to inject, the problem that changes threshold value because of the break-off in hole is known.About this phenomenon, can consult the argumentation of people such as W.J.Tsai in the non-patent literature 6.By reducing the positive charge in hole, after the hole was injected, threshold value moved to high direction along with the time.The information hold facility of relevant memory cell depends on the change of this threshold value, is big problem so this hole breaks away from the variation that causes, and injects to become because of the hole and hinders the reason that memory forms.
Summary of the invention
Therefore, the objective of the invention is to, address the above problem, the insulated-gate type nonvolatile memory that can carry out stable action is provided.
The variation of reading electric current that this phenomenon that illustrates Fig. 6 causes.Transverse axis is the grid voltage of storage grid, and the longitudinal axis is the reading unit electric current.After this figure has drawn and has just wiped and through the I-V characteristic behind the certain hour.Shown in arrow 850, threshold value rises because of the hole breaks away from as can be known, and waveform moves to right.On the other hand, in the big zone of storage grid voltage, can find out waveform on the contrary left direction move (arrow 860).This is because interfacial characteristics breaks away from along with the hole and recovers.Like this, two kinds of phenomenons produce simultaneously, are that the boundary is to moving in the other direction so current waveform presents with the intersection point.Strictly speaking, this intersection point is not to go up the intersection point that intersects on one point, and the elapsed time dependence is little, in fact, can regard as to go up on one point and intersect.That is, break away from, also can regard as and have motionless point even produce the hole.
This situation is summarised among Fig. 7.At Fig. 6, the current value of establishing intersection point is I
A, and the current value that clips intersection point is I
BAnd I
CAt this moment, to each current value definition threshold value, as Vth-A, Vth-B, Vth-C, its time shown in Figure 7 changes.Transverse axis is the elapsed time of wiping back (back is injected in the hole).Corresponding to arrow 850 and arrow 860, be respectively that Vth-C rises, or Vth-C reduce.On the contrary, with regard to Vth-A, not free change is certain value.
Therefore, by utilizing this intersection point, can obtain stable storage retention performance.
Have the Nonvolatile semiconductor device of selecting grid and electric charge being remained on the storage grid in the dielectric film and adopts the hole to inject, can obtain the current value that reads of not free change, so can carry out stable storage action.
Description of drawings
Figure 1A is the plane graph of separate type (split gate) memory cell.
Figure 1B is the representational equivalent circuit diagram of the separate type memory cell that illustrates among Figure 1A.
Fig. 1 C is the profile of the separate type memory cell shown in Figure 1A.
Fig. 2 has been to use the equivalent circuit diagram of the storage array of separate type memory cell.
Fig. 3 is the schematic element section structure chart that is used to illustrate memory cell structure and write activity.
Fig. 4 is the schematic element section structure chart that is used to illustrate memory cell structure and erasing move.
Fig. 5 is that expression is used to illustrate the figure that writes with the memory transistor operating characteristics of erase status.
Fig. 6 is the figure of the memory transistor operating characteristics that changes in the elapsed time of the IV characteristic of expression erase status.
Fig. 7 is the figure that changes the time of the threshold value of expression erase status.
Fig. 8 is the figure of the erasing move order of expression erasing move of the present invention.
Fig. 9 is the figure of the memory transistor operating characteristics that changes in the elapsed time of the IV characteristic of expression write state.
Figure 10 is the key diagram that writes threshold value and effect of interface energy level.
Figure 11 is the key diagram that writes threshold value and effect of interface energy level.
Figure 12 is chip structure figure.
Figure 13 is a memory cell terminal name.
Figure 14 writes pulse to set reference table.
Figure 15 is the schematic element section structure chart that is used to illustrate write activity.
Figure 16 is the schematic element section structure chart that is used to illustrate write activity.
Figure 17 writes pulse to set reference table.
Figure 18 writes pulse to set reference table.
Figure 19 writes pulse and verification order key diagram.
Figure 20 is the memory cell array equivalent circuit diagram.
Figure 21 writes pulse to set reference table.
Figure 22 writes pulse to set reference table.
Figure 23 writes pulse to set reference table.
Figure 24 is that reference table is set in erasing pulse.
Figure 25 is that reference table is set in erasing pulse.
Figure 26 is that reference table is set in erasing pulse.
Figure 27 is that reference table is set in erasing pulse.
Figure 28 is memory array structure figure.
Figure 29 is that reference table is set in erasing pulse.
Figure 30 is that reference table is set in erasing pulse.
Figure 31 is that reference table is set in erasing pulse.
Figure 32 is that reference table is set in erasing pulse.
Figure 33 is that reference table is set in erasing pulse.
Figure 34 is that reference table is set in erasing pulse.
Figure 35 is that reference table is set in erasing pulse.
Figure 36 is that reference table is set in erasing pulse.
Figure 37 is used to produce the circuit structure diagram that apply pulse corresponding with writing pulse setting table.
Figure 38 is the fashionable sequential chart that applies pulse of writing of expression present embodiment.
Figure 39 is the fashionable sequential chart that applies pulse of writing of another embodiment of expression.
Figure 40 is the fashionable sequential chart that applies pulse of writing of another embodiment of expression.
Embodiment
Below, explain embodiments of the present invention with reference to accompanying drawing.
[embodiment 1]
Below, representational erasing move of the present invention is described.Fig. 8 is the flow chart of expression erasing move order of the present invention.
In the integrating nonvolatile memory of the array that has constituted based semiconductor, for stably write, erasing move, extensively adopt so-called ' verification (verification) action '.This is because when writing and wipe, apply write erasing move after, confirm the level of threshold value, and, repeat to write erasing move in order to reach the setting current potential.Carrying out the unit that the hole is injected,, after having applied erasing pulse, extensively adopt checkout action to the affirmation of erase status in order to produce sufficient erase status.
Have, in Fig. 8, VMG represents storage grid voltage again, and what the grid voltage on the intersection point of VA presentation graphs 6, Icell represented to flow through memory cell reads electric current (cell current), the cell current when IA represents VA, and N represents the number of times that applies of erasing pulse.
In the past, threshold value broke away from the generation time change because of the hole, and for example, when using Ic (Vth-C) to carry out verification, the time of causing because of disengaging changes, so electric current can reduce, can not guarantee the necessary electric current that reads.In addition, after erasing pulse applies,, cause the electric current change, so can not carry out the suitable evaluation of erase status because of until the elapsed time of carrying out checkout action.
Therefore, as shown in Figure 6, the intersection point that changes in the time that is not subjected to, be storage grid voltage V
A, by carrying out and electric current I
AComparison, carry out verification.Because the influence of the time fluctuation after this current point is injected is so can easily judge erase status.
If will read the current value of electric current, then after wiping, even, also can obtain the stable electric current that reads through long-time as this intersection point.In addition, as the electric current that reads of unit, this calibration voltage can be set as the basis.For example, as reading electric current, compare I at needs
ABig electric current I
BSituation under, estimate Vth-B under the initial condition and the poor V of Vth-A
BST, set the storage grid voltage V when reading
AJust can.Than V
AHigh zone, electric current produces the variation that increases, so by carrying out this current settings that reads, can guarantee to read electric current.On the contrary, even under the situation of the electric current that does not need the sort of degree, by with storage grid voltage V
AImplement verification, also can estimate erase status, change so can predict electric current thereafter.That is, because the elapsed time variation of process Vth-A, so if be judged to be certain I
A, its effect of then can estimating and convert.
In addition, can the heterodyne checkpoint.That is, at the voltage V lower than intersection point
FDuring last setting checkpoint, according to V
FThe time electric current and mutual inductance, can predict the current value of intersection point.In view of the above, can be at V
FPoint carries out verification.
[embodiment 2]
Below, the establishing method that writes the verification condition in the erasing move that adopts under the mode situation of the present invention is described.At erase status, as mentioned above, undertaken by intersection point under the situation of verification, can be used as the action window of the reality of this memory cell between the checkpoint under this intersection point and the write state.
On the other hand, known to write state, hot hole being injected under the situation of dielectric film, on dielectric film-interfacial oxide film, generate interface energy level.When interface energy level was arranged, surface potential changed because of the field effect of grid, thereby electronics is hunted down at interface energy level, and because of the electric charge that this electronics carries, the threshold value that defines with electric current greatly changes.Therefore, with regard to the action of nonvolatile memory, the change of threshold value increases, and can see important problem as.This effect, main because of catching of electronics produces, so become big problem writing side.With Fig. 9 this phenomenon is described.At Fig. 9, transverse axis is represented the grid potential of storage grid, and the longitudinal axis adopts logarithm to represent the electric current that reads of unit.Be illustrated in just write after, through the IV characteristic behind the certain hour.After writing, the interface energy level that produces is injected in the hole when wiping, and the slope that reads electric current is diminished.But after the elapsed time, interface energy level recovers, and can become the slope that reads electric current and diminish the situation that waveform forms.Known this recovery phenomenon manifests under the condition of high temperature more consumingly, and is particularly more remarkable in time more than 100 ℃.The usage operation temperature of common semiconductor chip is about-40 ℃ to 100 ℃, so we can say and be difficult to avoid this phenomenon.
The variation of this slope, with regard to the memory cell that electric charge is read as the difference of transistor characteristic, finally the variation as threshold value manifests.That is, at Fig. 9, with I
DUnder the situation for the verification current value, after writing, be V with respect to the verification level
D, after the elapsed time, can regard as and can be changed to V
EProblem.
This variable quantity below is described.About the variable quantity of this threshold value, can consult the record in the non-patent literature 2.That is, the relation of the slope of the amount of the interface energy level of generation and storage grid voltage is clear and definite.Therefore, according to this relation, the result who obtains the relation of the amount of interface energy level and the variable quantity of verification level (variations in threshold voltage amount) is Figure 10, Figure 11.
At Figure 10, Figure 11, with the gate insulator thickness of storage grid as parameter.In this memory cell structure, the gate insulating film 950 of storage grid adopts the laminated construction of silicon oxide film and silicon nitride film.Here, use the effective thickness Tox that is scaled oxide-film to represent.Approach by the thickness that makes storage grid, can suppress the interface energy level effect.But when this thickness approached, the fact that other device properties such as charge-retention property are exerted an influence was known.And this thickness is when thick, and it is known writing the fact that erasing characteristic worsens, so when considering to use the situation of the selection transistor in suitable sub-micron (below 1 micron) generation and memory transistor, in fact spendable effective thickness is considered to Tox＜25nm.In addition, the establishing method of ' L ' state in the storage and the current ratio of ' H ' state is considered to depend on consumingly array and peripheral read-out amplifier characteristic.But, usually,, consider with unit in the delegation to have number about 256 bits as array structure, as this ratio, can will guarantee that three figure places regard standard as.At this moment, cause the threshold variation of 2V under the effect that interface energy level causes.Here, the interface energy level that forms according to the hole is 10
12Cm
-2The report of level, the upper limit as the necessary condition of asking threshold variation is assumed to be 10
13Cm
-2Figure 11 is the figure that obtains the relation of this interface energy level and threshold variation.Be assumed to be 10
13Cm
-2Situation under, to need to estimate the variation of 2V.Wherein, when the verification that writes side, except the effect that this interface energy level produces, set, thereby even, also can obtain the stable electric current that reads through long-time by the high 2V of setting verification level with necessity.In the tentative calculation here, be assumed to be room temperature, but can consider temperature characterisitic based on using to set for basic action is described.
Here, by considering practical cell current, discussed establishing method as the variation of threshold value.On the other hand, as shown in Figure 9, the recovery of interface energy level can be used as the situation of IV slope formation and observes.Under the situation of interface energy level, become the center, work at the valence band electron capture in the electronics conduction band side hole capture of band gap, thus can regard as with surperficial potential energy as the grid voltage of intermediate space for axle causes this recovery phenomenon.At Fig. 9, can on the x axle, observe the situation that this intersection point manifests.In this case, this point can be regarded the fixed point under the write state as, so can use effectively when this point is used for verification.But in fact, the current value of this intersection point is minimum value as shown in Figure 9, so there is not practicality.But the IV waveform that manifests fixed point here presents roughly straight line, so-called sub-threshold property, so even be not direct use, also can use by extrapolation with respect to logarithmic axis.
When below example is set in explanation, under erase status shown in Figure 6, at storage grid voltage is that 2V, cell current are in the unit of 100 μ A/ μ m, in initial condition, at the storage grid voltage corresponding with this cell current value is under the situation of 4V, when the storage grid voltage that writes side is set at 6V, consider the effect of the interface order of above-mentioned explanation, can also improve 2V and be set at 8V.But,, can reduce writing the side calibration voltage, and carry out with low current value by the effect that the conversion slope causes.
Implementing thisly high to write fashionablely,, can obtain good storage action by using a plurality of pulses that write.As mentioned above, the electronics that writes of SSI has in narrow zone by the local feature of injecting.The part of electronics inject formed potential barrier because of the infiltration of the electric field of channel direction by drop-down, the fact that produces the leakage current that is called as puncture is known.Therefore, just realize high threshold value, need to inject very many electronics.And in wiping, in order to wipe this electronics, need to inject very many holes, cause the deterioration of film and wipe the problem of deficiency etc.For fear of it, it is effective that the electronics wrting method of channel hot electron (CHE) mode and SSI mode are made up.So-called CHE is that the electric field by raceway groove and diffusion layer end comes accelerated electron, thereby generates hot electron, and is injected into the mode of electric charge maintaining part.Therefore, injecting near the wide zone of diffusion layer than SSI.Certainly, CHE and SSI are used to illustrate that electronics injects the model of mechanism, not difference strictly.Here, use them, in the pulse of carrying out CHE, also comprise the injection of SSI, and the pulse of carrying out SSI also comprises the injection of CHE for two kinds of different pulses are described.
The injection of CHE is compared with SSI, by the voltage of storage grid is set little the realization.Therefore, in order to realize high writing, at first, set storage grid voltage low, and after the injection of having carried out CHE, improve writing of storage grid voltage.In this case, under the state that is injected by wide formula by the CHE electronics, carry out local injection, carry out the effect that height writes effectively so have to inject with few electronics by SSI.Therefore, the SSI injection length can be shortened, and the voltage that applies on the diffusion layer can be reduced.For example, at first carry out just can writing after storage grid voltage is writing of 8V with 11V storage grid voltage.In addition, meanwhile, diffusion layer voltage can be changed into 5.5V from 6.5V.
Represent the multistage effect that writes generation in further detail.In multistage writing, improving under the more weak storage grid voltage condition, injected electronics owing to exist, so electronics thereafter injects changes in distribution.CHE inject is improved storage grid voltage, and situation about producing when storage grid side diffusion layer voltage is set lowly state is discussed.After multistage the 2nd time of writing, because existence injection electronics so far, so can regard the electronics that same mechanism causes as.Below, in order offering some clarification on,, the bias voltage title of each terminal to be shown in Figure 13, and to use representativeness action bias condition shown in Figure 14 to discuss according to Fig. 1 C.These figure are the figure that are used to provide image, do not specify numerical value., carry out electronics and inject (Figure 15) by storage grid voltage being set at the pulse that writes of 6V at step1.In Figure 15, represent electric charge savings layer by the laminated construction of silicon oxide film 954, silicon nitride film 955, silicon oxide film 956.At step1, shown in 850, at first selecting transistor side to carry out the electronics injection.At step2, even improve storage grid voltage, effectively storage grid voltage also descends because of the electron charge of putting aside in 850.Therefore, shown in arrow among Figure 16 830, electronics is carried out in distance diffusion layer electrode 200 nearer zones 851 inject.Certainly, inject, so 850 electron density and the distribution of film thickness direction changed to widen at the electronics that does not hinder fully during this period to 850.This can think fashionable writing of back level, and the injecting mechanism of CHE works more consumingly.Therefore, inject,, also can adopt the electronics of CHE to inject even improve final storage grid voltage by carrying out multistage step (step).Because the electronics that is injected into can form the shape of wide distribution in the storage grid zone, so can improve threshold value by the distribution of widening effectively.On the contrary, under the identical situation of threshold value, in the distribution of widening, owing to can reduce the unit charge density that each injects the position injected electrons, so can make the electronics retention performance after writing good.
Figure 17 also represents to have adopted the injection example of multistage step.Above-mentioned checkout action can be used in combination.That is,, can not apply unwanted high storage grid voltage, just carry out electronics until the threshold status of necessity and inject by in the step of necessity, carrying out verification.For example,, then needn't carry out step 4, so storage grid can write processing before 9V if can write until enough height in step 3.This writing mode is prepared the reference table that pulse shown in Figure 17 is set, and each step is carried out write activity according to reference table.When the electronics of step 1 injects, because the pressure drop that electronics causes is little, so can be set at the pulse duration of short time.Its situation is shown in Figure 18.
These reference tables, the control program that can be used as Nonvolatile storage array forms.In addition, in the circuit of storage array, can pack into as circuit structure by element.For example, as shown in figure 37, the counter of the step number apply pulse is set, the selector of the power line (Vd1, Vd2, Vd3, Vd4) by having different potentials drives the driver of storage grid (MGL), can apply different voltage by step.
Injecting under the situation of carrying out step 1, after having carried out step 1,, obviously do not reach calibration reference even carry out verification with very weak electronics yet.Therefore, by carrying out step 1 verification afterwards, the write time can be shortened.Here, using step 1 to be illustrated, but under the situation of using multistage step, also save unwanted verification after step 2, after repeating to write, carry out verification, is being effective aspect shortening the write time.Do not carry out verification in initial two-stage, the write sequence that carries out when the pulse thereafter applies under the situation of verification is summarised among Figure 19.
At Figure 38, show with slip chart and to write the fashionable combination that applies pulse.Here, being conceived to a unit describes.Here, applied write pulse P1, P2, P3 after, carry out checkout action (V1), apply as required and write pulse P4.Here, provide P1, P2, P3, but as shown in figure 39, also can gather is that a pulse is carried out with the pulse of cutting apart.In the figure, except timing, also represent situation with each P1, P2, the corresponding different storage grid bias voltage that applies of P3.Vd1 is corresponding with checkpoint.As shown in figure 40, even in identical pulse,, also can produce same effect by Iterim Change voltage.
Charge holding film worsens because of repeating to rewrite, and need carry out stronger writing.Therefore,, in step early, carry out initial verification, under the situation that number of rewrites increases, in slower step, carry out initial verification, can shorten the write time by in number of rewrites is few.Here, be illustrated, and also be effective carrying out under the multistage situation of wiping for writing.
In addition, in table so far, illustration the situation of all terminal voltages is provided.
But under the situation that obtains array action shown in Figure 20, structure, reference table is not based on the parameter of voltage, and can constitute with current value as parameter.Describe by writing of two memory cell (Bit0 and Bit1) Figure 20.At this moment, each drain side diffusion layer current potential (Vd) is provided by BL0, BL1.BL0 and BL1 are being inserted and put by MP0, MP1 and MN0, MP1 up and down, and its grid potential provides by the circuit that has connected constant-current source CCS1, CCS2.CCS1 and CCS2 are used to flow through electric current I 1, I2, so the grid that is set at MP0, MP1 provides the current potential that flows through electric current I 1.Equally, in MN0, MN1, be set at the grid potential that flows through electric current I 2.This moment in the unit that writes ' H ' by BS0 and BS1 conducting are selected.So from downside flow out I2, can obtain in memory cell flow through the state of electric current I p from upside inflow current I1 this moment.That is, can be with the current potential of Vd as the Ip=I1-I2 relation.For example, when cell current Ip was 1 μ A, selecting transistorized gate overdrive (Vcg-Vd) among Figure 14 was 0.5V, and corresponding therewith, Vd provides the current potential about about 1V among Figure 21.Here, in order to understand explanation easily, omit relevant body effect.In such array structure,, has the feature of the setting degree of freedom increase of selecting transistorized grid potential owing to can stipulate by cell current.That is, in Figure 21, even in the memory cell of setting with 1.5V, also can be set at 1V as shown in figure 22.At this moment, even Vs is identical value (5V), also can reduce Vd, so can increase Vs-Vd.Thus, can improve and write efficient.
In addition, as shown in figure 23,,, can inject electronics by setting diffusion layer electrode potential Vs high for the low setting of storage grid current potential widelyer.
Even in wiping, use the mode of this pulse reference table also effective.In erasing move, in the unit that is written as ' H ' state, because of the electric charge of having put aside electronics produces high electric field.That is, erasing pulse applies back bias voltage to storage grid, and storage grid side diffusion layer electrode potential is applied positive bias.At this moment, because of having the electric charge of electronics, the negative bias pressure of actual storage grid, the interelectrode potential difference of storage grid-diffusion layer is big.Therefore, produce a large amount of holes, flow through the big electric current of wiping.Therefore, as shown in figure 24, it is effective reducing and weaken Vs in step 1.In addition, as shown in figure 25,, can operate wiping electric current by setting pulse duration.
In addition, when carrying out the hole injection by applying erasing pulse, it is known that the electric charge in the hole that utilization is put aside suppresses the hole generation.Therefore, in order to wipe fully, it is effective that step ground strengthens electric field.On the other hand, the hole is infused in and produces stress in the dielectric film, causes that the fact that film worsens is known.Therefore, need avoid excessive hole to inject.Therefore, reference table as shown in figure 26 carries out verification, and electric field step ground is risen, when wiping fully, by stopping wiping more than it, can avoid need not the hole inject.In addition, as shown in figure 27, set, can carry out high efficiency wiping by the bias voltage of storage grid.
As shown in figure 28, carry out erasing move, can reduce to wipe electric current by storage array 960 is divided into piece 970.Figure 28 represents array is divided into eight the example of A0 to A7.The reference table corresponding with it is shown in Figure 29.At Figure 29, added the project of selecting piece.From step1 to 24, carry out every selection, carry out the selection of all pieces at step25.This is because wiping the electron production highfield of initial savings, and flows through the big electric current of wiping.By this initial erase is carried out with every, can reduce electric current.In addition, by wiping with every, when wiping, also produce non-selected cell.Thereby need to consider to disturb.Therefore, shown in step25, select all pieces wipe the order be effective.In order once to wipe,, also can be suppressed to little electric current even select all pieces.The order of the piece of selecting in the wiping of this mode is selected all pieces as shown in figure 30 successively, can apply multistage pulse simultaneously.
Figure 31 is illustrated in the figure that carries out the reference table under the erasure case when selecting to flow through electric current in the transistor.By applying the hot carrier component that channel current causes, can make the efficiency of erasing height.In addition,, produce superfluous hot carrier, the problem that exists the withstand voltage puncture of element to bring adopting under the situation of this mode.Therefore, it is effective using Current Control shown in Figure 20.Reference table in this case is Figure 32.For example, as Vd, as long as channel current Ip flows through with 1 μ A.
In the injection mode of this hole, even reduce diffusion layer voltage (Vs), also have can injected hole feature.Therefore, carrying out such multistage the wiping of reference table shown in Figure 33, is being effective aspect the reduction leakage current.That is,,, produce big leakage current so between diffusion layer-storage grid, produce highfield owing in step1, put aside electronics.Therefore, during step1, reducing diffusion layer voltage, is being effective aspect the reduction leakage current.Also can behind the electronics that has relaxed by the step1 savings, wipe.
In addition, if erasing move and the write activity of this step1 compared, then the setting current potential of storage grid is just in time positive and negative opposite as can be known.Therefore, at step1,,, can be reduced in the hole of diffusion layer end savings by overlapping rewriting by obtaining the strong setting that writes of CHE effect.The reference table of the multistage step of this moment is shown in Figure 34.Like this, except reference table, can also implement and write or processing that erasing move carries out simultaneously.In the reference table shown in Figure 35, be after having carried out multistage wiping, by storage grid is applied positive potential, the reference table of the order of excess holes is removed in expression.Shown in the reference table of Figure 36, after having carried out every wipe,, can obtain storage grid is carried out the order of positive bias to all pieces.
[embodiment 3]
Below, illustrate the integrated a plurality of situation of memory module.
Figure 12 represents its structure chart.On chip, load in mixture the required storage array of high speed motion and for example be used to reduce consumption electric power and the required array of low speed action.At this moment, in the required storage array of high speed motion, can adopt aforesaid hot hole injection mode.In this case, even identical memory cell also can change manner of execution as required.In the structure shown in Figure 12, only in high speed storage array, used the checkout action described in the embodiment 1 and 2.
Claims (20)
1. a semiconductor storage unit is characterized in that, comprising:
The 1st insulated-gate type field effect transistor has between on the Semiconductor substrate the 1st grid across dielectric film stack gate electrode;
The 2nd insulated-gate type field effect transistor has the 2nd grid that has comprised the electric charge savings film that forms on the zone of the described Semiconductor substrate adjacent with described the 1st insulated-gate type field effect transistor;
The 1st raceway groove is formed in the described Semiconductor substrate of described the 1st insulated-gate type field effect transistor below;
The 2nd raceway groove is in the described Semiconductor substrate below described the 2nd insulated-gate type field effect transistor, with the adjacent formation of mode that is electrically connected with described the 1st raceway groove; And
The 1st impurity diffusion layer and the 2nd impurity diffusion layer form respectively in that another of distolateral and described the 2nd raceway groove of described the 1st raceway groove is distolateral, so that insert the zone of the described Semiconductor substrate that has been formed described the 1st raceway groove and described the 2nd raceway groove;
Described semiconductor storage unit have by electronics being injected into described electric charge savings film write, by the hole being injected into wiping/write activity that the electric charge savings film that has been injected into described electronics wipes,
On the current-voltage characteristic of described electric current under the state that the hole is injected into described the 2nd insulated-gate type field effect transistor and described the 2nd grid, reading current value is I1, the electric charge that does not carry out write/erase injects action and during through reading current value and be I2 behind the certain hour, the storage grid voltage of the relation of expression I1＞I2 is V1
Under the state that has injected described hole, be I3 reading current value, do not write that the electric charge wiped injects action and during through reading current value and be I4 behind the certain hour, the storage grid voltage that expression becomes the relation of I3＜I4 is under the situation of V2,
The storage erasing move of described electric charge savings film carries out under the storage grid voltage Vv of the relation that satisfies V1＜Vv＜V2 state.
2. semiconductor storage unit as claimed in claim 1 is characterized in that, wipes the checkout action of electric current under described storage grid voltage Vv.
3. semiconductor storage unit as claimed in claim 1, it is characterized in that, the electric current that reads when not being injected into storage grid voltage under the state of electric charge being Vi in described electric charge savings film is Ii, the electric current that reads after electronics injects in the described electric charge savings film is I5, and when satisfying Ii＞I5, (Vi+2V) is set at write state with storage grid voltage.
4. semiconductor storage unit as claimed in claim 3 is characterized in that, the verification that writes under described storage grid voltage (Vi+2V).
5. a semiconductor storage unit has a plurality of non-volatile semiconductor storage arrays that are formed on the Semiconductor substrate, it is characterized in that,
At least under the situation of injecting the low threshold status be formed on the memory cell that a non-volatile semiconductor storage array uses by the hole, must be with the threshold setting that writes of described non-volatile semiconductor storage array than the memory cell height of other non-volatile semiconductor storage arrays.
6. an integrated semiconductor nonvolatile memory is characterized in that, comprising:
The 1st insulated-gate type field effect transistor has between on the Semiconductor substrate the 1st grid across dielectric film stack gate electrode;
The 2nd insulated-gate type field effect transistor has the 2nd grid that has comprised the electric charge savings film that forms on the zone of the described Semiconductor substrate adjacent with described the 1st insulated-gate type field effect transistor;
The 1st raceway groove is formed in the described Semiconductor substrate of described the 1st insulated-gate type field effect transistor below;
The 2nd raceway groove is in the described Semiconductor substrate below described the 2nd insulated-gate type field effect transistor, with the adjacent formation of mode that is electrically connected with described the 1st raceway groove; And
The 1st diffusion layer electrode and the 2nd diffusion layer electrode form respectively in that another of distolateral and described the 2nd raceway groove of described the 1st raceway groove is distolateral, so that insert the zone of the described Semiconductor substrate that has been formed described the 1st raceway groove and described the 2nd raceway groove;
By on described the 2nd grid, applying voltage, and inject electronics and hole and write to described electric charge savings film from described the 2nd channel region,
Said write is carried out multiple pulses and is applied on described the 2nd grid, described pulse voltage decides according to pre-prepd reference table separately.
7. integrated semiconductor nonvolatile memory as claimed in claim 6 is characterized in that described reference table is stored by the circuit element structure.
8. integrated semiconductor nonvolatile memory as claimed in claim 6 is characterized in that, in described multiple pulses applies, after predetermined pulse applies, before the following subpulse that carries out described predetermined pulse applies, carries out the described verification of claim 4.
9. an integrated semiconductor nonvolatile memory is characterized in that, comprising:
The 1st insulated-gate type field effect transistor has between on the Semiconductor substrate the 1st grid across dielectric film stack gate electrode;
The 2nd insulated-gate type field effect transistor has the 2nd grid that has comprised the electric charge savings film that forms on the zone of the described Semiconductor substrate adjacent with described the 1st insulated-gate type field effect transistor;
The 1st raceway groove is formed in the described Semiconductor substrate of described the 1st insulated-gate type field effect transistor below;
The 2nd raceway groove is in the described Semiconductor substrate below described the 2nd insulated-gate type field effect transistor, with the adjacent formation of mode that is electrically connected with described the 1st raceway groove; And
The 1st diffusion layer electrode and the 2nd diffusion layer electrode form respectively in that another of distolateral and described the 2nd raceway groove of described the 1st raceway groove is distolateral, so that insert the zone of the described Semiconductor substrate that has been formed described the 1st raceway groove and described the 2nd raceway groove,
By on described the 2nd grid, applying voltage, and inject electronics and hole and write to described electric charge savings film from described the 2nd channel region,
Said write is carried out multistage step on described the 2nd grid voltage applies, and described multistage step voltage decides according to pre-prepd reference table separately.
10. integrated semiconductor nonvolatile memory as claimed in claim 6 is characterized in that described reference table is stored by the circuit element structure.
11. integrated semiconductor nonvolatile memory as claimed in claim 6 is characterized in that, after described multistage step voltage applies, carries out the described verification of claim 4.
12. an integrated semiconductor nonvolatile memory is characterized in that, comprising:
The 1st insulated-gate type field effect transistor has between on the Semiconductor substrate the 1st grid across dielectric film stack gate electrode;
The 2nd insulated-gate type field effect transistor has the 2nd grid that has comprised the electric charge savings film that forms on the zone of the described Semiconductor substrate adjacent with described the 1st insulated-gate type field effect transistor;
The 1st raceway groove is formed in the described Semiconductor substrate of described the 1st insulated-gate type field effect transistor below;
The 2nd raceway groove is in the described Semiconductor substrate below described the 2nd insulated-gate type field effect transistor, with the adjacent formation of mode that is electrically connected with described the 1st raceway groove; And
The 1st diffusion layer electrode and the 2nd diffusion layer electrode form respectively in that another of distolateral and described the 2nd raceway groove of described the 1st raceway groove is distolateral, so that insert the zone of the described Semiconductor substrate that has been formed described the 1st raceway groove and described the 2nd raceway groove,
By on described the 2nd grid, applying voltage, and inject electronics and hole and write to described electric charge savings film from described the 2nd channel region,
Said write and wipe the pulse of carrying out repeatedly apply on described the 2nd grid, described pulse voltage decides according to pre-prepd reference table separately.
13. integrated semiconductor nonvolatile memory as claimed in claim 12 is characterized in that, has stipulated pulse duration in described reference table.
14. integrated semiconductor nonvolatile memory as claimed in claim 12 is characterized in that, a plurality of write the applying of pulse during, carry out the verification of claim 4, during the applying of a plurality of erasing pulses, carry out the verification of claim 2.
15. integrated semiconductor nonvolatile memory as claimed in claim 12 is characterized in that, carried out at least twice write the applying of pulse after, carry out verification.
16. integrated semiconductor nonvolatile memory as claimed in claim 12 is characterized in that, after having carried out the applying of at least twice erasing pulse, carries out verification.
17. integrated semiconductor nonvolatile memory as claimed in claim 12 is characterized in that, carried out at least twice write the applying of pulse after, carry out verification, after having carried out the applying of at least twice erasing pulse, carry out verification.
18. an integrated semiconductor nonvolatile memory is characterized in that, comprising:
The 1st insulated-gate type field effect transistor has between on the Semiconductor substrate the 1st grid across dielectric film stack gate electrode;
The 2nd insulated-gate type field effect transistor has the 2nd grid that has comprised the electric charge savings film that forms on the zone of the described Semiconductor substrate adjacent with described the 1st insulated-gate type field effect transistor;
The 1st raceway groove is formed in the described Semiconductor substrate of described the 1st insulated-gate type field effect transistor below;
The 2nd raceway groove is in the described Semiconductor substrate below described the 2nd insulated-gate type field effect transistor, with the adjacent formation of mode that is electrically connected with described the 1st raceway groove; And
The 1st diffusion layer electrode and the 2nd diffusion layer electrode form respectively in that another of distolateral and described the 2nd raceway groove of described the 1st raceway groove is distolateral, so that insert the zone of the described Semiconductor substrate that has been formed described the 1st raceway groove and described the 2nd raceway groove,
By on described the 2nd grid, applying voltage, and inject electronics and hole and write and wipe to described electric charge savings film from described the 2nd channel region,
Said write and wipe the voltage that carries out multistage step on described the 2nd grid and apply, described multistage step voltage decides according to pre-prepd reference table separately.
19. integrated semiconductor nonvolatile memory as claimed in claim 9 is characterized in that described reference table is stored by the circuit element structure.
20. integrated semiconductor nonvolatile memory as claimed in claim 6 is characterized in that, after described multistage step voltage applies, carries out the described verification of claim 4.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102682843A (en) * | 2011-03-09 | 2012-09-19 | 拉碧斯半导体株式会社 | Nonvolatile semiconductor memory and data writing method |
| CN102779554A (en) * | 2006-05-15 | 2012-11-14 | 苹果公司 | Maintenance operations for multi-level data storage cells |
| CN103904081A (en) * | 2012-12-26 | 2014-07-02 | 爱思开海力士有限公司 | Nonvolatile memory device and method for fabricating the same |
| CN110729016A (en) * | 2018-07-16 | 2020-01-24 | 爱思开海力士有限公司 | Memory device, memory system and method of operating the same |
| CN110838328A (en) * | 2018-08-17 | 2020-02-25 | 北京兆易创新科技股份有限公司 | Memory erasing method and system |
| CN112017717A (en) * | 2019-05-28 | 2020-12-01 | 美光科技公司 | System and method for improving memory control voltage calibration |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5462461B2 (en) | 2008-09-30 | 2014-04-02 | 株式会社東芝 | Nonvolatile semiconductor memory device and driving method thereof |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5095344A (en) * | 1988-06-08 | 1992-03-10 | Eliyahou Harari | Highly compact eprom and flash eeprom devices |
| JPH03222196A (en) * | 1990-01-26 | 1991-10-01 | Hitachi Ltd | Non-volatile semiconductor memory device |
| JP2984045B2 (en) * | 1990-09-27 | 1999-11-29 | 沖電気工業株式会社 | Semiconductor storage device |
| JPH05174586A (en) * | 1991-12-24 | 1993-07-13 | Kawasaki Steel Corp | Electrically erasable nonvolatile memory |
| JPH0729385A (en) * | 1993-07-12 | 1995-01-31 | Hitachi Ltd | Eeprom device |
| JP2987105B2 (en) * | 1996-06-10 | 1999-12-06 | ハライ エリヤホウ | Flash EEprom memory system and its use |
| JPH113597A (en) * | 1997-04-15 | 1999-01-06 | Toshiba Microelectron Corp | Non-volatile semiconductor memory, verifying method for writing data to non-volatile semiconductor, memory, and writing method for data to non-volatile semiconductor memory |
| JPH11220111A (en) * | 1998-01-29 | 1999-08-10 | Sanyo Electric Co Ltd | Nonvolatile semiconductor storage device |
| JP4550206B2 (en) * | 1999-02-19 | 2010-09-22 | ルネサスエレクトロニクス株式会社 | Driving method of nonvolatile semiconductor memory device |
| JP4084922B2 (en) * | 2000-12-22 | 2008-04-30 | 株式会社ルネサステクノロジ | Non-volatile memory device writing method |
| JP2002260388A (en) * | 2001-03-02 | 2002-09-13 | Sony Corp | Semiconductor memory which makes contents address possible and its operating method |
| JP2003046002A (en) * | 2001-07-26 | 2003-02-14 | Sony Corp | Non-volatile semiconductor memory and operation method |
| TW546840B (en) * | 2001-07-27 | 2003-08-11 | Hitachi Ltd | Non-volatile semiconductor memory device |
| JP3632001B2 (en) * | 2001-12-28 | 2005-03-23 | サンディスク コーポレイション | Flash EEprom memory system and method of use thereof |
| JP4052857B2 (en) * | 2002-03-18 | 2008-02-27 | 株式会社日立製作所 | Nonvolatile semiconductor memory array and memory array read method |
| JP4647175B2 (en) * | 2002-04-18 | 2011-03-09 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit device |
| JP2004087770A (en) * | 2002-08-27 | 2004-03-18 | Sony Corp | Nonvolatile semiconductor memory device and charge injection method thereof |
| JP4372406B2 (en) * | 2002-11-11 | 2009-11-25 | 株式会社ルネサステクノロジ | Nonvolatile semiconductor memory device and semiconductor integrated circuit device |
| JP2007272952A (en) * | 2006-03-30 | 2007-10-18 | Renesas Technology Corp | Semiconductor storage device |
-
2005
- 2005-05-27 CN CN200510074348A patent/CN100595923C/en active Active
-
2008
- 2008-01-04 JP JP2008000095A patent/JP2008153678A/en active Pending
-
2011
- 2011-02-21 JP JP2011034239A patent/JP5080663B2/en active Active
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|---|---|---|---|---|
| CN102779554A (en) * | 2006-05-15 | 2012-11-14 | 苹果公司 | Maintenance operations for multi-level data storage cells |
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| CN102682843A (en) * | 2011-03-09 | 2012-09-19 | 拉碧斯半导体株式会社 | Nonvolatile semiconductor memory and data writing method |
| CN103904081A (en) * | 2012-12-26 | 2014-07-02 | 爱思开海力士有限公司 | Nonvolatile memory device and method for fabricating the same |
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| CN100595923C (en) | 2010-03-24 |
| JP2008153678A (en) | 2008-07-03 |
| JP2011108357A (en) | 2011-06-02 |
| JP5080663B2 (en) | 2012-11-21 |
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