JPH05174586A - Electrically erasable nonvolatile memory - Google Patents

Abstract

PURPOSE:To remarkably increase the number of rewriting times and a life by obtaining a threshold value corresponding to a predetermined current flowing to a sample cell and deciding '0' or '1'. CONSTITUTION:Sample cells 20, 22 are provided. When a predetermined gate voltage is applied to the cells 20, 22 of a writing state, a first current flowing in the cells is obtained. When a predetermined gate current is applied to the cells 20, 22 of an erased state, a second current flowing in the cells is obtained. A threshold value corresponding to an intermediate current value between the first current of the writing state and the second current of the erasing state is obtained, and '0' or '1' is decided by using the threshold value. Thus, a threshold value is varied in the memory cell as a time is elapsed. When this change with time is compensated, the number of rewriting times can be remarkably increased from 10<6> or less to 10<7> times or more.

Description

Detailed Description of the Invention

[0001]

The present invention relates to, for example, MNOS, MO.
The present invention relates to a memory using an electrically erasable non-volatile memory cell called NOS or the like.

[0002]

2. Description of the Related Art Conventionally, for example, MNOS, MONOS
Electrically erasable non-volatile memory cells (E ² PROM, flash EPROM, etc.) called “etc.” have been widely used. This memory cell injects electrons into an electrically insulated thin film or gate electrode (called "writing") or draws electrons from the thin film or gate electrode (called "erase"). As a result, the threshold voltage of the gate at which the memory element shifts from the off state to the on state rises and falls, and information is recorded by utilizing this.

FIG. 3 is a graph showing an example of dependence of threshold voltages of MNOS and NOMOS on write time and erase time. As shown in this graph, for example, 1
When writing and erasing for msec, the threshold voltages become about + 2V and -2V, respectively. On the other hand, when reading information from this memory cell, a threshold voltage in a state where electrons are injected (writing state; here, this state is set to '0') and a state where electrons are extracted (erasing state; here, this state) By setting the threshold voltage difference (memory window) to "1".
Whether 0'or '1' is recognized.

FIG. 4 shows the contents stored in the memory cell.
FIG. 5 is a diagram showing an example of a conventional read circuit for recognizing 0'or '1', and FIG. 5 is an explanatory diagram of the read circuit shown in FIG. Sources of a large number of memory cells 10, 12, ...
The respective transistors 11, 13, ... Are connected to the ground, and these memory cells 10, 12 ,.
Is connected to the read line 14.

Here, the transistor connected to the memory cell 10 now
The positive voltage V is applied to the gate of the transistor 11. _ccIs applied, this
Together with the other memory cells 12, ...
The gates of the star 13, ... Must be kept at the ground potential.
When the memory cell 10 is selected by
As shown in, the threshold voltage is applied to the gate of the memory cell 10.
Predetermined gate voltage V that is slightly higher than the voltage_g Is applied
And its gate voltage V_gAnd the threshold voltage
Current flows.

Here, the memory cell 10 is in the write state "0".
When the threshold voltage when the memory cell 10 is "1" is V _write and the threshold voltage when the erased state is "1" is V _erase , I shown in FIG. 5 depending on whether the memory cell 10 is "0" or "1". ₁ or I ₂ flows to the bit line 14. Then, this current is converted into a voltage signal by the current-voltage conversion circuit 16, and this voltage signal is input to the comparator 18 and compared with a predetermined reference voltage V _ref , whereby the contents stored in the memory cell 10 are stored. It is determined whether it is 0'or '1'. Since the reference voltage V _ref is a predetermined constant voltage, it is not necessary to provide the comparator 18 independently, and it may be integrated with the current-voltage conversion circuit.

[0007]

However, there is a problem in that the threshold voltage of the memory cell changes with the lapse of time, and the method of changing the threshold varies depending on the number of times of writing and erasing of the memory cell. FIG. 6 shows a prescribed number of memory cells called MNOS (1
Times, 10 ⁵ to 10 ⁷ times) write is a graph showing an example of the charge retention characteristics after repeated erasure.

As can be seen from this graph, the threshold voltage decreases with the passage of time in the written state, and the threshold voltage rises with the passage of time in the erased state, and the difference between the threshold voltages in these two states shrinks. The change state of the threshold voltage varies depending on how many times writing, erasing and writing are performed. In addition, this graph shows the non-discriminating range when the base potential is 0V. When the threshold voltage in the written state falls within the non-discriminating range, it is impossible to discriminate between "0" and "1". Therefore, the time until the threshold voltage falls within the non-discriminating range is the life of the memory. This non-discriminating range changes variously mainly depending on the circuit of the read system. For example, in the example shown in FIG. 6, when rewriting is performed 10 ⁷ times,
In less than about 10 ⁶ seconds (about 11 days), the erased threshold voltage is in the non-discriminating range and is therefore the life of this memory. Such a change in the threshold voltage is not limited to MNOS and is the same for MONOS and the like. In the case of MONOS, the life after rewriting 10 ⁷ times is about 10 years as an example.

Here, in the case of electrically erasable nonvolatile memory cells such as NMOS and MONOS, one of the important characteristics is how much the number of rewritable times can be increased and how long the life can be extended. In view of the above circumstances, it is an object of the present invention to extend the number of times of rewriting and the life of a memory cell by devising a read circuit.

[0010]

An electrically erasable non-volatile memory according to the present invention for achieving the above object comprises a large number of memory cells, writing to each of the plurality of memory cells,
A first sample which is written and erased a number of times representative of the number of erases, and a first cell which flows to the sample cell in the written state when a predetermined gate voltage is applied to the sample cell.
And a second current flowing through the sample cell in the erased state when a predetermined gate voltage is applied to the sample cell in the erased state. The current value of the first current and the second current for discriminating whether the memory cell is in the written state or the erased state by comparing with the signal value corresponding to the current value of the third current. The present invention is characterized by comprising a threshold value calculation circuit that outputs a threshold value corresponding to an intermediate current value with the current value of.

Here, only one sample cell is provided, and when writing and erasing to this sample cell, the first current and the second current are respectively measured, and these first currents are measured. , At least one of the second currents may be stored and a threshold value corresponding to an intermediate current value thereof may be output, but a plurality of sample cells are provided and one of The write state may be used and the other may be used as the erased state.

The "signal value corresponding to the current value" may be the current value itself or the current value converted into a voltage value, and the signal corresponding to the current value. It means that it can be anything. In the electrically erasable non-volatile memory of the present invention, the threshold value calculation circuit is arranged on a write state side of a current range in which it is impossible to distinguish whether the memory cell is in the write state or the erase state. When the difference between the current value at the boundary and the current value of the third current when the memory cell is in the written state, and the current value at the boundary on the erased state side of the current range and the memory cell is in the erased state It is preferable that the threshold value is output such that the difference between the third current and the current value is substantially equal to each other.

[0013]

The above-mentioned electrically erasable non-volatile memory of the present invention
Write the same number of times as writing and erasing to the memory cell
Only the sample cell to be erased
And the second current in the erased state
The threshold value corresponding to the intermediate current value of
'0' and '1' are determined by using a certain value
Therefore, for example, 10 shown in FIG.⁷ In case of rewriting, the conventional 1
0⁶ 10 times or less ⁷ Lifespan dramatically more than once
It can be postponed.

Further, in obtaining the intermediate current value, the current value at the boundary of the non-discriminating range determined by the read circuit is taken into consideration so that the write state side and the erase state side have substantially equal margins. By obtaining the threshold value, the life can be further extended.

[0015]

EXAMPLES Examples of the present invention will be described below.
It should be noted that only characteristic parts will be shown and described here, and circuits that are obvious for configuring the non-volatile memory, such as erase and write circuits, booster circuits, and sense amplifiers, are not shown and described. Has been done.

FIG. 1 is a circuit diagram showing two sample cells included in an electrically erasable non-volatile memory according to one embodiment of the present invention and a read circuit for reading the two sample cells. Transistors 21 and 23 are provided between the sources of two sample cells 20 and 22 having the same structure as a large number of memory cells (not shown in FIG. 1) and the ground.

When writing and erasing are performed on a large number of memory cells, two sample cells 2 are written each time writing and erasing are performed on average once for each of the large number of memory cells.
Of the 0 and 22, the sample cell 20 is erased first,
Next, writing is performed, and the sample cell 22 is first written and then erased. A flash EPROM
In the case of a memory referred to as, particularly, a large number of memory cells are collectively erased, so that the number of times of writing and erasing of the sample cell and the normal memory cell are completely the same. Since this writing and erasing circuit is a widely known technique, its illustration and description are omitted here.

Next, prior to reading, the transistor 2
A positive voltage V _cc is applied to the transistors 1 and 23 to turn on these transistors 21 and 23, and the sample cell 2
A predetermined gate voltage V _g is applied to 0 and 22. As a result, in the sample cells 20 and 22, the difference between the predetermined gate voltage V _g and the threshold voltages on the writing side and the erasing side that have changed due to aging and the like. Each current corresponding to flows. These respective currents are converted into respective voltage signals V1 and V2 by the respective current / voltage conversion circuits 24 and 26, and the average voltage output circuit 2
8 is input. The average voltage output circuit 28 calculates the average voltage of the voltage signals V1 and V2 based on the input voltage signals V1 and V2, and outputs the calculated average voltage as the reference signal _Vref .

FIG. 2 is a circuit diagram showing a read circuit of the memory cell of the nonvolatile memory according to the embodiment of the present invention. In this figure, the same parts as those in FIG. 4 described above are designated by the same reference numerals, and only different points will be described. Here, independent of the current-voltage conversion circuit 16, the reference voltage V _ref is provided with a comparator 18 to be input, yet the reference voltage V _{re f} unlike the conventional case not always constant voltage, The change over time of each threshold voltage of the write-side sample cell 20 and the erase-side sample cell 22 obtained by the circuit shown in FIG. 1 is taken into consideration. The life will be greatly extended.

In the above embodiment, the average voltage output circuit 28 shown in FIG. 1 obtains the average value of the voltage signals V1 and V2, and instead of obtaining the reference voltage, the average value is taken into consideration in the non-discriminable range. Then, find the voltage optimized so that the difference between each threshold voltage and the voltage at each boundary of the non-discriminating range (called "margin") is approximately the same on the write side and erase side, and refer to this. If it is configured to be used as the signal V _ref , its life can be further extended.

Further, in the above embodiment, the two sample cells 20 and 22 in the written state and the erased state are provided, but the number of the sample cells does not have to be two, and more sample cells may be provided, or the sample cells may be provided. Alternatively, the write state and the erase state may be created alternately, and at least one of the currents flowing through the sample cells in those states may be stored to obtain the reference voltage V _ref .

[0022]

As described above, the electrically erasable nonvolatile memory of the present invention includes the sample cell, and the first current flowing through the sample cell in the written state and the second current flowing in the sample cell in the erased state. Since the threshold value corresponding to an intermediate current between the first and second currents is obtained based on the current of 1 and the judgment of '0' or '1' is made, the threshold voltage of the memory cell changes with time. It is compensated and the number of rewritable times and the service life are greatly extended.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing two sample cells included in an electrically erasable nonvolatile memory according to an embodiment of the present invention and a read circuit thereof.

FIG. 2 is a circuit diagram showing a read circuit of a memory cell in the nonvolatile memory according to the embodiment of the present invention.

FIG. 3 shows threshold voltages of MNOS and MONOS,
6 is a graph showing an example of the dependence of the writing time and the erasing time.

[FIG. 4] Content stored in a memory cell is “0” or “1”
It is the figure which showed an example of the conventional read circuit which recognizes whether it is.

5 is an explanatory diagram of a read circuit shown in FIG.

FIG. 6 is a graph showing an example of charge retention characteristics of a memory cell called MNOS after repeating writing and erasing a prescribed number of times (1 time, 10 ⁵ to 10 ⁷ times).

[Explanation of symbols]

 10, 12 Memory cell 16 Current-voltage conversion circuit 18 Comparator 20, 22 Sample cell 24, 26 Current-voltage conversion circuit 28 Average voltage output circuit

Claims (2)

[Claims] 1. A plurality of memory cells, a sample cell to be written and erased a number of times representative of the number of times of writing and erasing to each of the plurality of memory cells, and a predetermined gate voltage is applied to the sample cell in the written state. A predetermined current flowing through the sample cell and a second current flowing through the sample cell when a predetermined gate voltage is applied to the sample cell in the erased state. A second value for discriminating whether the memory cell is in a written state or an erased state by comparing with a signal value corresponding to a current value of a third current flowing in the memory cell at the time of reading by applying a base voltage; 1
Electrically erasable non-volatile, which comprises a threshold value calculation circuit for outputting a threshold value corresponding to an intermediate current value between the current value of the current and the current value of the second current. memory. 2. The threshold value operation circuit can distinguish whether the memory cell is in the written state or the erased state, and the current value at the boundary on the written state side of the current range where the memory cell is in the written state and the memory cell is in the written state. Of the third current when the memory cell is in the erased state, and the current value at the boundary of the current range on the erased side and the current value of the third current when the memory cell is in the erased state. An electrically erasable non-volatile memory, which outputs the threshold values so that the differences are substantially equal to each other.