CN1941203A - Nonvolatile semiconductor memory device - Google Patents

Abstract

A nonvolatile semiconductor memory device for storing data by accumulating charge in a floating gate (32) includes: a plurality of MOS transistors (24, 25, 26) sharing the floating gate (32). In the device, a PMOS (24) is used for coupling during writing and an n-type depletion MOS (DMOS) (25) is used for coupling during erasure. Coupling of channel inversion capacitance by the PMOS (24) is used for writing and coupling of depletion capacitance by the n-type DMOS (25) is used for erasure, thereby increasing the erase speed without increase of area, as compared to a conventional three-transistor nonvolatile memory element.

Description

Nonvolatile semiconductor memory device

Technical field

The present invention relates to Nonvolatile semiconductor memory device, in more detail, the present invention relates to mix the Nonvolatile semiconductor memory device cheaply among the LSI that is downloaded to most advanced and sophisticated standard CMOS process.

Background technology

In recent years, in the system LSI of most advanced and sophisticated standard CMOS process, be the center with the password keyword of content class, install security information require growing.Towards this installation, just at the research and utilization metal fuse.But worry to cause leakage of information after resolved.As its solution, people have expected carrying Nonvolatile semiconductor memory device low-cost, that can rewrite.

When carrying Nonvolatile semiconductor memory devices such as short-access storage in the system LSI, for standard CMOS process, need other special operation,, can not use most advanced and sophisticated technology so the technology cost increases.Therefore, requirement can mix the Nonvolatile semiconductor memory device of the cheapness among the LSI that is downloaded to most advanced and sophisticated standard CMOS process.

As the means that solve this problem, grid with the grid that can mix 1 NMOS among the LSI that is downloaded to most advanced and sophisticated standard CMOS process and 2 PMOS, form floating grid, diffusion layer region with 1PMOS, control grid during as write activity, when reading action uses, then use the CMOS nonvolatile memory of the diffusion layer region of 2PMOS when cancellation is moved, (with reference to non-patent literature 1) is widely known by the people.

Fig. 1 is the circuit diagram of the non-volatile memory device that is made of 1 nmos pass transistor and 2 PMOS transistors of expression prior art.Fig. 2 represents the sectional view of non-volatile memory device shown in Figure 1.In addition, Fig. 3 is the concise and to the point vertical view of the non-volatile memory device of expression prior art.

In Fig. 1, the 1st, control gate gated transistors (PMOS transistor), the 2nd, cancellation gridistor (PMOS transistor), the 3rd, read transistor (nmos pass transistor), the 4th, control grid, the 5th, cancellation grid, the 6th, the drain terminal of nmos pass transistor, the 7th, the source terminal of nmos pass transistor, the 8th, P type silicon substrate terminal.The 9th, floating grid (FG), it is connected with the grid of PMOS transistor 1,2 and the grid of nmos pass transistor 3.

As shown in Figure 2, nmos pass transistor 3 forms on P type silicon substrate 10, energization area and gate electrode with N type.PMOS transistor 1,2 is separately positioned on the N type trap 11,12 on the P type silicon substrate 10 energization area and gate electrode with P type.And, connect the gate electrode of nmos pass transistors 3 and the gate electrode of PMOS transistor 1,2 with floating grid (FG) 9, apply the voltage of regulation to each terminal, thereby to floating grid (FG) 9 carry out the writing of charge carrier, read, the cancellation action.

[non-patent literature 1] Richard J.McPartland, et al., " 1.25 Volt; Low Cost; Embedded FLASH Memory for Low Density Applications ", 2000 Symposiumon VLSI Circuits Digest of Technical Papers, pp.158-161.

Use the non-volatile memory device of the standard CMOS process of above-mentioned prior art, exist following problems: behind the writing speed high speed, the occupied area of memory cell just increases; And with behind the cancellation speed high speed, then the processing dimension limit with the minimum of the cancellation gridistor that constitutes memory cell clashes.So on the viewpoint of the limit of cost and physical property, the requirement for using exists writing speed, cancellation speed is difficult to problems such as high speed.

In addition, use the Nonvolatile semiconductor memory device of the standard CMOS process of prior art, the data rewriting number of times can only reach about 1000 times, exists to guarantee the reliability equal with short-access storage problems such as (the data rewriting number of times are 100,000 times).From now on, the requirement of high capacity and the data rewriting number of times more than 1000 times appears and after, on the viewpoint of cost and reliability, the data rewriting number of times of Nonvolatile semiconductor memory device will become extremely important factor.

In addition, in order to write and the high speed of cancellation, the capacity that make the control gate gated transistors is greater than reading transistor, but therefore makes the threshold voltage step-down of the state (extremity after the reliability deterioration) of electric charge 0.Like this, want to bring into play the advantage of differential scale-up version memory cell, just the threshold voltage settings of erased condition need be become extreme low, cause the problem that cancellation is excessive easily with excellent data retentivity

Summary of the invention

In order to solve above-mentioned problem, a viewpoint of the present invention, in floating grid, accumulate electric charge, in the Nonvolatile semiconductor memory device of storage data, a plurality of MOS transistor with total floating grid, wherein with writing the MOS transistor of usefulness, writing fashionablely, use the coupling (coupling) of channel capacitance; With the MOS transistor that cancellation is used, when cancellation, use the coupling of depletion capacitance.Like this, can realize the Nonvolatile semiconductor memory device of cancellation speed high speed.

If in the coupling that writes, use PMOS, in the coupling of cancellation, use depletion type (Depletion) MOS of N type, just can improve and write efficient and cancellation efficient.

If writing fashionablely, apply high bias voltage to the control grid of PMOS and the cancellation grid of depletion type MOS, thereby, inject with FN (Fowler-Nordheim) tunnel of electronics and to carry out write activity the reading in the transistor of NMOS; When cancellation, apply low bias voltage to the control grid of described PMOS, thereby in described depletion type MOS, emit with the FN tunnel of electronics and to carry out the cancellation action, just can reduce write, the cancellation electric current, so can write-once, a plurality of bit locations of cancellation, can realize writing, the high speed of cancellation.

In addition, other viewpoint of the present invention, in floating grid, accumulate in the Nonvolatile semiconductor memory device of electric charge, storage data, a plurality of MOS transistor with total floating grid, wherein the 1st control grid, only apply high bias voltage when writing and read, the 2nd control grid is only being write the fashionable high bias voltage that applies.The threshold voltage of electric charge 0 state, with the 1st control grid decision, with the current potential that writes, cancellation is corresponding, enough the 2nd control grids of energy and cancellation grid are adjusted, can carry out that high speed writes, in the cancellation and the speed adjustment differently determine the threshold voltage of electric charge 0 in addition.

If in the coupling of writing fashionable use channel capacitance, when cancellation, use the coupling of depletion capacitance, just can realize the Nonvolatile semiconductor memory device of cancellation speed high speed.Therefore, the bias voltage lower voltage that applies in order to realize required cancellation speed can be able to be improved the data rewriting number of times.

If adopt respectively with PMOS constitute the 1st control grid, with PMOS constitute the 2nd control grid, with the bit cell that the depletion type MOS of N type constitutes the cancellation grid and constitutes transistorized 4 transistor-types of reading usefulness with NMOS, just can realize that high speed writes cancellation.

In addition, other viewpoint of the present invention, it is the Nonvolatile semiconductor memory device of in floating grid, accumulating electric charge, storage data, a plurality of MOS transistor with total floating grid, these a plurality of MOS transistor, comprise: the 1MOS transistor, this MOS transistor forms at N type well region, and source electrode or drain electrode form at the diffusion layer of P type; The 2MOS transistor, this MOS transistor forms at N type well region, and source electrode or drain electrode form at the diffusion layer of N type.2MOS transistor, preferably depletion-type mos transistor.

In addition, other viewpoint of the present invention, it is the Nonvolatile semiconductor memory device of in floating grid, accumulating electric charge, storage data, a plurality of MOS transistor with total floating grid, these a plurality of MOS transistor, comprise: the 1MOS transistor, this MOS transistor forms at N type well region, and source electrode or drain electrode form at the diffusion layer of P type; The 2MOS transistor, this MOS transistor forms at N type well region, and source electrode or drain electrode form at the diffusion layer of P type; The 3MOS transistor, this MOS transistor forms at N type well region, and source electrode or drain electrode form at the diffusion layer of N type; The 4MOS transistor, this transistor constitutes with NMOS.

After adopting Nonvolatile semiconductor memory device of the present invention, for 3 transistor-type non-volatile memory devices of prior art, can not increase memory component area make cancellation speed high speed.In addition, because can make cancellation speed high speed, so realizing and during cancellation speed that prior art is equal, can make to apply the bias voltage lower voltage, thereby can improve the data rewriting number of times.

Description of drawings

Fig. 1 is the circuit diagram of the non-volatile memory device of prior art.

Fig. 2 is the sectional view of the non-volatile memory device of prior art.

Fig. 3 is the concise and to the point vertical view of the non-volatile memory device of prior art.

Fig. 4 is the circuit diagram of the non-volatile memory device of 3 transistor-types.

Fig. 5 be expression 3 transistor-types non-volatile memory device write fashionable floating grid potential (V _FG) volume ratio (α, β) figure of interdependence.

Fig. 6 is the sectional view of N type DMOS capacitor.

Fig. 7 is the circuit diagram of the non-volatile memory device in the 1st embodiment of the present invention.

Fig. 8 is the sectional view of the non-volatile memory device in the 1st embodiment of the present invention.

Fig. 9 is the sectional view of the N type DMOS capacitor used of C-V characteristic measurement, PMOS capacitor, NMOS capacitor.

Figure 10 (a) is that N type DMOS capacitor, (b) are that PMOS capacitor, (c) are NMOS capacitor C-V performance plots separately.

Figure 11 is the circuit diagram of the Nonvolatile semiconductor memory device of the differential unit formation in the 2nd embodiment of the present invention.

Figure 12 is the circuit diagram that writes " 1 " action that the differential unit in expression the 2nd embodiment of the present invention constitutes.

Figure 13 is the circuit diagram that writes " 0 " action that the differential unit in expression the 2nd embodiment of the present invention constitutes.

Figure 14 is the circuit diagram of reading action that the differential unit in expression the 2nd embodiment of the present invention constitutes.

Figure 15 is the circuit diagram of the non-volatile memory device in the 3rd embodiment of the present invention.

Figure 16 is the sectional view of the non-volatile memory device in the 3rd embodiment of the present invention.

Figure 17 is the circuit diagram of the non-volatile memory device in the 4th embodiment of the present invention.

Figure 18 is the circuit diagram of the Nonvolatile semiconductor memory device of the differential unit formation in expression the 5th embodiment of the present invention.

Embodiment

Below, with reference to accompanying drawing, tell about embodiments of the present invention.

At first, be example with the Nonvolatile semiconductor memory device of 3 transistor-types, tell about optimal structure, as the optimal structure of cancellation grid as the control grid.

(about the explanation of control grid)

Fig. 4 represents the circuit diagram of the non-volatile memory device of 3 transistor-types.In Fig. 4, the 13rd, control grid (CG), the 14th, cancellation grid (EG), the 19th, floating grid (FG), the 15th, NMOS reads transistor, the 16th, the drain terminal of nmos pass transistor, the 17th, the source terminal of nmos pass transistor, the 18th, P type silicon substrate terminal, C ₁Be the channel capacitance of control gate gated transistors, C ₂Be the channel capacitance of cancellation gridistor, C ₃Be to read transistorized channel capacitance.

During write activity, apply high bias voltage, after source terminal 16 and drain terminal 17 ground connection, in reading out in transistor 15, utilize the tunnel to inject electronics, write to floating grid (FG) 19 to control grid (CG) 13 and cancellation grid (EG) 14.At this moment, in order to improve the injection efficiency of electronics, need (capacity be C with the control gate gated transistors ₁) (capacity is C with reading transistor ₃) volume ratio be designed to bigger.Like this, having control gate gated transistors, cancellation gridistor, reading in the Nonvolatile semiconductor memory device of transistorized 3 transistor-types,, tell about optimal structure as the control gate gated transistors.Read transistor and be made as NMOS, but be not limited to NMOS.

At first, when writing beginning, preserve law according to electric charge, following formula is set up.

[mathematical expression 1]

Q＝C ₁·(V _FG-V _CG)+C ₂·(V _FG-V _EG)+C ₃·V _FG …(1)

[mathematical expression 2]

$V_{\mathrm{FG}}=\frac{({\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="A20061015401700271.png,A20061015401700281.png"\; state="\{\{state\}\}">C</figure-callout>}}_1/C_2)V_{\mathrm{CG}}+{\mathrm{<figure-callout\; id="1"\; label="V\; EG"\; filenames="A20061015401700271.png,A20061015401700281.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{EG}}}{1+({\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="A20061015401700271.png,A20061015401700281.png"\; state="\{\{state\}\}">C</figure-callout>}}_1/C_2)+(C_3/C_2)}---\left(2\right)$

Here, Q is the electric charge in the floating grid (FG) 19, V _CGBe the control gate pole tension, V _EGBe the cancellation grid voltage, V _FGBe floating grid potential, C ₁Be the channel capacitance of control gate gated transistors, C ₂Be the channel capacitance of cancellation gridistor, C ₃Be to read transistorized channel capacitance.In formula (1), during Q=0, become formula (2).With C ₁With C ₂Volume ratio (C ₁/ C ₂) be defined as α, C ₃With C ₂Volume ratio (C ₃/ C ₂) be defined as β.

Fig. 5 represents to write fashionable (V _CG=V _EG=8.5V) floating grid potential V _FGVolume ratio (α, β) interdependence.As shown in Figure 5, if make C ₁/ C ₂(=α) increases, C ₃/ C ₂(=β) reduces, then V _FGJust becoming big, reading transistor 15---the voltage that applies between the grid of NMOS and the P type silicon substrate terminal 18 becomes big, cancellation speed high speed.

The control gate gated transistors can be considered two of depletion type MOS (being designated hereinafter simply as " DMOS ") of PMOS and N type.

Fig. 6 represents the sectional view of N type DMOS capacitor.Here, the 20th, the gate terminal of N type DMOS capacitor, the 21st, the N type well terminal (diffusion layer terminal) of N type DMOS capacitor, the 22nd, N type well region, the 23rd, P type silicon substrate.N type DMOS capacitor shown in Figure 6 can not append mask ground and makes in CMOS technology.

(capacity is C at the control gate gated transistors ₁) in use N type DMOS after because during write activity, move wasting under the state, so capability value can only obtain about 1/3 of oxide film capacity.In other words, (capacity is C to the control gate gated transistors ₁) (capacity is C with reading transistor ₃) volume ratio diminish, pass to floating grid potential (V _FG) voltage reduce, so the writing speed deterioration.On the other hand, (capacity is C at the control gate gated transistors ₁) in use PMOS after owing to move under inverted status, so can obtain the channel inversion capacity, (capacity is C to obtain bigger control gate gated transistors ₁) and (capacity is C to read transistor ₃) volume ratio diminish.So as writing fashionable coupled transistor, (capacity is C to be preferably in the control gate gated transistors ₁) the middle PMOS that adopts.

(about the explanation of cancellation grid)

As mentioned above, if (capacity is C at the control gate gated transistors ₁) in adopt PMOS, so to the coupling efficiency height of the floating grid (FG) 19 of control grid (CG) 13.On the other hand, told about that (capacity is C as the cancellation gridistor ₂), among NMOS and the PMOS which is all right.(capacity is C to read transistor ₁) be decided to be NMOS, but be not limited to NMOS.

At first, during the cancellation action, preserve law according to electric charge, following formula is set up.

[mathematical expression 3]

Q＝C ₁·(V _FG-V _CG)+C ₂·(V _FG-V _EG)+C ₃·V _FG …(3)

[mathematical expression 4]

$V_{\mathrm{FG}}=\frac{{\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="A20061015401700271.png,A20061015401700281.png"\; state="\{\{state\}\}">C</figure-callout>}}_1\&CenterDot;V_{\mathrm{CG}}+C_2\&CenterDot;V_{\mathrm{EQ}}+\mathrm{<figure-callout\; id="1"\; label="Q\; C"\; filenames="A20061015401700271.png,A20061015401700281.png"\; state="\{\{state\}\}">Q</figure-callout>}}{C_{}}---\left(4\right)$

[mathematical expression 5]

$V_{\mathrm{FG}}=\frac{V_{\mathrm{EG}}+(Q/C_2)}{1+({\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="A20061015401700271.png,A20061015401700281.png"\; state="\{\{state\}\}">C</figure-callout>}}_1/C_2)+(C_3/C_2)}---\left(5\right)$

Here, C ₁Be the channel capacitance of control gate gated transistors, C ₂Be the channel capacitance of cancellation gridistor, C ₃Be to read transistorized channel capacitance.

V _CGDuring=0V, formula (4) becomes formula (5).By formula (5) as can be known: α (=C ₁/ C ₂) and β (=C ₃/ C ₂) become big after, floating grid potential (V _FG) diminish, (capacity is C to impose on the cancellation gridistor ₂) the voltage of grid---floating grid (FG) 19 and cancellation grid 14---between the N type trap become big, cancellation speed high speed.During cancellation, apply 8.5V for example for cancellation grid 14, apply 0V for control grid 13.(capacity is C at the cancellation gridistor ₂) in when using PMOS, under this bias condition, PMOS moves under inverted status, so capability value is bigger.On the other hand, (capacity is C at the cancellation gridistor ₂) in when using NMOS, under this bias condition, N type DMOS moves under spent condition, so capability value is less.Therefore, (capacity is C at the cancellation gridistor ₂) in when using NMOS, can strengthen α and β, so compare when using PMOS, can reduce floating grid potential (V _FG).Like this, (capacity is C to impose on the cancellation gridistor ₂) the voltage of grid---floating grid (FG) 19 and cancellation grid 14---between the N type trap become big, cancellation speed high speed.At this moment, at the grid of N type DMOS---the overlay area and the channel region of (S/D) diffusion layer leaked in floating grid (FG) 19 and source, utilizes the FN tunnel of electronics to emit and carries out cancellation.Therefore, (capacity is C to be preferably in the cancellation gridistor ₂) the middle N type DMOS that adopts.

As mentioned above, preferably (capacity is C at the control gate gated transistors respectively ₁) the middle PDMOS that adopts, (capacity is C at the cancellation gridistor ₂) the middle N type DMOS that adopts.

As shown in Figure 5, writing near fashionable volume ratio β=3, be α＞8～9, the voltage of floating grid can be set for very high, and the efficient of write activity is good.At this moment, in control grid and cancellation grid, form raceway groove, become the area ratio of volume ratio=grid.Therefore, preferably make the gate area of cancellation gridistor: the gate area of control gate gated transistors=1: 2～4.In addition, the gate area of cancellation gridistor: the gate area of control gate gated transistors=1: 8～9 item are better.Act on an example, preferably make the gate area of cancellation gridistor: read transistorized gate area: the gate area of control gate gated transistors=1: 3: 9.In addition, during cancellation, when the cancellation grid is DMOS, formation wastes layer, is the area of volume ratio ≠ grid, the gate area of cancellation gridistor: the gate area of control gate gated transistors=1: 9 o'clock, volume ratio becomes about 1: 27, can obtain volume ratio effectively.

" the 1st embodiment "

Fig. 7 represents the circuit diagram of the non-volatile memory device in the 1st embodiment of the present invention, and Fig. 8 represents its sectional view.Non-volatile memory device of the present invention, with control gate gated transistors 24 for PMOS, read transistor 26 and constitute for 3 transistors of N type DMOS for NMOS, cancellation gridistor 25, with non-volatile memory device of the present invention, be called " PMOS-NMOS-DMOS (PND) unit ".

In Fig. 7, the 27th, control grid (CG), the 28th, cancellation grid (EG), 29NMOS transistor drain terminal, the 30th, the source terminal of nmos pass transistor, the 31st, P type silicon substrate terminal, the 32nd, floating grid (FG).In Fig. 8,33 and 34 is N type well regions, the 35th, and P type silicon substrate.The polysilicon gate of PMOS24, NMOS26, N type DMOS25 is electrically connected, and forms the floating grid (FG) 32 of non-volatile memory device.The N type well region 34 of PMOS24 becomes control grid (CG) 27; The N type well region 33 of N type DMOS25 becomes cancellation grid (EG) 28.Here, N type DMOS25 can not append mask ground and makes in CMOS technology.

Write is to read transistor---in the whole raceway groove of NMO transistor 26, the FN tunnel that carries out electronics injects, cancellation then is the grid at N type DMOS25---the overlay area and the channel region of (S/D) diffusion layer leaked in floating grid (FG) 32 and source, and the FN tunnel that carries out electronics discharges.During cancellation, under spent condition, make the cancellation gridistor---N type DMOS25 action, make capacity between the N type well region 33 of floating grid (FG) 32 and N type DMOS25 reduce (to accumulate capacity about 28%), thereby can make the voltage between the N type well region 33 that imposes on floating grid (FG) 32 and N type DMOS25 become big, make cancellation speed than prior art high speed.

Fig. 9 represents the sectional view of N type DMOS capacitor that the C-V characteristic measurement uses, PMOS capacitor, NMOS capacitor.Here, the 36th, the well terminal (diffusion layer terminal) of N type DMOS capacitor, the 37th, the gate terminal of N type DMOS capacitor, the 38th, N type well region, the 39th, the well terminal of PMOS capacitor (diffusion layer terminal), the 40th, the gate terminal of PMOS capacitor, the 41st, N type well region, the 42nd, the base-plate terminal of NMOS capacitor (diffusion layer terminal), the 43rd, the gate terminal of NMOS capacitor, the 44th, P type silicon substrate.

Figure 10 is illustrated in the CMOS logic process of 110nm, the measurement result of the C-V characteristic of (a) N type DMOS capacitor of the PND unit of the I/O transistor fabrication of formation use 3.3V, (b) PMOS capacitor, (c) NMOS capacitor.The PMOS capacitor is because easily by n ⁺And p ⁺Both of electronics and hole are supplied with in the diffusion region, so its C-V curve is different with the C-V curve of N type DMOS capacitor.In contrast, N type DMOS capacitor is only supplied with electronics by near n+ diffusion region.Shown in the C-V curve of the PMOS capacitor of Figure 10 (b) since along with-5V～+ increase of the bias voltage of 5V, the silicon face state variation under the gate electrode becomes inverted status, spent condition, accumulated state, so that capacitor is changed to is large and small, big.In contrast, the C-V curve of the DMOS capacitor of Figure 10 (a), because under the same conditions, the silicon face state variation becomes spent condition, accumulated state, so that capacitor is changed to is little, big.By Figure 10 (a) as can be known: the potential difference (PD) between the gate terminal 37 of DMOS capacitor and the N type well terminal 36 is-capacity of (spent condition) during 5V is to accumulate about 28% of capacity.In the PND unit, utilize this characteristic.

" the 2nd embodiment "

Figure 11 represents the circuit diagram of the Nonvolatile semiconductor memory device that the differential unit in the 2nd embodiment of the present invention constitutes.Be called T (True) bit with one in the differential bit cell, another is called B (Bar) bit.Here, the 45th, the control gate gated transistors of T bit (PMOS transistor), the 46th, the cancellation gridistor of T bit (N type DMOS transistor), the 47th, the T bit read transistor (nmos pass transistor), the 48th, load PMOS transistor, the 49th, the control gate gated transistors of B bit (PMOS transistor), the 50th, the cancellation gridistor of B bit (N type DMOS transistor), the 51st, read transistor (nmos pass transistor), the 52nd, load PMOS transistor, the 53rd, bit line (BL), the 54th, the bit line bar (/BL), and the 55th, sensor amplifier.

Figure 12 is the circuit diagram that writes " 1 " action that the differential unit in expression the 2nd embodiment of the present invention constitutes.Writing in " 1 " action in differential unit constitutes carried out write activity with the T bit, carries out the cancellation action with the B bit.The VDD of supply voltage is read out control signal, and (/RD) input, load PMOS transistor 48,52 disconnects.

At first, the write activity of the PND unit of expression T bit.Apply 8.5V for respectively the control grid CG (T) and the cancellation grid EG (T) of the PND unit of T bit.At this moment, because with the PMOS of control gate gated transistors 45 and volume ratio design very big of reading the NMOS of transistor 47, so the high voltage transfer near 8.5V is given floating grid (FG), reading transistor 47---in the raceway groove of NMOS, utilize the FN tunnel, inject electronics to floating grid, threshold voltage uprises, and forms one state.

Then, the cancellation action of the PND unit of expression B bit.Apply 8.5V for the cancellation grid EG (T) of the PND unit of B bit, apply 0V for control grid CG (T).At this moment, because very big with the volume ratio design of the N type DMOS of the PMOS of control gate gated transistors 49 and cancellation gridistor 50, so the 0V of floating grid potential Be Controlled grid potential pulling, under the effect of the accumulated electrons amount in floating grid (FG), become-0.5V about.Therefore, in N type DMOS50, floating grid (FG) and N type trap---between the cancellation grid (EG), be applied in high voltage, the electronics of being accumulated by floating grid (FG) is from the N type well terminal of floating grid (FG) to N type DMOS50---cancellation grid EG (B) carries out the FN tunnel and emits.

Figure 13 is the circuit diagram that writes " 0 " action that the differential unit in expression the 2nd embodiment of the present invention constitutes.At this moment, VDD is read out control signal (/RD) input, 48,52 disconnections of load PMOS transistor.It is identical when bias condition is opposite with the B bit with the T bit that writes " 0 " action.

Figure 14 is the circuit diagram of reading action that the differential unit in expression the 2nd embodiment of the present invention constitutes.Suppose to write " 1 " data, write " 0 " data to the B bit to the T bit of differential PND unit.Reading when action, as shown in figure 14,0V be transfused to read control signal (/RD), load PMOS transistor 48,52 disconnects.In addition, apply 1.2V and 0V for respectively the control grid CG (T) and the cancellation grid EG (T) of the PND unit of T bit.At this moment, because the memory cell of T bit becomes high threshold voltage, so disconnect, bit line (BL) 53 becomes VDD; The memory cell of B bit becomes low threshold voltage, thus connect,, the bit line bar (/BL) 54 become 0V.BL53 and/BL54, be transfused to sensor amplifier 55, read amplifying signal.

In addition, the voltage that the scope of 7～10V will be in fact equated with the supply voltage of the logical circuit of LSI as the 1st bias voltage is during as the 2nd bias voltage (being lower than the 1st bias voltage), for example can be in the PND unit of T bit, when writing, to control grid CG (T) and cancellation grid EG (T), apply the 1st bias voltage; When cancellation,, apply the 2nd bias voltage to control grid CG (T).

" the 3rd embodiment "

Figure 15 represents the circuit diagram of the non-volatile memory device in the 3rd embodiment of the present invention.Here, the 89th, program gridistor (PMOS transistor), the 90th, control gate gated transistors (PMOS transistor), the 91st, cancellation gridistor (PMOS transistor), the 92nd, read transistor (nmos pass transistor), the 93rd, program grid (PG), the 94th, control grid (CG), the 95th, cancellation grid (EG), the 96th, the drain terminal of nmos pass transistor, the 97th, the source terminal of nmos pass transistor, the 98th, P type silicon substrate terminal, the 99th, floating grid (FG).

Figure 16 represents the sectional view of the non-volatile memory device in the 3rd embodiment of the present invention.Here, 100,101 and 102 is N type well regions, the 103rd, and P type silicon substrate.For the non-volatile memory device of 3 transistor-types, use the program grid as 4 additional transistors of another control grid, formation non-volatile memory device.

Write activity applies high bias voltage for program grid (PG) 93, control grid (CG) 94, cancellation grid (EG) 95, in the NMOS that reads transistor 92, utilizes the FN tunnel, injects electronics to floating grid (FG) 99.The cancellation action applies 0V for program grid (PG) 93 and control grid (CG) 94, applies high bias voltage for cancellation grid (EG) 95, in cancellation gridistor 91, utilizes the FN tunnel, discharges electronics by floating grid (FG) 99 to cancellation grid (EG) 95.Read action, apply 0V for program grid (PG) 93, cancellation grid (EG) 95, apply common voltage for control grid (CG) 94, according to read transistor 92 whether the situation of conducting carry out.

After adopting the structure of Figure 15, the threshold voltage of electric charge 0 state, the volume ratio that is used in and reads transistor 92 is not higher than the state control gate gated transistors decision of setting down of program gridistor 89, with the current potential that writes, cancellation is corresponding, can use the capacity adjustment of program gridistor 89 and cancellation gridistor 91, can be when carrying out the high speed cancellation, writing and the speed adjustment differently determine the threshold voltage of the state (extremity after the reliability deterioration) of electric charge 0.

" the 4th embodiment "

Figure 17 represents the circuit diagram of the non-volatile memory device in the 4th embodiment of the present invention.Here, the 104th, program gridistor (PMOS transistor), the 105th, control gate gated transistors (PMOS transistor), the 106th, cancellation gridistor (nmos pass transistor), the 107th, read transistor (nmos pass transistor), the 108th, program grid (PG), the 109th, control grid (CG), the 110th, cancellation grid (EG), the 111st, the drain terminal of nmos pass transistor, the 112nd, the source terminal of nmos pass transistor, the 113rd, P type silicon substrate terminal, the 114th, floating grid (FG).Writing fashionablely, using the coupling of channel capacitance; When cancellation, use the coupling of depletion capacitance, thereby can make write, cancellation speed high speed.

In addition, respectively the 1st, the 2nd and the 3rd bias voltage is decided to be V1, V2 and V3, when making V1＞V2 and V3＞V2, can when write activity, applies V1 to program grid (PG) 108 and control grid (CG) 109; When reading action, apply V2 to control grid (CG) 109; When the cancellation action, apply V3 to cancellation grid (EG) 110.

" the 5th embodiment "

Figure 18 represents the Nonvolatile semiconductor memory device that the differential unit in the 5th embodiment of the present invention constitutes.With differential bit cell,, make the differential unit structure with the 4th embodiment shown in Figure 17.Here, the 115th, the program gridistor of T bit (PMOS transistor), the 116th, the control gate gated transistors of T bit (PMOS transistor), the 117th, the cancellation gridistor of T bit (N type DMOS transistor), the 118th, the T bit read transistor (nmos pass transistor), 119 and 124 is load PMOS transistors, the 120th, the program gridistor of B bit (PMOS transistor), the 121st, the control gate gated transistors of B bit (PMOS transistor), the 122nd, the cancellation gridistor of B bit (N type DMOS transistor), the 123rd, the B bit read transistor (nmos pass transistor), the 125th, bit line (BL), the 126th, the bit line bar (/BL), and the 127th, sensor amplifier.

After adopting the 5th embodiment of the present invention, with the non-volatile memory cells in the 4th embodiment of the present invention, as the differential unit structure, thereby can differently determine to keep the threshold voltage of electric charge 0 of the high reliability of differential unit with the speed adjustment, can realize bringing into play the Nonvolatile semiconductor memory device of data retention characteristics excellence of the advantage of differential motion amplifying unit.

In addition, the Nonvolatile semiconductor memory device of the respective embodiments described above, the MOS transistor made from the technology identical with the MOS transistor of the output input circuit that forms LSI constitutes, thereby can realize cheap Nonvolatile semiconductor memory device.Specifically, make the gate oxidation thickness of each MOS transistor that constitutes non-volatile memory cells, become and forms the thick equal in fact thickness of grid oxidation film of MOS transistor of the output input circuit of LSI, for example 7～8nm.

The Nonvolatile semiconductor memory device that the present invention relates to is the Nonvolatile semiconductor memory device cheaply that can mix among the LSI that is downloaded to most advanced and sophisticated standard CMOS process, in the information of circuit repairing and private data etc. is installed, is of great use.

Claims (31)

1, a kind of Nonvolatile semiconductor memory device is accumulated electric charge and is stored data in floating grid,

A plurality of MOS transistor with total floating grid wherein with writing the MOS transistor of usefulness, are being write fashionablely, use the coupling of channel capacitance; With the MOS transistor that cancellation is used, when cancellation, use the coupling of depletion capacitance.

2, Nonvolatile semiconductor memory device as claimed in claim 1 is characterized in that: use PMOS in the coupling of said write, use the depletion type MOS of N type in the coupling of described cancellation.

3, Nonvolatile semiconductor memory device as claimed in claim 1 is characterized in that: reading transistor is NMOS.

4, Nonvolatile semiconductor memory device as claimed in claim 1 is characterized in that: be formed on P type silicon substrate and the N type well region.

5, Nonvolatile semiconductor memory device as claimed in claim 1 is characterized in that:

Write fashionablely, apply high bias voltage, thereby, inject with the FN tunnel of electronics and to carry out write activity the reading in the transistor of NMOS to the control grid of PMOS and the cancellation grid of depletion type MOS;

During cancellation, apply low bias voltage, thereby in described depletion type MOS, emit with the FN tunnel of electronics and to carry out the cancellation action to the control grid of described PMOS.

6, a kind of Nonvolatile semiconductor memory device, with the described Nonvolatile semiconductor memory device of claim 1, make the differential unit structure, make the drain electrode of reading the usefulness MOS transistor separately of the 1st bit cell and the 2nd bit cell, be connected with the input of differential amplifier.

7, Nonvolatile semiconductor memory device as claimed in claim 1 is characterized in that: the MOS transistor made from the technology identical with the MOS transistor of the output input circuit that forms LSI constitutes.

8, a kind of Nonvolatile semiconductor memory device is accumulated electric charge and is stored data in floating grid,

A plurality of MOS transistor with total floating grid, wherein the 1st control grid only applies high bias voltage when writing and read, and the 2nd control grid is only being write the fashionable high bias voltage that applies.

9, Nonvolatile semiconductor memory device as claimed in claim 8 is characterized in that: writing fashionablely, using the coupling of channel capacitance; When cancellation, use the coupling of depletion capacitance.

10, Nonvolatile semiconductor memory device as claimed in claim 8 is characterized in that: reading transistor is NMOS.

11, Nonvolatile semiconductor memory device as claimed in claim 8 is characterized in that: be formed in P type silicon substrate and the N type well region.

12, Nonvolatile semiconductor memory device as claimed in claim 8, it is characterized in that: bit cell with 4 transistor-types, in the bit cell of this 4 transistor-type, constitute described the 1st control grid, constitute described the 2nd control grid, constitute with the depletion type MOS formation cancellation grid of N type, with NMOS and read the transistor of usefulness with PMOS respectively with PMOS.

13, a kind of Nonvolatile semiconductor memory device, with the described Nonvolatile semiconductor memory device of claim 8, make the differential unit structure, make the drain electrode of reading the usefulness MOS transistor separately of the 1st bit cell and the 2nd bit cell, be connected with the input of differential amplifier.

14, Nonvolatile semiconductor memory device as claimed in claim 8 is characterized in that:

The MOS transistor made from the technology identical with the MOS transistor of the output input circuit that forms LSI constitutes.

15, a kind of Nonvolatile semiconductor memory device is accumulated electric charge, is stored data in floating grid, have a plurality of MOS transistor of total floating grid,

Described a plurality of MOS transistor comprises:

1MOS transistor, this MOS transistor are formed on N type well region, and source electrode or drain electrode are formed by the diffusion layer of P type;

2MOS transistor, this MOS transistor are formed on N type well region, and source electrode or drain electrode are formed by the diffusion layer of N type.

16, Nonvolatile semiconductor memory device as claimed in claim 15 is characterized in that: described 2MOS transistor is a depletion-type mos transistor.

17, Nonvolatile semiconductor memory device as claimed in claim 16 is characterized in that: the area ratio of the transistorized grid of the described described 1MOS of 2MOS transistor AND gate came down to 1: 9.

18, Nonvolatile semiconductor memory device as claimed in claim 15 is characterized in that: also have the 3MOS transistor of total described floating grid, according to the transistorized current value of described 3MOS, carry out the action of reading of data.

19, Nonvolatile semiconductor memory device as claimed in claim 18 is characterized in that: the area ratio of the transistorized grid of the described described 3MOS of 2MOS transistor AND gate comes down to 1: 2～4.

20, Nonvolatile semiconductor memory device as claimed in claim 18 is characterized in that: the area ratio of the transistorized grid of the described described 1MOS of 3MOS transistor AND gate comes down to 1: 2～4.

21, Nonvolatile semiconductor memory device as claimed in claim 18 is characterized in that: the area ratio of the transistorized grid of the described described 1MOS of 3MOS transistor AND gate of described 2MOS transistor AND gate came down to 1: 3: 9.

22, a kind of Nonvolatile semiconductor memory device, with the described Nonvolatile semiconductor memory device of claim 18, make the differential unit structure, make the 1st bit cell and the 2nd bit cell described 3MOS transistor drain separately, be connected with the input of differential amplifier.

23, Nonvolatile semiconductor memory device as claimed in claim 18, it is characterized in that: the described the 1st, the 2nd and the transistorized gate oxidation film thickness of 3MOS, equate with the gate oxidation film thickness of the MOS transistor of the output input circuit that forms LSI in fact.

24, Nonvolatile semiconductor memory device as claimed in claim 18 is characterized in that: the described the 1st, the 2nd and the transistorized gate oxidation film thickness of 3MOS, and be 7～8nm.

25, Nonvolatile semiconductor memory device as claimed in claim 15 is characterized in that:

When writing, source electrode or drain electrode to source electrode or the drain electrode and the transistorized N type of described 2MOS of the transistorized P type of described 1MOS apply the 1st bias voltage;

When cancellation,, apply the 2nd bias voltage to the source electrode or the drain electrode of the transistorized P type of described 1MOS;

Described the 1st bias voltage is higher than described the 2nd bias voltage.

26, Nonvolatile semiconductor memory device as claimed in claim 25 is characterized in that: described the 1st bias voltage is the scope of 7～10V.

27, Nonvolatile semiconductor memory device as claimed in claim 25 is characterized in that: described the 2nd bias voltage equates with the supply voltage of the logical circuit of LSI in fact.

28, a kind of Nonvolatile semiconductor memory device is accumulated electric charge and is stored data in floating grid, have a plurality of MOS transistor of total floating grid,

Described a plurality of MOS transistor comprises:

1MOS transistor, this MOS transistor are formed on N type well region, and source electrode or drain electrode are formed by the diffusion layer of P type;

2MOS transistor, this MOS transistor are formed on N type well region, and source electrode or drain electrode are formed by the diffusion layer of P type;

3MOS transistor, this MOS transistor are formed on N type well region, and source electrode or drain electrode are formed by the diffusion layer of N type;

The 4MOS transistor, this transistor constitutes with NMOS.

29, Nonvolatile semiconductor memory device as claimed in claim 28 is characterized in that:

When write activity,, apply the 1st bias voltage to the described the 1st and the transistorized N type of 2MOS well region;

When reading action,, apply the 2nd bias voltage to the transistorized N type of described 2MOS well region;

When the cancellation action,, apply the 3rd bias voltage to the transistorized N type of described 3MOS well region;

The the described the 1st and the 3rd bias voltage is higher than described the 2nd bias voltage.

30, a kind of Nonvolatile semiconductor memory device, with the described Nonvolatile semiconductor memory device of claim 28, make the differential unit structure, make the 1st bit cell and the 2nd bit cell described 4MOS transistor drain separately, be connected with the input of differential amplifier.

31, Nonvolatile semiconductor memory device as claimed in claim 28, it is characterized in that: the described the the 1st, the 2nd, the 3rd and the transistorized gate oxidation film thickness of 4MOS, equate with the gate oxidation film thickness of the MOS transistor of the output input circuit that forms LSI in fact.

Images