CN111883530B - Capacitor and preparation method thereof - Google Patents

Capacitor and preparation method thereof Download PDF

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Publication number
CN111883530B
CN111883530B CN202011037143.1A CN202011037143A CN111883530B CN 111883530 B CN111883530 B CN 111883530B CN 202011037143 A CN202011037143 A CN 202011037143A CN 111883530 B CN111883530 B CN 111883530B
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capacitor
electrode
well
drain
substrate
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CN111883530A (en
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陈明睿
任雪琪
汪文婷
姚子凤
刘苑
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Nexchip Semiconductor Corp
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Nanjing Crystal Drive Integrated Circuit Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805—Capacitors only
    • H01L27/0811—MIS diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention provides a capacitor, which comprises two MOS capacitors formed on the same substrate, wherein the maximum application voltages of the two MOS capacitors are different and are both smaller than the maximum application voltage of the capacitor. The invention enlarges the capacitance value by connecting the two MOS capacitors formed on the same substrate in series, further improves the grade of the application voltage of the capacitor, has lower manufacturing cost, and can improve the unit capacitance value of the capacitor by designing various parameters of the two MOS capacitors, thereby reducing the size of the capacitor and improving the performance of the capacitor. Based on the capacitor, the invention also provides a preparation method of the capacitor.

Description

Capacitor and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a capacitor and a preparation method thereof.
Background
At present, capacitors are widely used in large-scale integrated circuits (e.g., mixed signal circuits, radio frequency circuits, analog circuits, etc.). The capacitor generally includes a Metal-Oxide-Metal (MOM) capacitor, a Metal-insulator-Metal (MIM) capacitor, and a Metal-Oxide-Semiconductor (MOS) capacitor.
In order to increase the application voltage of the capacitor, it is preferable to enlarge the capacitance. The MOM capacitor is a gear shaping structure, the single-layer capacitance value of the MOM capacitor is very small, and the capacitance value can be enlarged only by multiple layers, but the size of the MOM capacitor is increased inevitably, and the MOM capacitor does not accord with the development trend of the existing miniaturized device; if the capacitance value of the MIM capacitor needs to be enlarged, a photomask needs to be added in the preparation process, so that the manufacturing cost is very expensive; the capacitance of the MOS capacitor is limited and cannot be further increased.
Disclosure of Invention
The invention aims to provide a capacitor and a preparation method thereof, which can enlarge the application voltage of the capacitor by improving the capacitance value of the capacitor.
In order to achieve the above object, the present invention provides a capacitor, including two MOS capacitors formed on the same substrate, the two MOS capacitors being connected in series, the maximum application voltages of the two MOS capacitors being different and both being less than the maximum application voltage of the capacitor, the sum of the breakdown voltages of the two MOS capacitors being greater than the maximum application voltage of the capacitor;
each MOS capacitor comprises a source electrode, a drain electrode, a body electrode and a grid electrode, wherein the source electrode, the drain electrode and the body electrode are all positioned in the substrate, and the grid electrode is positioned on the substrate and positioned between the corresponding source electrode and the corresponding drain electrode;
one of the two MOS capacitors is an NMOS capacitor, the other one is a PMOS capacitor, the NMOS capacitor is connected with a grid electrode of the PMOS capacitor, a source electrode, a drain electrode and a body electrode of the NMOS capacitor are connected and then serve as a first electrode of the capacitor, and a source electrode, a drain electrode and a body electrode of the PMOS capacitor are connected and then serve as a second electrode of the capacitor.
Optionally, the unit capacitance value of the capacitor is greater than the unit capacitance value of each MOS capacitor.
Optionally, the two MOS capacitors are manufactured synchronously.
Optionally, the areas of the overlapping regions of the gates of the two MOS capacitors and the substrate are not equal.
Optionally, a gate oxide layer is formed between the gate of each MOS capacitor and the substrate, and the gate oxide layer of the MOS capacitor with the higher maximum application voltage is thicker in the two MOS capacitors.
Optionally, a P-well and an N-well are formed in the substrate, the source, the drain, and the bulk of the NMOS capacitor are all located in the P-well, and the source, the drain, and the bulk of the PMOS capacitor are all located in the N-well.
Optionally, the first electrode is used for grounding, the second electrode is used for connecting a positive voltage, and the breakdown voltage of the N-well is greater than the maximum application voltage of the capacitor.
The invention also provides a preparation method of the capacitor, which comprises the following steps:
providing a substrate;
forming two MOS capacitors on the substrate, wherein the maximum application voltages of the two MOS capacitors are different and are both smaller than the maximum application voltage of the capacitor; and the number of the first and second groups,
connecting two MOS capacitors in series;
the method comprises the following steps of forming a P well and an N well in a substrate, and forming two MOS capacitors on the substrate, wherein the step of forming the P well and the N well in the substrate comprises the following steps:
forming a source electrode, a drain electrode and a body electrode in the P well and the N well respectively; and the number of the first and second groups,
forming two gates on the P well and the N well respectively, wherein each gate is positioned between the corresponding source and drain, the source, the drain and the body in the P well and the gate on the P well form an NMOS capacitor, and the source, the drain and the body in the N well and the gate on the N well form a PMOS capacitor;
the step of connecting two MOS capacitors in series comprises the following steps:
connecting the NMOS capacitor with the grid of the PMOS capacitor; and the number of the first and second groups,
and connecting the source electrode, the drain electrode and the body electrode of the NMOS capacitor to serve as a first electrode of the capacitor, and connecting the source electrode, the drain electrode and the body electrode of the PMOS capacitor to serve as a second electrode of the capacitor.
The capacitor provided by the invention comprises two MOS capacitors formed on the same substrate, and the maximum application voltages of the two MOS capacitors are different and are both smaller than the maximum application voltage of the capacitor. The invention enlarges the capacitance value by connecting the two MOS capacitors formed on the same substrate in series, further improves the grade of the application voltage of the capacitor, has lower manufacturing cost, and can improve the unit capacitance value of the capacitor by designing various parameters of the two MOS capacitors, thereby reducing the size of the capacitor and improving the performance of the capacitor. Based on the capacitor, the invention also provides a preparation method of the capacitor.
Drawings
FIG. 1a is a schematic cross-sectional view of a capacitor according to an embodiment of the present invention;
FIG. 1b is an equivalent circuit diagram of a capacitor according to an embodiment of the present invention;
fig. 2 is a circuit diagram of a capacitor applied to a power clamp ESD protection circuit according to an embodiment of the present invention;
FIG. 3 is a flow chart of a method for fabricating a capacitor according to an embodiment of the present invention;
wherein the reference numerals are:
a 10-NMOS capacitor; 101-a first gate oxide layer; 11-PMOS capacitor; 111-a second gate oxide layer; 20-a substrate;
Vdd-a positive voltage; vss-a ground terminal;
b1-first body pole; b2 — second bulk pole; s1 — a first source; s2 — a second source; d1 — first drain; d2 — second drain; g1 — first gate; g2 — second gate;
STI1 — first shallow trench isolation structure; STI 2-second shallow trench isolation structure; STI 3-third shallow trench isolation structure;
WELL 1-P-WELL; WELL 2-N-WELL;
r-resistance; m1-capacitor; M2-NMOS tube; an A-inverter; and K-node.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 1a is a schematic cross-sectional view of a capacitor provided in this embodiment, and fig. 1b is an equivalent circuit diagram of the capacitor provided in this embodiment. Referring to fig. 1a and 1b, the capacitor includes two MOS capacitors formed on the same substrate 20, and the two MOS capacitors are connected in series.
With reference to fig. 1a and fig. 1b, one of the two MOS capacitors is an NMOS capacitor 10, and the other is a PMOS capacitor 11. Specifically, a P-WELL 1 and an N-WELL 2 are formed in the substrate 20 by ion implantation, the P-WELL 1 and the N-WELL 2 both extend from the surface of the substrate 20 into the substrate 20, wherein the depth of the P-WELL 1 is equal to the depth of the N-WELL 2. In the embodiment, the bottoms of the P-WELL 1 and the N-WELL 2 are lower than the bottom of the first shallow trench isolation STI1, so that the P-WELL WELL1 and the N-WELL WELL2 sink further to the first shallow trench isolation STI 1.
With continued reference to fig. 1a and 1B, the P-WELL 1 has a first body B1, a first source S1, a first drain D1, and a second shallow trench isolation STI2 formed therein, and the first body B1 and the first source S1 are isolated by the second shallow trench isolation STI 2. A first gate G1 is formed on the substrate 20 between the first source S1 and the first drain D1, in this embodiment, the first body B1 is a P + doped region, the first source S1 and the first drain D1 are N + doped regions, and the first body B1, the first source S1, the first drain D1 and the first gate G1 form the NMOS capacitor 10.
With continued reference to fig. 1a and 1B, a second body B2, a second source S2, a second drain D2 and a third shallow trench isolation structure STI3 are formed in the N-WELL 2, and the second body B2 and the second source S2 are isolated by the third shallow trench isolation structure STI 3. A second gate G2 is formed on the substrate 20 between the second source S2 and the second drain D2, in this embodiment, the second body B2 is an N + doped region, the second source S2 and the second drain D2 are P + doped regions, and the second body B2, the second source S2, the second drain D2 and the second gate G2 form the PMOS capacitor 11.
Further, with continued reference to fig. 1a and 1b, the first gate G1 and the second gate G2 are electrically connected through a metallization process, such that the NMOS capacitor 10 and the PMOS capacitor 11 are equivalently connected in series; the first body B1, the first source S1 and the first drain D1 of the NMOS capacitor 10 are electrically connected by a metallization process to serve as a first electrode of the capacitor; the second body B2, the second source S2 and the second drain D2 of the PMOS capacitor 11 are electrically connected by a metallization process to serve as a second electrode of the capacitor.
In this embodiment, the NMOS capacitor 10 and the PMOS capacitor 11 are fabricated simultaneously, for example, two ion implantations may be performed on the substrate 20 at the same time, so as to form the first body B1, the second source S2 and the second drain D2 simultaneously and to form the second body B2, the first source S1 and the first drain D1 simultaneously. Similarly, the gates of the NMOS capacitor 10 and the PMOS capacitor 11 may be formed simultaneously by patterning a conductive layer formed on the substrate 20, and specifically, after the first body B1, the second body B2, the first source S1, the first drain D1, the second source S2 and the second drain D2 are formed, a conductive layer such as polysilicon may be formed on the substrate 20, and then the conductive layer is etched to remove a portion of the conductive layer, leaving the conductive layer between the first source S1 and the first drain D1 and between the second source S2 and the second drain D2 to form the first gate G1 and the second gate G2. Similarly, after the first gate G1 and the second gate G2 are formed, the subsequent metallization processes may be simultaneously formed, and are not explained one by one here.
With reference to fig. 1a and 1b, the NMOS capacitor 10 has a first voltage range (0-V) when it is used as a single devicemax1) (ii) a The PMOS capacitor 11 is used as a device independently and has a second application voltage range (0-V)max2) (ii) a The capacitor formed by the NMOS capacitor 10 and the PMOS capacitor 11 connected in series has a third application voltage range (0-V)max3) (ii) a The first application voltage range and the second application voltage range of the capacitor are different, namely: vmax1≠Vmax2. Furthermore, since the NMOS capacitor 10 and the PMOS capacitor 11 are connected in series to form the capacitor, the capacitance of the capacitor is increased, and the application voltage range of a single MOS capacitor is widened, so that the maximum application voltage of the NMOS capacitor 10 is increasedThe maximum application voltage of the PMOS capacitor 11 and the maximum application voltage of the NMOS capacitor 10 are both smaller than the maximum application voltage of the PMOS capacitor 11, in this embodiment, that is: vmax1<Vmax2，Vmax1<Vmax2<Vmax3The capacitor can be applied to the application with higher voltage level (compared with the case that the NMOS capacitor 10 and the PMOS capacitor 11 are used as devices independently), and the NMOS capacitor 10 and the PMOS capacitor 11 are prepared synchronously, so that the manufacturing time and cost are lower.
With reference to fig. 1a and fig. 1b, a first gate oxide layer 101 is formed between the first gate G1 and the substrate 20, a second gate oxide layer 111 is formed between the second gate G2 and the substrate 20, and the first gate oxide layer 101 and the second gate oxide layer 111 are respectively used as dielectric layers of the NMOS capacitor 10 and the PMOS capacitor 11. In this embodiment, since the maximum application voltage of the NMOS capacitor 10 is smaller than the maximum application voltage of the PMOS capacitor 11, the second gate oxide layer 111 is thicker than the first gate oxide layer 101, thereby improving the safety performance of the PMOS capacitor 11.
It should be understood that, in order to avoid the breakdown of the capacitor, the breakdown voltage of the capacitor is usually larger than the maximum application voltage of the capacitor, and since the capacitor is composed of the NMOS capacitor 10 and the PMOS capacitor 11 connected in series, the breakdown voltage of the capacitor is theoretically equal to the sum of the breakdown voltages of the NMOS capacitor 10 and the PMOS capacitor 11. In order to avoid the breakdown of the NMOS capacitor 10 and the PMOS capacitor 11 by a larger applied voltage when the capacitor is used, in this embodiment, the sum of the breakdown voltages of the NMOS capacitor 10 and the PMOS capacitor 11 is larger than the maximum applied voltage of the capacitor.
For example, when the first application voltage range may be 0V to 2.5V, the second application voltage range may be 0V to 6V, and the third application voltage range may be 0V to 15V, at this time, the breakdown voltages of the NMOS capacitors 10 and the PMOS capacitors 11 are both 4V, the breakdown voltages of the PMOS capacitors 11 are both 13V, and the sum of the breakdown voltages of the NMOS capacitors 10 and the PMOS capacitors 11 is greater than the maximum value of the first voltage range (17V > 15V), even if the capacitor is applied in a 15V working environment, the NMOS capacitors 10 and the PMOS capacitors 11 are not broken down, which is feasible. Of course, this is merely an example, and the actual applied voltage range of the capacitor can be determined experimentally after the capacitor is manufactured.
Further, the unit capacitance of the capacitor can be increased by designing various parameters of the NMOS capacitor 10 and the PMOS capacitor 11, so that the unit capacitance of the capacitor is larger than that of each MOS capacitor of the capacitor, and thus, the size of the capacitor can be reduced under the condition that the applied voltage is the same in level. Specifically, the area of the overlapping region between the gate of the MOS capacitor and the substrate is the effective capacitance region, and the unit capacitance value of the capacitor can be maximized by adjusting the areas of the effective capacitance regions of the NMOS capacitor 10 and the PMOS capacitor 11, and after the areas of the effective capacitance regions of the NMOS capacitor 10 and the PMOS capacitor 11 are adjusted, the areas of the effective capacitance regions of the NMOS capacitor 10 and the PMOS capacitor 11 are different, that is: the overlapping area of the first gate G1 and the substrate 20 is different from the overlapping area of the second gate G2 and the substrate 20.
As an alternative embodiment, the areas of the capacitance effective areas of the NMOS capacitor 10 and the PMOS capacitor 11 may also be the same, that is: the overlapping area of the first gate G1 and the substrate 20 is the same as the overlapping area of the second gate G2 and the substrate 20, as long as the maximization of the unit capacitance value of the capacitor is achieved.
Further, when the capacitor is used, the first electrode can be connected with a ground terminal VssThe second electrode can be connected with a positive voltage VddAt this time, the PMOS capacitor 11 operates at a higher voltage, and the breakdown voltage of the N-WELL 2 needs to be greater than the maximum application voltage of the capacitor, so as to avoid the PMOS capacitor 11 from being broken down and damaged.
As an alternative embodiment, the capacitor is, in use, the firstThe electrode can be connected with a positive voltage VddThe second electrode can be connected with a ground terminal VssAt this time, the NMOS capacitor 10 operates at a higher voltage, and the breakdown voltage of the P-WELL 1 needs to be greater than the maximum application voltage of the capacitor, so as to avoid the NMOS capacitor 10 from being broken down and damaged.
Of course, when the NMOS capacitor 10 operates at a higher voltage, leakage is likely to occur, so in this embodiment, the NMOS capacitor 10 further includes an isolation ring (not shown) disposed in the P-WELL 1 and surrounding the first body B1, the first source S1 and the first drain D1, and the isolation ring is disposed around a circle of the first body B1, the first source S1 and the first drain D1, so that leakage of the NMOS capacitor 10 can be prevented. Specifically, the spacer ring may include: the deep WELL is located at the bottom of the P-WELL 1, and the edge WELL surrounds the side edge of the P-WELL 1 and is connected with the deep WELL, the deep WELL and the edge WELL can be both N-WELLs, and the doping of the edge WELL can be gradually changed along the depth direction. In one aspect, a voltage can be applied to the deep WELL through the side WELL such that the deep WELL is reverse isolated from between the P-WELL WELL1 and the substrate 20; on the other hand, the breakdown voltage of the NMOS capacitor 10 may be increased by increasing the area of the side well (the side well may extend laterally to be located outside the deep well) and decreasing the concentration of the impurity ions in the side well.
It should be understood that although the sum of the breakdown voltages of the NMOS capacitor 10 and the PMOS capacitor 11 is described as being greater than the maximum application voltage of the capacitor and the breakdown voltage of the N-WELL 2 (or P-WELL 1) needs to be greater than the maximum application voltage of the capacitor in the present embodiment, the actual application voltage of the capacitor may exceed the third voltage range due to voltage fluctuation and the like. In order to ensure the safety of the device, the sum of the breakdown voltages of the NMOS capacitor 10 and the PMOS capacitor 11 may be generally limited to be greater than 1.1 times the maximum application voltage of the capacitor, and the breakdown voltage of the N-WELL 2 (or the P-WELL 1) may be limited to be greater than 1.1 times the maximum application voltage of the capacitor.
It should be understood that, although the two MOS capacitors in the capacitor are respectively an NMOS capacitor and a PMOS capacitor in the present embodiment, in practice, the two MOS capacitors in the capacitor may be both NMOS capacitors or both PMOS capacitors, which is not illustrated herein.
Fig. 2 is a circuit diagram of the capacitor provided in this embodiment applied to a power clamp ESD protection circuit. As shown in fig. 2, the power clamp ESD protection circuit may be located between an input interface and an output interface of an integrated circuit to protect the integrated circuit from electrostatic damage.
The power clamp ESD protection circuit includes a capacitor-resistor (C-R) circuit, a trigger circuit, and a clamp circuit. The capacitance-resistance (C-R) circuit comprises a resistor R and a capacitor M1 provided by the implementation, the trigger circuit comprises an inverter A, and the clamping circuit comprises a large-sized NMOS transistor M2. The resistor R is connected at a positive voltage VddAnd a node K, and two electrodes of the capacitor M1 are connected between the node K and a ground terminal VssIn the meantime. The input end and the input end of the phase inverter A are respectively connected with the node K and the grid electrode of the NMOS tube M2, and the source electrode and the drain electrode of the NMOS tube M2 are connected with the ground end VssConnection, body pole to positive voltage Vdd. The capacitor M1 is used for sensing the ESD voltage and driving the trigger circuit; the inverter A is used for driving an NMOS transistor M2, and the NMOS transistor M2 is used for providing a positive voltage V when an ESD pulse is sensedddTo ground end VssThe current bleeding channel.
The capacitor M1 in this embodiment is formed by two MOS capacitors connected in series, and compared with a MOS capacitor having the same application voltage range as that of a single MOS capacitor in the capacitor M1, the capacitor M1 has a higher application voltage level, and can be applied to a power clamp ESD protection circuit having a higher ESD voltage, and the size of the capacitor is smaller.
Fig. 3 is a method for manufacturing the capacitor provided in this embodiment. As shown in fig. 3, the method for manufacturing the capacitor includes:
step S100: providing a substrate;
step S200: forming two MOS capacitors on the substrate, wherein the maximum application voltages of the two MOS capacitors are different and are both smaller than the maximum application voltage of the capacitor; and the number of the first and second groups,
step S300: and connecting two MOS capacitors in series.
Next, in this embodiment, a method for manufacturing the capacitor will be described in detail by taking two MOS capacitors as an NMOS capacitor and a PMOS capacitor, respectively.
Specifically, referring to fig. 1a, step S100 is first executed to provide the substrate 20, where the substrate 20 is, for example, a silicon substrate (silicon substrate), a silicon containing substrate (silicon containing substrate), an epitaxial silicon substrate (epitaxial silicon substrate), a silicon-on-insulator substrate (silicon-on-insulator substrate), or the like. The substrate 20 is formed with a P-WELL WELL1 and an N-WELL WELL2, the P-WELL WELL1 and the N-WELL WELL2 both extend from the surface of the substrate 20 into the substrate 20, and the depth of the P-WELL WELL1 is equal to the depth of the N-WELL WELL 2.
The substrate 20 also has a first trench isolation structure STI1 formed therein, the first trench isolation structure STI1 is located between the P-WELL 1 and the N-WELL 2 to define an active region, and bottoms of the P-WELL 1 and the N-WELL 2 are lower than a bottom of the first trench isolation structure STI 1.
Further, step S200 is performed to form a first body B1, a first source S1 and a first drain D1 in the P-WELL 1 through an ion implantation process; and forming a second body B2, a second source S2 and a second drain D2 in the N-WELL 2, wherein the first body B1, the first source S1 and the first drain D1 are sequentially arranged, and the second source S2, the second drain D2 and the second body B2 are sequentially arranged.
It should be understood that the first body B1, the first source S1, the first drain D1, the second body B2, the second source S2 and the second drain D2 are considered to be formed at the same time, but since the first body B1, the second source S2 and the second drain D2 are P + doped regions and the first source S1, the first drain D1 and the second body B2 are N + doped regions, the first body B1, the second source S2 and the second drain D2 and the first source S1, the first drain D1 and the second body B2 are actually formed in two steps.
Next, a second shallow trench isolation STI2 is formed between the first body B1 and the first source S1, a third shallow trench isolation STI3 is formed between the second body B2 and the second drain D2, the first body B1 and the first source S1 are isolated by the second shallow trench isolation STI2, and the second body B2 and the second drain D2 are isolated by the third shallow trench isolation STI 3.
Further, a first gate G1 and a second gate G2 are formed on the substrate 20, the first gate G1 is located on the P-well and between the first source S1 and the first drain D1, the second gate G2 is located on the N-well and between the second source S2 and the second drain D2, the first body B1, the first source S1, the first drain D1 and the first gate G1 form an NMOS capacitor, and the second body B2, the second source S2, the second drain D2 and the second gate G2 form a PMOS capacitor.
The method of forming the first and second gates G1 and G2 may be: a conductive layer is formed on the substrate 20, and then a portion of the conductive layer is removed by an etching process, and a portion of the conductive layer between the first source S1 and the first drain D1 is reserved as the first gate G1, and a portion of the conductive layer between the second source S2 and the second drain D2 is reserved as the second gate G2.
Next, step S300 is performed, and a metallization process is performed to connect the NMOS capacitor and the PMOS capacitor in series. Specifically, the first gate G1 and the second gate G2 are connected by an electrical connector and/or a metal wiring layer, and similarly, the first body B1, the first source S1 and the first drain D1 are connected by an electrical connector and/or a metal wiring layer to serve as a first electrode of the capacitor, and the second body B2, the second source S2 and the second drain D2 are connected to serve as a second electrode of the capacitor. In this embodiment, the electrical connector may be a contact hole electrical connector.
In summary, the capacitor provided in the embodiments of the present invention includes two MOS capacitors formed on the same substrate, and the maximum application voltages of the two MOS capacitors are different and both smaller than the maximum application voltage of the capacitor. The invention enlarges the capacitance value by connecting the two MOS capacitors formed on the same substrate in series, further improves the grade of the application voltage of the capacitor, has lower manufacturing cost, and can improve the unit capacitance value of the capacitor by designing various parameters of the two MOS capacitors, thereby reducing the size of the capacitor and improving the performance of the capacitor. Based on the capacitor, the embodiment of the invention also provides a preparation method of the capacitor.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (8)

1. A capacitor is characterized by comprising two MOS capacitors formed on the same substrate, wherein the two MOS capacitors are connected in series, the maximum application voltages of the two MOS capacitors are different and are both smaller than the maximum application voltage of the capacitor, and the sum of the breakdown voltages of the two MOS capacitors is larger than the maximum application voltage of the capacitor;
each MOS capacitor comprises a source electrode, a drain electrode, a body electrode and a grid electrode, wherein the source electrode, the drain electrode and the body electrode are all positioned in the substrate, and the grid electrode is positioned on the substrate and positioned between the corresponding source electrode and the corresponding drain electrode;
one of the two MOS capacitors is an NMOS capacitor, the other one is a PMOS capacitor, the NMOS capacitor is connected with a grid electrode of the PMOS capacitor, a source electrode, a drain electrode and a body electrode of the NMOS capacitor are connected and then serve as a first electrode of the capacitor, and a source electrode, a drain electrode and a body electrode of the PMOS capacitor are connected and then serve as a second electrode of the capacitor.
2. The capacitor of claim 1, wherein a unit capacitance value of the capacitor is greater than a unit capacitance value of each MOS capacitor.
3. The capacitor of claim 1, wherein two of said MOS capacitors are fabricated simultaneously.
4. The capacitor of claim 1, wherein the areas of the overlapping regions of the gates of the two MOS capacitors and the substrate are not equal.
5. The capacitor of claim 1, wherein a gate oxide layer is formed between the gate of each of said MOS capacitors and said substrate, and the gate oxide layer of the MOS capacitor having the higher maximum application voltage is thicker in both of said MOS capacitors.
6. The capacitor of claim 1 wherein the substrate has a P-well and an N-well formed therein, the source, drain and bulk of the NMOS capacitor are all located in the P-well, and the source, drain and bulk of the PMOS capacitor are all located in the N-well.
7. The capacitor of claim 6, wherein the first electrode is for ground, the second electrode is for connection to a positive voltage, and the breakdown voltage of the N-well is greater than a maximum applied voltage of the capacitor.
8. A method of making a capacitor, comprising:
providing a substrate;
forming two MOS capacitors on the substrate, wherein the maximum application voltages of the two MOS capacitors are different and are both smaller than the maximum application voltage of the capacitor; and the number of the first and second groups,
connecting two MOS capacitors in series;
the method comprises the following steps of forming a P well and an N well in a substrate, and forming two MOS capacitors on the substrate, wherein the step of forming the P well and the N well in the substrate comprises the following steps:
forming a source electrode, a drain electrode and a body electrode in the P well and the N well respectively; and the number of the first and second groups,
forming two gates on the P well and the N well respectively, wherein each gate is positioned between the corresponding source and drain, the source, the drain and the body in the P well and the gate on the P well form an NMOS capacitor, and the source, the drain and the body in the N well and the gate on the N well form a PMOS capacitor;
the step of connecting two MOS capacitors in series comprises the following steps:
connecting the NMOS capacitor with the grid of the PMOS capacitor; and the number of the first and second groups,
and connecting the source electrode, the drain electrode and the body electrode of the NMOS capacitor to serve as a first electrode of the capacitor, and connecting the source electrode, the drain electrode and the body electrode of the PMOS capacitor to serve as a second electrode of the capacitor.
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1941203A (en) * 2005-09-29 2007-04-04 松下电器产业株式会社 Nonvolatile semiconductor memory device
CN101833186A (en) * 2009-03-10 2010-09-15 立景光电股份有限公司 Pixel circuit of display device
CN102903715A (en) * 2011-07-25 2013-01-30 瑞萨电子株式会社 Semiconductor integrated circuit
CN203325415U (en) * 2013-06-21 2013-12-04 南开大学 Pixel unit circuit composed of MOS transistor and MOS capacitor of same type
CN203397671U (en) * 2013-06-21 2014-01-15 南开大学 Pixel unit circuit composed of complementary transmission gate and MOS capacitor
CN106057240A (en) * 2015-04-06 2016-10-26 爱思开海力士有限公司 Non-volatile memory device and method of fabricating the non-volatile memory device and non-volatile memory cell array
CN108736697A (en) * 2017-04-24 2018-11-02 台湾积体电路制造股份有限公司 Capacitor cell

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1941203A (en) * 2005-09-29 2007-04-04 松下电器产业株式会社 Nonvolatile semiconductor memory device
CN101833186A (en) * 2009-03-10 2010-09-15 立景光电股份有限公司 Pixel circuit of display device
CN102903715A (en) * 2011-07-25 2013-01-30 瑞萨电子株式会社 Semiconductor integrated circuit
CN203325415U (en) * 2013-06-21 2013-12-04 南开大学 Pixel unit circuit composed of MOS transistor and MOS capacitor of same type
CN203397671U (en) * 2013-06-21 2014-01-15 南开大学 Pixel unit circuit composed of complementary transmission gate and MOS capacitor
CN106057240A (en) * 2015-04-06 2016-10-26 爱思开海力士有限公司 Non-volatile memory device and method of fabricating the non-volatile memory device and non-volatile memory cell array
CN108736697A (en) * 2017-04-24 2018-11-02 台湾积体电路制造股份有限公司 Capacitor cell

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