TW202336978A - Semiconductor structure - Google Patents

Abstract

A semiconductor structure is provided. At least one first well region is disposed in a semiconductor substrate and has a first conductivity type. At least one gate of a transistor is disposed over the first well region and extends along a first direction. At least one second well region and at least one third well region are disposed on opposite sides of the first well region and extend along the first direction. The second well region and the third well region have a second conductivity type, and the second conductivity type is complementary to the first conductivity type. A first shielding structure is disposed on at least one end of the gate and partially overlaps the first well region in a vertical projection direction. The first shielding structure is separated from the end of the gate. A bulk ring is disposed in the semiconductor substrate and surrounds the gate, the second well region, the third well region and the first shielding structure.

Description

semiconductor structure

The present invention relates to a semiconductor structure, and in particular to a semiconductor structure with a shielding structure.

The electronics industry has experienced increased demand for smaller and faster electronic devices that simultaneously support a larger number of increasingly complex and high-tech functions. Therefore, the ongoing trend in the semiconductor industry is to produce low-cost, high-performance, and low-power integrated circuits (ICs).

Today, integrated circuits include millions or billions of semiconductor components formed on a semiconductor substrate, such as silicon. Integrated circuits may use many different types of semiconductor structural devices depending on the IC's application. In recent years, the growing market for cellular devices and radio frequency (RF) components has resulted in a significant increase in the use of high-voltage semiconductor structural components. For example, high-voltage semiconductor structural components are commonly used in power amplifiers in RF transmitter/receivers due to their ability to handle high breakdown voltages and high frequencies. In addition, high-voltage semiconductor structural components can also be used in electrostatic discharge (ESD) protection circuits.

The present invention provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate, at least a first well region, at least one gate of a transistor, at least a second well region and at least a third well region, a first shielding structure and a body ring. The at least one first well region is disposed in the semiconductor substrate and has a first conductivity type. The at least one gate of the transistor is disposed above the at least one first well region and extends along a first direction. The at least one second well zone and the at least one third well zone are disposed on opposite sides of the at least one first well zone and extend along the first direction. The at least one second well region and the at least one third well region have a second conductivity type, and the second conductivity type is complementary to the first conductivity type. The first shielding structure is disposed on at least one end of the at least one gate and partially overlaps the at least one first well region in a vertical projection direction. The first shielding structure is separated from the at least one end of the at least one gate. The bulk ring is disposed in the semiconductor substrate and surrounds the at least one gate, the at least one second well region, the at least one third well region and the first shielding structure.

In order to make this and other objects, features, and advantages of the present invention more clearly understood, preferred embodiments are listed below and described in detail with reference to the accompanying drawings:

The following disclosure provides numerous embodiments, or examples, for implementing different elements of the provided subject matter. Specific examples of each component and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that the first element is formed on the second element, it may include an embodiment in which the first element and the second element are in direct contact, or it may also include an embodiment in which additional elements are formed on the first element and the second element. between them so that they are not in direct contact. In addition, embodiments of the present invention may repeat reference numbers and/or letters in various examples. Such repetition is for the sake of simplicity and clarity and is not intended to represent the relationship between the various embodiments and/or configurations discussed.

Furthermore, words relative to space may be used, such as "under", "below", "lower", "above", "higher" and other similar words, for the convenience of description. The relationship between one component(s) or feature(s) and another(s) component(s) or feature(s) in the diagram. Spatially relative terms are used to encompass different orientations of equipment in use or operation and the orientation depicted in the drawings. When the device is turned to a different orientation (rotated 90 degrees or at other orientations), the spatially relative adjectives used therein will also be interpreted in accordance with the rotated orientation.

Figure 1 is a top view of a semiconductor structure 100 according to some embodiments of the invention. In some embodiments, semiconductor structure 100 is an N-type symmetric semiconductor structure. In some embodiments, semiconductor structure 100 is a high voltage semiconductor structure. In this embodiment, the semiconductor structure 100 includes a transistor, and the bulk region of the transistor forms a ring, hereinafter referred to as the bulk ring 122 . The block ring 122 is electrically coupled to the upper interconnect structure (not shown) via the contacts 205 and the metal lines 210a. In some embodiments, the gate G of the transistor in the semiconductor structure 100 includes a metal gate structure. In addition, the gate G is electrically coupled to the upper interconnect structure (not shown) via the contact 205 and the metal lines 210d and 210e. The source region S of the transistor in the semiconductor structure 100 is formed in the second well region 110a and is electrically coupled to the upper interconnect structure (not shown) via the contact 205 and the metal line 210b. Furthermore, the drain region D of the transistor in the semiconductor structure 100 is formed in the second well region 110b and is electrically coupled to the upper interconnect structure (not shown) via the contact 205 and the metal line 210c. In this embodiment, metal wire 210a partially overlaps block ring 122 . In addition, the metal lines 210b, 210c, 210d, and 210e extend along the Y direction, and the metal lines 210d and 210 span a portion of the block ring 122 (ie, the portion not covered by the metal line 210a).

In FIG. 1 , the semiconductor structure 100 further includes shielding structures 10A and 10B. In this embodiment, the block ring 122 is a square ring. Shielding structures 10A and 10B are formed between gate G and bulk ring 122 . For example, in terms of layout, the shielding structure 10A is formed between the gate G and the first side (or first side) of the block ring 122 , while the shielding structure 10B is formed between the gate G and the first side of the block ring 122 . Between two sides (or second sides). For the block ring 122, the first side is relative to the second side. Similarly, the shielding structure 10A is disposed close to one end (eg, the upper end) of the gate G, and the shielding structure 10B is disposed close to the other end (eg, the lower end) of the gate G. For the gate G, the shielding structures 10A and 10B are disposed at opposite ends of the gate G. In this embodiment, the shielding structure 10A is further disposed between the metal lines 210d and 210e. The shielding structure 10A includes an electrode (or metal plate) 215a and a contact 205, while the shielding structure 10B includes an electrode (or a metal plate) 215b and a contact 205. In the top view of the semiconductor structure in Figure 1, the gate G extends along the Y direction. In some embodiments, gate G is formed of polysilicon. In some embodiments, gate G is formed of metal. The drain region D and the source region S are arranged on the left and right sides of the gate G, and the shielding structures 10A and 10B are formed on the upper and lower sides of the gate G. In other words, the gate G and the shielding structures 10A and 10B are disposed on the same straight line along the Y direction.

In the semiconductor structure 100, the metal lines 210a-210e and the metal plates 215a and 215b are formed of the same conductive material. In addition, the metal lines 210a-210e and the metal plates 215a and 215b are disposed on the same metal layer (eg, the lowest metal layer). Furthermore, the metal plate 215b is connected to the metal wire 210a on the second side of the block ring 122.

Figure 2 is a top view of the semiconductor structure 100 of Figure 1 with metal lines 210a-210e and metal plates 215a and 215b removed according to some embodiments of the present invention. Referring to FIGS. 1 and 2 simultaneously, the first doped region 132a is formed in the second well region 110a, and the metal line 210b is electrically coupled to the transistor via the contact 205 and the first doped region 132a. Source region S. In addition, the N-type doped region 132b is formed in the second well region 110b, and the metal line 210c is electrically coupled to the drain region D of the transistor via the contact 205 and the first doped region 132b. The first doped regions 132a and 132b extend along the Y direction. In some embodiments, the first doped regions 132a and 132b are N-type doped regions.

In one embodiment, the shielding structure 10A is made of polysilicon, and the shielding structure 10A is electrically coupled to the metal plate 215a through the contact 205. The shielding structure 10A is separated from the gate G and the bulk ring 122, and partially overlaps the second well regions 110a and 110b. In addition, the shielding structure 10A is electrically connected to the block ring 122 via the metal plate 215a and the contact point 205. Similarly, the shielding structure 10B is made of polysilicon in one embodiment, and the shielding structure 10B is electrically coupled to the metal plate 215b via the contact 205 . The shielding structure 10B is separated from the gate G and the bulk ring 122, and partially overlaps the second well regions 110a and 110b. In addition, the shielding structure 10B is electrically connected to the block ring 122 via the metal plate 215b and the contact point 205.

In some embodiments, the gate G and the shielding structures 10A and 10B are disposed on the same layer and formed of the same polycrystalline silicon material, but the invention is not limited thereto. In some embodiments, the gate G and the shielding structures 10A and 10B may be formed of different materials respectively. The gate G includes polycrystalline silicon, metal or other suitable materials. Shielding structures 10A and 10B include polysilicon, metal, or are formed of other suitable materials. In the X direction, the width of the shielding structures 10A and 10B is smaller than the width (or size) of the gate G. In the Y direction, the lengths of the shielding structures 10A and 10B are also smaller than the length (or size) of the gate G. Specifically, the area of the shielding structure 10A or 10B is smaller than the area of the gate G, so as to achieve better area utilization and facilitate the reduction of semiconductor components.

FIG. 3 is a cross-sectional view along line A-AA of the semiconductor structure 100 in FIGS. 1-2 according to some embodiments of the present invention. Second well regions 110a and 110b are formed in the semiconductor substrate 15. In some embodiments, the semiconductor substrate 15 may be a bulk silicon substrate, a silicon-on-insulator substrate, a binary compound semiconductor substrate, a ternary compound semiconductor substrate, or a higher-order compound semiconductor substrate, or the like. The second well regions 110a and 110b are formed by implanting one or more dopants or an ion implantation process.

The source region S in the semiconductor structure 100 is formed by the second well region 110a, and the second well region 110a is electrically coupled to the metal line 210b through the first doping region 132a and the contact 205 in sequence. In addition, the drain region D in the semiconductor structure 100 is formed by the second well region 110b, and the second well region 110b is electrically coupled to the metal line 210c through the first doping region 132b and the contact 205 in sequence.

Bulk ring 122 and first well regions 105a and 105b are formed in semiconductor substrate 15. The first well region 105a is formed between the second well regions 110a and 110b, and the first well region 105b is formed between the second well regions 110a and 110b and the block ring 122. In some embodiments, the first well areas 105a and 105b are P-type well areas and the second well areas 110a and 110b are N-type well areas. In some embodiments, first well regions 105a and 105b may be semiconductor substrate 15. In some embodiments, first well regions 105a and 105b and block ring 122 are formed from the same material. also. The channel of the transistor in the semiconductor structure 100 is formed in the first well region 105a. Block ring 122 is formed by P-shaped well regions. The second doped region 134 is formed in the bulk ring 122 , and the metal line 210 a is electrically coupled to the bulk ring 122 via the contact 205 and the second doped region 134 . In some embodiments, the second doped region 134 is a P-type heavily doped region.

The second well areas 110a and 110b and the block ring 122 are separated by the first well area 105a. Furthermore, the first doped region 132a and the second doped region 134 are separated by the field oxide 130, and the first doped region 132b and the second doped region 134 are separated by the field oxide 130. Gate G is formed above the first well region 105a. To simplify the description, other features of the gate G in the semiconductor structure 100 (such as the gate dielectric layer, etc.) will be omitted. In addition, the gate G is electrically coupled to the metal lines 210d and 210e via the contact point 205. In addition, the gate G and the first doped regions 132a and 132b are separated by the field oxide 130.

FIG. 4 is a cross-sectional view along line B-BB of the semiconductor structure 100 in FIGS. 1-2 according to some embodiments of the present invention. Second well regions 110a and 110b, bulk ring 122, and first well regions 105a and 105b are formed in the semiconductor substrate 15. The shielding structure 10B is formed on the first well region 105a and is separated from the first well region 105a and the second well regions 110a and 110b via the field oxide 130. As can be seen from Figures 2 and 4, the shielding structures 10A and 10B partially overlap the first well area 105a and the second well area 110a and 110b in the vertical projection direction. As described previously, the shielding structure 10B is electrically coupled to the bulk ring 122 via the contact 205, the metal plate 215b, the metal line 210a, the contact 205 and the second doped region 134 in sequence. Therefore, when the bulk ring 122 is grounded via the interconnect structure in the semiconductor structure, the shield structure 10B is grounded. Therefore, when there are metal lines formed (windings) formed by a higher metal layer above the first well region 105a and the second well regions 110a and 110b, the shielding structure 10B can avoid the voltage of the higher metal layer (for example, if The drain voltage supplied to the semiconductor structure 100 is coupled to the first well region 105a. Therefore, the parasitic NPN bipolar transistor (NPN BJT) 113 formed by the second well region 110a, the first well region 105a and the second well region 110b will not be turned on, so no leakage current will occur. In addition, the leakage current generated by the gate bias of the semiconductor structure 100 under high temperature can also be suppressed, thereby increasing the breakdown voltage.

Figure 5 shows a top view of a semiconductor structure 300 according to some embodiments of the invention. In some embodiments, semiconductor structure 300 is an N-type symmetric semiconductor structure. In some embodiments, semiconductor structure 300 is a high voltage semiconductor structure. In this embodiment, the semiconductor structure 300 includes a transistor, and the bulk region of the transistor forms a ring, hereinafter referred to as the bulk ring 122 . The gate G of the transistor in the semiconductor structure 300 is formed by a plurality of sub-gates 150a-150d. In some embodiments, the sub-gates 150a-150d are electrically coupled to the same finger electrode (not shown) on the upper layer via the contact 205. The source region S of the transistor in the semiconductor structure 300 is formed in the second well regions 110a, 110c, and 110e, and is electrically coupled to the upper layer interconnection through the first doped regions 132a, 132c, and 132e and the contact 205. structure (not shown). The drain region D of the transistor in the semiconductor structure 300 is formed in the second well regions 110b and 110d, and is electrically coupled to the upper interconnect structure (not shown) through the first doping regions 132b and 132d and the contact 205 ). In this embodiment, to simplify the description, the electrodes and metal lines in the lowest metal layer that electrically couple features of the semiconductor structure 300 are omitted. In addition, the second well regions 110a, 110c and 110e and the second well regions 110b and 110d are alternately arranged along the X direction, that is, the drain regions D and the source regions S are alternately arranged along the X direction.

In this embodiment, the sub-gate 150a is disposed between the first doping regions 132a and 132b and above the first well region 125a. The sub-gate 150b is disposed between the first doping regions 132b and 132c and above the first well region 125b. The sub-gate 150c is disposed between the first doping regions 132c and 132d and above the first well region 125c. The sub-gate 150d is disposed between the first doping regions 132d and 132e and above the first well region 125d. The first well zones 125a-125d may be P-type well zones. In addition, the second well areas 110a-110e are respectively surrounded by annular well areas 120a-120e. For example, the second well area 110a is completely surrounded by the annular well area 120a, and the second well area 110b is completely surrounded by the annular well area 120b. In some embodiments, the annular well regions 120a-120e may be formed by P-shaped well regions. In some embodiments, the annular well regions 120a-120e may be formed on a P-type substrate.

In FIG. 5, the semiconductor structure 300 includes shielding structures 10A_1-10A_4 and 10B_1-10B_4. In this embodiment, the block ring 122 is a square ring. The shielding structures 10A_1 - 10A_4 are formed near the first side of the block ring 122 , and the shielding structures 10B_1 - 10B_4 are formed near the second side of the block ring 122 . As previously described, the shielding structures 10A_1-10A_4 and the shielding structures 10B_1-10B_4 are formed of polycrystalline silicon. The shielding structures 10A_1 - 10A_4 and the shielding structures 10B_1 - 10B_4 can be electrically coupled to the block ring 122 through the contacts 205 and the upper metal plate (eg, the electrodes 215a and 215b in FIG. 1 ).

In addition, the sub-gate 150a and the shielding structures 10A_1 and 10B_1 are disposed on the same straight line along the Y direction. The sub-gate 150b and the shielding structures 10A_2 and 10B_2 are disposed on the same straight line along the Y direction. The sub-gate 150c and the shielding structures 10A_3 and 10B_3 are disposed on the same straight line along the Y direction. The sub-gate 150d and the shielding structures 10A_4 and 10B_4 are disposed on the same straight line along the Y direction.

FIG. 6 is a cross-sectional view along line C-CC of the semiconductor structure 300 of FIG. 5 according to some embodiments of the present invention. Second well regions 110a and 110b are formed in the semiconductor substrate 15. The second well region 110a forms the source region S of the semiconductor structure 300, and the second well region 110a is electrically coupled to the upper metal line via the first doped region 132a and the contact 205. In addition, the second well region 110b forms the drain region D of the semiconductor structure 300, and the second well region 110b is electrically coupled to the upper metal line through the first doping region 132b and the contact 205.

As previously described, the second well area 110a is surrounded by the annular well area 120a, and the second well area 110b is surrounded by the annular well area 120b. The first well region 125a is formed in the semiconductor substrate 15 between the annular well regions 120a and 120b. The sub-gate 150a is formed above the second well area 110a, the annular well area 120a, the first well area 125a, the annular well area 120b and the second well area 110b. In addition, the sub-gate 150a is electrically coupled to an upper metal line (such as a finger electrode) through the contact point 205. It is worth noting that the sub-gate 150a completely overlaps the first well region 125a.

FIG. 7 is a cross-sectional view along line D-DD of the semiconductor structure 300 of FIG. 5 according to some embodiments of the present invention. Second well regions 110 a and 110 b and bulk ring 122 are formed in semiconductor substrate 15 . The shielding structure 10B_1 is formed on the first well region 125a and is separated from the first well region 125a and the annular well regions 120a and 120b via the field oxide 130. The shielding structure 10B_2 is formed on the first well region 125b and is separated from the first well region 125b and the annular well regions 120b and 120c via the field oxide 130. As previously described, the shielding structures 10B_1 and 10B_2 are electrically coupled to the bulk ring 122 via the contact 205 , the upper metal plate and metal lines, the contact 205 and the second doped region 134 . Therefore, when the bulk ring 122 is grounded via the interconnect structure in the semiconductor structure, the shielding structures 10A_1 - 10A_4 and the shielding structures 10B_1 - 10B_4 are grounded. Therefore, when there are metal lines formed by higher metal layers arranged (windings) above the first well regions 125a and 125b, the shielding structures 10B_1 and 10B_2 can prevent the voltage on the metal lines (eg, to be supplied to the semiconductor structure 300 drain voltage) is coupled to first well regions 125a and 125b. Therefore, the parasitic NPN bipolar transistor (such as the bipolar transistor 113 in FIG. 4) formed by the second well region 110a, the first well region 125a and the second well region 110b will not be turned on, so it will not Leakage current occurs.

Figure 8 shows a top view of a semiconductor structure 400 according to some embodiments of the invention. In some embodiments, semiconductor structure 400 is an N-type symmetric semiconductor structure. In some embodiments, semiconductor structure 400 is a high voltage semiconductor structure. The structure of the semiconductor structure 400 is similar to the structure of the semiconductor structure 300 in FIG. 5 . The difference from the semiconductor structure 300 in FIG. 5 is that the semiconductor structure 400 in FIG. 8 includes shielding structures 30A and 30B. The shielding structure 30A is formed proximate the first side of the block ring 122 and the shielding structure 30B is formed proximate the second side of the block ring 122 . The shielding structures 30A and 30B may be electrically coupled to the bulk ring 122 via the contact 205 and the upper metal plate (eg, the electrodes 215a and 215b in FIG. 1 ). In some embodiments, the contacts 205 above the shielding structures 30A and 30B are disposed close to the source region S, the drain region D, and the gate G. In this embodiment, the shielding structures 30A and 30B extend along the X direction, and the sub-gates 150a-150d extend along the Y direction.

The sub-gates 150a-150d and the shielding structures 30A and 30B are disposed on the same layer and formed of the same polycrystalline silicon material. In some embodiments, sub-gates 150a-150d and shielding structures 30A and 30B may be formed of the same conductive material. In the X direction, the width (or size) of the sub-gates 150a-150d is smaller than the width of the shielding structures 30A and 30B. In the Y direction, the length (or size) of the sub-gates 150a-150d is also greater than the length of the shielding structures 30A and 30B. In FIG. 8, the shielding structures 30A and 30B extend from the first doping region 132a to the first doping region 132e in the X direction.

FIG. 9 is a cross-sectional view along line E-EE of the semiconductor structure 400 of FIG. 8 according to some embodiments of the present invention. Second well regions 110 a and 110 b and bulk ring 122 are formed in semiconductor substrate 15 . Shield structure 30B is formed over field oxide 130 . As previously described, the shielding structure 30B is electrically coupled to the bulk ring 122 via the contact 205 , the upper metal plate and metal lines, the contact 205 and the second doped region 134 . Therefore, when bulk ring 122 is grounded via interconnect structures in the semiconductor structure, shield structures 30A and 30B are grounded. Therefore, when there are metal lines formed by higher metal layers arranged (windings) above the first well regions 125a and 125b, the shielding structure 30B can avoid the voltage on the metal lines (such as the drain to be supplied to the semiconductor structure 400). polar voltage) coupled to first well regions 125a and 125b. Therefore, the parasitic NPN bipolar transistor is not turned on, thereby preventing leakage current from occurring.

Figure 10 shows a top view of a semiconductor structure 500 according to some embodiments of the invention. In some embodiments, semiconductor structure 500 is an N-type semiconductor structure that serves as electrostatic discharge (ESD) protection. The structure of the semiconductor structure 500 is similar to the structure of the semiconductor structure 400 of FIG. 8 . The difference from the semiconductor structure 500 in Figure 8 is that the configuration of the contacts 205 of the sub-gates 150a-150d of the semiconductor structure 500 in Figure 10 is different from the contacts of the sub-gates 150a-150d of the semiconductor structure 400 in Figure 8 205 configuration. In FIG. 8, each sub-gate 150a-150d is electrically coupled to the upper electrode (or metal line) through the contacts 205 arranged in a row along the Y direction, so as to receive the voltage applied to the semiconductor structure 400. Gate voltage of gate G. In Figure 10, each sub-gate 150a-150d is electrically coupled to the upper electrode (or metal line) through contacts 205 arranged in a row along the X direction.

FIG. 11 is a top view of the semiconductor structure 500 and electrode 510 of FIG. 10 according to some embodiments of the invention. The electrode 510 is a metal ring formed by metal lines formed on the lowest metal layer. The electrode 510 overlaps the bulk ring 122 and the first doped regions 132a, 132c, and 132e, and is electrically coupled to the bulk ring 122 and the first doped regions 132a, 132c, and 132e via the contacts 205. Therefore, the bulk B and the source region S of the semiconductor structure 500 are electrically coupled together through the electrode 510 . In addition, the electrode 510 further includes sub-electrodes 512, 514 and 516 for electrically coupling to the sub-gates 150a-150d via the contacts 205. Therefore, the bulk B, the source region S and the gate G of the semiconductor structure 500 are electrically coupled together via the electrode 510 .

Figure 12 shows an electrostatic discharge protection circuit 50 implemented by a semiconductor structure 500 according to some embodiments of the present invention. Electrostatic discharge protection circuit 50 includes semiconductor structure 500 . Referring also to FIGS. 10-12 , the drain region D of the semiconductor structure 500 is electrically coupled to the bonding pad 52 via metal lines 520 and 522 and other interconnect structures. The gate G and source region S of the transistor in the semiconductor structure 500 are electrically coupled to the ground terminal VSS through the electrode 510 and other interconnection structures. As previously described, by using the shield structures 30A and 30B, electrostatic discharge energy or higher voltage signals from the bonding pad 52 are not coupled to the gate G of the semiconductor structure 500 to avoid turning on the parasitic NPN double Polar transistor, thus preventing leakage current.

Figure 13 shows a top view of a semiconductor structure 600 according to some embodiments of the invention. In some embodiments, semiconductor structure 600 is an N-type symmetric semiconductor structure. In some embodiments, semiconductor structure 600 is a high voltage semiconductor structure. The configuration of the semiconductor structure 600 is similar to the configuration of the semiconductor structure 300 of FIG. 5 . The difference from the semiconductor structure 300 in Figure 5 is that the semiconductor structure 600 in Figure 13 further includes shielding structures 10C_1-10C_3, shielding structures 10D_1 and 10D_2, shielding structures 10E_1-10E_3, and shielding structures 10F_1 and 10F_2. Shielding structures 10C_1 - 10C_3 and shielding structures 10D_1 and 10D_2 are formed proximate a first side of the block ring 122 , while shielding structures 10E_1 - 10E_3 and shielding structures 10F_1 and 10F_2 are formed proximate a second side of the block ring 122 .

The shielding structures 10C_1 - 10C_3 and the shielding structures 10D_1 - 10D_2 may be electrically coupled to the first side of the block ring 122 via the contacts 205 and the upper metal plate (not shown). The shielding structures 10E_1-10E_3 and the shielding structures 10F_1-10F_2 may be electrically coupled to the second side of the block ring 122 via the contacts 205 and upper electrodes (not shown).

In FIG. 13, the first doped region 132a and the shielding structures 10C_1 and 10E_1 are disposed on the same straight line along the Y direction. The first doped region 132b and the shielding structures 10D_1 and 10F_1 are disposed on the same straight line along the Y direction. The first doped region 132c and the shielding structures 10C_2 and 10E_2 are disposed on the same straight line along the Y direction. The first doping region 132d and the shielding structures 10D_2 and 10F_2 are disposed on the same straight line along the Y direction. The first doped region 132e and the shielding structures 10C_3 and 10E_3 are disposed on the same straight line along the Y direction.

In the X direction, the widths (or sizes) of the first doped regions 132a, 132c and 132e are smaller than the widths of the shielding structures 10C_1-10C_3 and the shielding structures 10E_1-10E_3. Furthermore, in the X direction, the widths (or sizes) of the first doped regions 132b and 132d are smaller than the widths of the shielding structures 10D_1 and 10D_2 and the shielding structures 10F_1 and F_2.

The shielding structures 10C_1-10C_3, 10D_1-10D_2, 10E_1-10E_3, and 10F_1-10F_2 may be electrically coupled to the block ring 122 via the contacts 205 and the metal plate of the lowest metal layer. Compared with the continuous shielding structures 30A and 30B of the semiconductor structure 400 in Figure 8, the upper part of the gap between the shielding structures 10C_1-10C_3, the shielding structures 10D_1-10D_2, the shielding structures 10E_1-10E_3 and the shielding structures 10F_1-10F_2 can be The metal wires of the lowest metal layer are reserved for routing, thereby increasing layout flexibility. Furthermore, as previously described, by adjusting the configuration of the contacts 205 , the semiconductor structure 600 can be used as an N-type semiconductor structure for electrostatic discharge protection.

In embodiments of the present invention, by disposing a shielding structure formed of shielding polysilicon between the gate and the bulk ring of the semiconductor structure, high-voltage signals from the upper layer can be prevented from being coupled to the P-type well region of the gate. It can avoid turning on the parasitic NPN bipolar transistor, thereby preventing the generation of leakage current.

Although the present invention has been described above in terms of preferred embodiments, they are not intended to limit the invention. Anyone with ordinary skill in the art may make slight changes and modifications without departing from the spirit and scope of the invention. , therefore, the protection scope of the present invention shall be subject to the scope of the appended patent application.

10A,10A_1-10A_4:shielding structure 10B,10B_1-10B-_4: Shielding structure 10C_1-10C-_3: Shielding structure 10D_1-10D-_2: Shielding structure 10E_1-10E-_3: Shielding structure 10F_1-10F-_2: Shielding structure 15:Semiconductor substrate 30A: Shielded structure 30B: Shielding structure 50: Electrostatic discharge protection circuit 52:Joining pad 100:Semiconductor Structure 105a-105b: First well area 110a-110e: Second well area 120a-120e: Ring well area 122:Block Ring 125a-125d: First well area 130:Field Oxide 132a-132e: first doped region 134: Second doping region 205:Contact 210a-210e: Metal wire 215a, 215b: Electrode 300:Semiconductor Structure 400:Semiconductor Structure 500:Semiconductor Structure 510:Electrode 512,514,516: Sub-electrode 520,522:Metal wire 600:Semiconductor Structure D: Drainage area G: Gate S: source area VSS: ground terminal

Figure 1 is a top view of a semiconductor structure according to some embodiments of the invention. Figure 2 is a top view of the semiconductor structure of Figure 1 with metal lines and metal plates removed according to some embodiments of the present invention. Figure 3 is a cross-sectional view along line A-AA of the semiconductor structure in Figures 1-2 according to some embodiments of the present invention. Figure 4 is a cross-sectional view along line B-BB of the semiconductor structure in Figures 1-2 according to some embodiments of the present invention. Figure 5 shows a top view of a semiconductor structure according to some embodiments of the invention. Figure 6 is a cross-sectional view along line C-CC of the semiconductor structure of Figure 5 according to some embodiments of the present invention. FIG. 7 is a cross-sectional view along line D-DD of the semiconductor structure of FIG. 5 according to some embodiments of the present invention. Figure 8 shows a top view of a semiconductor structure according to some embodiments of the invention. Figure 9 is a cross-sectional view along line E-EE of the semiconductor structure of Figure 8 according to some embodiments of the present invention. Figure 10 is a top view of a semiconductor structure according to some embodiments of the invention. Figure 11 is a top view of the semiconductor structure of Figure 10 according to some embodiments of the invention. Figure 12 shows an electrostatic discharge protection circuit implemented by a semiconductor structure according to some embodiments of the present invention. Figure 13 shows a top view of a semiconductor structure according to some embodiments of the invention.

100:Semiconductor Structure

10A, 10B: shielding structure

110a, 110b: N-type well area

122:Block Ring

205:Contact

210a-210e: Metal wire

215a, 215b: Electrode

D: Drainage area

G: gate

S: source area

Claims (12)

A semiconductor structure including: a semiconductor substrate; At least one first well region is disposed in the semiconductor substrate and has a first conductivity type; At least one gate of a transistor is disposed above the at least one first well region and extends along a first direction; At least one second well zone and at least one third well zone are arranged on opposite sides of the at least one first well zone and extend along the first direction, wherein the at least one second well zone and the at least one third well zone The region has a second conductivity type, and the second conductivity type is complementary to the first conductivity type; A first shielding structure is disposed on at least one end of the at least one gate and partially overlaps the at least one first well region in a vertical projection direction, wherein the first shielding structure is separated from the at least one end of the at least one gate. one end; and A body ring is disposed in the semiconductor substrate and surrounds the at least one gate, the at least one second well region, the at least one third well region and the first shielding structure. The semiconductor structure of claim 1 further includes: A first electrode is formed above the first shielding structure, wherein the first shielding structure is electrically coupled to the block ring and electrically connected to a ground terminal through the first electrode. The semiconductor structure of claim 1 further includes: A second shielding structure is disposed between the other end of the at least one gate and the block ring and partially overlaps the at least one first well region in the vertical projection direction. The semiconductor structure of claim 1, wherein the bulk ring has the first conductivity type. The semiconductor structure of claim 1, wherein the at least one second well region and the at least one third well region are a source region and a drain region of the transistor, and the first shielding structure partially overlaps The at least one second well zone and the at least one third well zone. The semiconductor structure of claim 1 further includes: A first annular well region is formed in the semiconductor substrate, wherein the at least second well region is surrounded by the first annular well region; and A second annular well region is formed in the semiconductor substrate, wherein the third well region is surrounded by the second annular well region, wherein the first annular well and the second annular well have the third A conductivity type. The semiconductor structure of claim 6, wherein the first well region is formed between the first annular well region and the second annular well region. The semiconductor structure of claim 1, wherein the at least one gate, the at least one first well region, the at least one second well region and the at least one third well region are respectively a plurality and all are along the first direction. extending, and the gates, the second well regions and the third well regions are alternately arranged in a second direction, wherein the first direction is perpendicular to the second direction. The semiconductor structure of claim 8, wherein the second well regions and the third well regions are a source region and a drain region of the transistor. The semiconductor structure of claim 1 further includes: a first interconnect structure formed above the semiconductor substrate; a bonding pad formed over the semiconductor substrate, wherein the bonding pad is electrically coupled to a drain region of the transistor via the first interconnect structure; and a second interconnect structure formed above the semiconductor substrate; The at least one gate, a source region of the transistor, the bulk ring and the first shielding structure are electrically connected to a ground terminal through the second interconnection structure. The semiconductor structure of claim 1 further includes: a third shielding structure formed above the semiconductor substrate; The third shielding structure is disposed between the at least one second well region and/or the at least one third well region and the block ring, and the first shielding structure and the third shielding structure are disposed between the at least one second well region and/or the at least one third well region and the block ring. The same side of at least one gate. The semiconductor structure of claim 11, wherein the first shielding structure is electrically connected to the third shielding structure.

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