CN117673079A - ESD device of MOS structure - Google Patents
ESD device of MOS structure Download PDFInfo
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- CN117673079A CN117673079A CN202311363621.1A CN202311363621A CN117673079A CN 117673079 A CN117673079 A CN 117673079A CN 202311363621 A CN202311363621 A CN 202311363621A CN 117673079 A CN117673079 A CN 117673079A
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- Prior art keywords
- substrate
- trench isolation
- shallow trench
- esd device
- nmos
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- 239000000758 substrate Substances 0.000 claims abstract description 45
- 238000002955 isolation Methods 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 11
- 239000010410 layer Substances 0.000 claims description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 239000012212 insulator Substances 0.000 claims description 4
- 239000011229 interlayer Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 238000000605 extraction Methods 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides an ESD device with a MOS structure, which comprises a substrate, wherein the substrate is of a first conduction type; forming a first shallow trench isolation structure on the substrate to define an active region; a substrate lead-out area of a first conductivity type is formed on the outer side of the first shallow trench isolation; the active areas on two sides of the grid are formed with heavily doped areas of a second conductivity type for defining source and drain ends on two sides of the grid; the second shallow trench isolation structures are formed on the active area and distributed in an array mode, and are in a plurality of strip shapes in a overlook angle, and are used for dividing the active area into a plurality of strip-shaped active area structures which are distributed alternately; and the metal interconnection line structure is used for leading out the source electrode, the drain electrode, the substrate leading-out area and the grid electrode. The invention saves one SAB mask plate, avoids parallel ESD devices and saves the area of a chip.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an ESD device with a MOS structure.
Background
In CMOS integrated circuits, PMOS and NMOS are often used as input or output, but in Full Salicide (fully Salicide) process, NMOS/PMOS has substantially no ESD (electrostatic impeder) capability, and an extra SAB (metal silicide) mask (as shown in fig. 1 and 2) is required to be added to prevent metal silicide from forming between the gate and the contact hole at the drain end to improve the ESD self-protection capability of the device, which increases the cost; or an ESD device is connected in parallel to the corresponding MOS side (as shown in fig. 3), which increases the area.
In order to solve the above-mentioned problems, a new type of ESD device with MOS structure needs to be proposed.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an ESD device of a MOS structure for solving the problem that a cost-and area-reduced ESD device is required in the prior art.
To achieve the above and other related objects, the present invention provides an ESD device of a MOS structure, comprising:
a substrate of a first conductivity type;
a first shallow trench isolation structure is formed on the substrate to define an active region, and the first shallow trench isolation structure is annular in a overlook angle;
a substrate lead-out area of a first conductivity type is formed on the outer side of the first shallow trench isolation;
the active areas on two sides of the grid are formed with heavily doped areas of a second conductivity type for defining source and drain ends on two sides of the grid;
the second shallow trench isolation structures are formed on the active area and distributed in an array, the second shallow trench isolation structures are in a plurality of strips in a top view, the second shallow trench isolation structures are used for dividing the active area into a plurality of strip-shaped active area structures, and the strip-shaped active area structures and the second shallow trench isolation structures are distributed alternately;
and the metal interconnection line structure is used for leading out the source end, the drain end, the substrate leading-out area and the grid electrode.
Preferably, the substrate comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.
Preferably, the substrate is formed with an NMOS device.
Preferably, the first conductivity type in the NMOS device is P-type, and the second conductivity type is N-type.
Preferably, the substrate has a PMOS device formed thereon.
Preferably, the first conductivity type in the PMOS device is N-type and the second conductivity type is P-type.
Preferably, the gate is a metal gate.
Preferably, the first and second shallow trench isolation materials are spin-on glass (sog), dense oxide (hdp-cvdox) formed by high density plasma chemical vapor deposition, silicon dioxide (sio 2), or double filling with two materials of silicon dioxide and silicon nitride (sin).
Preferably, the metal interconnection line structure includes a contact hole structure formed in the interlayer film, and a metal interconnection layer electrically contacting the contact hole structure.
Preferably, the second shallow trench isolation structures are distributed in an equally-spaced array.
Preferably, the ESD device further comprises an output circuit: the drain electrode of a PMOS is connected with the drain electrode of an NMOS, the source electrode of the PMOS is connected with the power supply voltage, the source electrode of the NMOS is grounded, the grid electrodes of the PMOS and the NMOS are connected with the driving voltage, and the output end of the PMOS is connected between the drain electrode of the PMOS and the drain electrode of the NMOS.
As described above, the ESD device of the MOS structure of the present invention has the following advantageous effects:
the active regions of the invention are in a low-resistance state due to the injection of the heavily doped regions, and under the ESD condition, ESD current is uniformly dispersed to each active region at the drain end through the metal connecting wire and then flows out from the source end. The shallow trench isolation structure introduced by the drain terminal and the source terminal plays a certain role in ballasting, so that ESD current flows into the device more uniformly. The MOS device with the structure can improve the ESD self-protection capability, save one SAB mask plate, avoid parallel ESD devices and save the chip area.
Drawings
FIG. 1 is a schematic diagram of a metal silicide structure in a PMOS of the prior art;
FIG. 2 is a schematic diagram of a metal silicide structure in a NMOS of the prior art;
FIG. 3 shows a schematic diagram of a prior art parallel ESD device;
FIG. 4 is a schematic view of the NMOS structure of the present invention in a top view;
FIG. 5 is a schematic view showing a cross-sectional structure of an NMOS AA at a cross-sectional line according to the present invention;
FIG. 6 is a schematic diagram showing a cross-sectional structure of the NMOS BB cross-section line of the present invention;
FIG. 7 is a schematic diagram of a PMOS top view structure of the present invention;
FIG. 8 is a schematic diagram showing the cross-sectional structure of the PMOS AA at the cross-section line of the present invention;
FIG. 9 is a schematic diagram showing the cross-sectional structure of the PMOS BB section line of the present invention;
FIG. 10 is a schematic diagram of an output circuit according to the present invention;
FIG. 11 is a graph showing the comparison of the voltage-current curves and ESD capabilities of the NMOS and prior art NMOS test of the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
The invention provides an ESD device with a MOS structure, comprising:
a substrate 101, the substrate 101 being of a first conductivity type, for example, a PMOS with an N-well formed thereon and an NMOS with a P-well formed thereon;
in an embodiment of the present invention, the substrate 101 comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulator layer under a thin semiconductor layer that is an active layer of the SOI substrate. The semiconductor and bulk semiconductor of the active layer typically comprise crystalline semiconductor material silicon, but may also comprise one or more other semiconductor materials such as germanium, silicon germanium alloys, compound semiconductors (e.g., gaAs, alAs, inAs, gaN, alN, etc.) or alloys thereof (e.g., gaxAl1-xAs, gaxAl1-xN, inxGa1-xAs, etc.), oxide semiconductors (e.g., znO, snO2, tiO2, ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.
In an embodiment of the present invention, an NMOS device is formed on a substrate 101, and its top view structure is shown in fig. 4, and its cross-sectional structures at the AA cross-sectional line and the BB cross-sectional line are shown in fig. 5 and 6, respectively.
In the embodiment of the invention, the first conductive type in the NMOS device is P type, and the second conductive type is N type.
In an embodiment of the present invention, a PMOS device is formed on a substrate 101, and its top view structure is shown in fig. 7, and its cross-sectional structures at the AA cross-sectional line and the BB cross-sectional line are shown in fig. 8 and 9, respectively.
In an embodiment of the present invention, the first conductivity type in the PMOS device is N-type and the second conductivity type is P-type.
A first shallow trench isolation structure 102 is formed on the substrate 101 to define an active region, and the first shallow trench isolation structure 102 is annular from a top view;
a substrate lead-out region 103 of the first conductivity type is formed outside the first shallow trench isolation;
a plurality of substrate lead-out regions 103 crossing the active region, wherein the active regions on two sides of the substrate lead-out region 103 are formed with heavily doped regions of the second conductivity type for defining source and drain terminals (105, 106) on two sides of the substrate lead-out region 103;
in an embodiment of the present invention, the substrate extraction region 103 is a metal gate.
The second shallow trench isolation structures 107 are formed on the active area and distributed in an array, the second shallow trench isolation structures 107 are in a plurality of strip shapes when seen from a top view, the second shallow trench isolation structures 107 are used for dividing the active area into a plurality of strip-shaped active area structures, and the strip-shaped active area structures and the second shallow trench isolation structures 107 are distributed alternately;
in the embodiment of the invention, the first and second shallow trench isolation materials are spin-on glass (sog), dense oxide (hdp-cvdox) formed by high-density plasma chemical vapor deposition, silicon dioxide (sio 2) or double filling of two materials of silicon dioxide and silicon nitride (sin).
In an embodiment of the present invention, the second shallow trench isolation structures 107 are distributed in an equally spaced array.
A metal interconnect structure for extracting source and drain terminals (105, 106), a substrate extraction region 103, and a substrate extraction region 103.
The active regions are in a low-resistance state due to the injection of the heavily doped regions, and under the ESD condition, ESD current is uniformly dispersed to each active region at the drain end through the metal connecting wire and then flows out from the source end. The shallow trench isolation structure introduced by the drain terminal and the source terminal plays a certain role in ballasting, so that ESD current flows into the device more uniformly. The MOS device with the structure can improve the ESD self-protection capability, save one SAB mask plate, avoid parallel ESD devices and save the chip area.
In an embodiment of the present invention, the metal interconnect line structure includes a contact hole structure 108 formed in an interlayer film, and a metal interconnect layer electrically contacting the contact hole structure 108, the metal interconnect line structure being one or more layers, and the material of the interlayer film is typically silicon dioxide.
In an embodiment of the present invention, referring to fig. 10, the esd device further includes an output circuit: the drain of a PMOS is connected with the drain of an NMOS, the source of the PMOS is connected with the power supply Voltage (VDD), the source of the NMOS is grounded (VSS), the substrate lead-out areas 103 of the PMOS and the NMOS are connected with the driving voltage (Pre-Drive), and the Output PAD is connected between the drain of the PMOS and the drain of the NMOS.
Fig. 11 is a schematic diagram showing comparison between the test voltage and current curves and ESD capability of the NMOS device of the present invention and the NMOS device of the prior art, wherein the greater the failure current, the stronger the ESD capability, and the test shows that the NMOS device of the prior art has no ESD capability basically, and the failure current of the NMOS device of the present invention is 1.4A, and the capability is stronger.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In summary, the active regions of the present invention are injected into the heavily doped regions to form a low-resistance state, and under the ESD condition, ESD current is uniformly dispersed to each active region at the drain terminal via the metal connection line, and then flows out from the source terminal. The shallow trench isolation structure introduced by the drain terminal and the source terminal plays a certain role in ballasting, so that ESD current flows into the device more uniformly. The MOS device with the structure can improve the ESD self-protection capability, save one SAB mask plate, avoid parallel ESD devices and save the chip area. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (11)
1. An ESD device of a MOS structure comprising at least:
a substrate of a first conductivity type;
a first shallow trench isolation structure is formed on the substrate to define an active region, and the first shallow trench isolation structure is annular in a overlook angle;
a substrate lead-out area of a first conductivity type is formed on the outer side of the first shallow trench isolation;
the active areas on two sides of the grid are formed with heavily doped areas of a second conductivity type for defining source and drain ends on two sides of the grid;
the second shallow trench isolation structures are formed on the active area and distributed in an array, the second shallow trench isolation structures are in a plurality of strips in a top view, the second shallow trench isolation structures are used for dividing the active area into a plurality of strip-shaped active area structures, and the strip-shaped active area structures and the second shallow trench isolation structures are distributed alternately;
and the metal interconnection line structure is used for leading out the source end, the drain end, the substrate leading-out area and the grid electrode.
2. The ESD device of a MOS structure of claim 1, wherein: the substrate comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.
3. The ESD device of a MOS structure of claim 1, wherein: and an NMOS device is formed on the substrate.
4. A MOS structured ESD device as in claim 3 wherein: the first conductivity type in the NMOS device is P type, and the second conductivity type is N type.
5. The ESD device of a MOS structure of claim 1, wherein: the substrate has a PMOS device formed thereon.
6. The ESD device of a MOS structure of claim 5, wherein: the first conductivity type in the PMOS device is N-type, and the second conductivity type is P-type.
7. The ESD device of a MOS structure of claim 1, wherein: the grid electrode is a metal grid.
8. The ESD device of a MOS structure of claim 1, wherein: the first shallow trench isolation material and the second shallow trench isolation material are spin-on glass (sog), dense oxide (hdp-cvdox) formed by high-density plasma chemical vapor deposition, silicon dioxide (sio 2) or double filling of two materials of silicon dioxide and silicon nitride (sin).
9. The ESD device of a MOS structure of claim 1, wherein: the metal interconnection line structure includes a contact hole structure formed in an interlayer film, and a metal interconnection layer electrically contacting the contact hole structure.
10. The ESD device of a MOS structure of claim 1, wherein: the second shallow trench isolation structures are distributed in an array mode with equal intervals.
11. The ESD device of a MOS structure of claim 1, wherein: the ESD device further includes an output circuit: the drain electrode of a PMOS is connected with the drain electrode of an NMOS, the source electrode of the PMOS is connected with the power supply voltage, the source electrode of the NMOS is grounded, the grid electrodes of the PMOS and the NMOS are connected with the driving voltage, and the output end of the NMOS is connected between the drain electrode of the PMOS and the drain electrode of the NMOS.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311363621.1A CN117673079A (en) | 2023-10-20 | 2023-10-20 | ESD device of MOS structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311363621.1A CN117673079A (en) | 2023-10-20 | 2023-10-20 | ESD device of MOS structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117673079A true CN117673079A (en) | 2024-03-08 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311363621.1A Pending CN117673079A (en) | 2023-10-20 | 2023-10-20 | ESD device of MOS structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117673079A (en) |
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2023
- 2023-10-20 CN CN202311363621.1A patent/CN117673079A/en active Pending
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