TWI694580B - Transistor stacking structure - Google Patents

Abstract

The present invention provides a transistor stacking structure, including a plurality of stacking areas, which are surrounded by an STI, a plurality of gate, a plurality of source/drain regions, a source line, a drain line and a bit line. The gates are disposed in the stacking region, stretching along a first direction. The source/drain regions are disposed in the stacking region, arranged alternatively with the gates. The gate line stretches along the first direction. The source line stretches along the first direction. The source/drain regions between the source line and the gate line are floating.

Description

Transistor stack structure

The invention relates to a transistor stack structure, in particular to a transistor stack structure with a floating source and drain region.

With the advancement of technology, the integrated circuit process technology has been continuously improved, so various electronic circuits can be accumulated/formed on a single chip. At present, integrated circuit chips can be divided into core circuits and input/output (hereinafter referred to as I/O) circuits, and the core circuits and I/O circuits are driven by voltage sources of different sizes, respectively. In order to enable the core circuit and the I/O circuit to receive external voltage sources, the integrated circuit chip is provided with conductive power connection pads and I/O connection pads.

However, during the packaging, testing, transportation, processing, etc. of the chip, these connection pads are also prone to contact with the external electrostatic power source, and the excessive charge brought by it will enter and conduct into the chip within a very short time, resulting in The damage of the internal circuit of the chip is a phenomenon called electrostatic discharge. Therefore, general commercial integrated circuits must have a certain degree of tolerance to human body model (HBM) and machine model (hereinafter referred to as MM). For example, the tolerance of MM must be higher than 100 volts (V). In order to solve this problem, the industry usually sets an ESD protection device between the internal circuit and the I/O pin, which must be activated before the electrostatic discharge pulse (pulse) reaches the internal circuit to quickly eliminate excessive Voltage, which in turn reduces static electricity The destruction caused by the discharge phenomenon. Or, in some special communication chip circuit designs, high voltage resistant circuit designs are also often required. Therefore, there is an increasing demand in the industry for circuit designs that can withstand high voltages.

The present invention thus provides a transistor stack structure that can maintain high voltage alternating current (AC) signals, and is particularly suitable for use in communication circuit design.

The present invention then provides a transistor stack structure, which includes a plurality of stacked regions, a plurality of gates, a plurality of source/drain regions, a source line, a drain line, and a bit line. The stacked regions are each surrounded by a shallow trench isolation (STI). A plurality of gate lines are arranged in each of the stacking areas, and are arranged parallel to each other along a first direction. A plurality of source/drain regions are arranged in the stacking region and are arranged parallel to each other along the first direction, and the gate electrode and the source/drain regions are alternately arranged. The source line extends along the first direction and is electrically connected to one of the source/drain regions in different stacking regions. The drain line extends along the first direction and is electrically connected to one of the source/drain regions in different stacking regions, wherein the source/drain regions between the source line and the drain line are Floating electrically.

The present invention uses a special transistor stacking arrangement, which eliminates the need to provide contact plugs for each source/drain region, which can save manufacturing costs.

300: Semiconductor stack

302, 302A, 302B: Stacking area

304: Shallow trench isolation

306: Gate

306L: Word line

308: source/drain region

308SL: source line

301: Base

301B: Insulated part

308SC: source assembly line

308DL: Drain line

308DC: Drain line

309M: metal layer

309C: Plug

310: bit area

310L: bit line

301A: Semiconductor material part

309: Side wall

FIG. 1 is a top view of a transistor stack structure of the present invention.

FIG. 2 is a partially enlarged view of area B in FIG. 1.

Figs. 3 to 5 are cross-sectional views along the CC' tangent, DD' tangent, and EE' tangent in Fig. 2 respectively.

In order to enable those of ordinary skill in the art of the present invention to further understand the present invention, the following lists several preferred embodiments of the present invention, and in conjunction with the accompanying drawings, detailed description of the composition of the present invention and the desired Of efficacy.

The transistor stack structure 300 of the present invention is composed of a plurality of transistors connected in series with each other, that is, the drain of the previous transistor can be used as the source of the next transistor (shared source/drain region). When the gate is turned on, an electronic path can be formed in the source/drain interval in series. In one embodiment, the transistor stack structure 300 of the present invention is used as a voltage sustaining circuit. When the number of serially connected transistors is increased, a higher voltage can be allowed to pass, such as radio frequency (radio frequency, RF). Please refer to FIG. 1, which is a schematic diagram of one embodiment of the transistor stack structure of the present invention. The transistor stack 300 of the present invention is disposed on a substrate 301 and preferably has a silicon-containing material, such as silicon, single crystal silicon, single crystal silicon germanium, and amorphous silicon ) Or a combination of the above. In another embodiment, the substrate 301 may also contain other semiconductor materials, such as germanium or a III/V group compound semiconductor material, such as germanium arsenic. In the preferred embodiment of the present invention, the substrate 300 is a silicon on insulator (SOI) to increase the applicability to high voltage. Referring first to the cross-sectional view of FIG. 5, the substrate 301 includes a lower insulating portion 301B and an upper semiconductor material portion 301A, wherein the semiconductor material may have a small amount of dopant, such as an N-type with a first conductivity type Doped. Please refer to FIG. 1 again. FIG. 1 shows a dense array formed by stacking a plurality of transistors in series. The area A in this embodiment represents a transistor, which spans multiples in the first direction 400 In the stacking area 302, the transistors are arranged in series in a downward direction, that is, parallel to the second direction 402. The detailed description of the transistor stack will be described below.

Please refer to FIG. 2, the upper view presented in FIG. 2 is enlarged by the area B in FIG. 1. FIG. 2 shows two stacking regions 302: a stacking region 302A and a stacking region 302B. The configuration of the elements in the two is approximately the same. The turn-on of the transistor is controlled by the source line 308SL, the drain line 308DL, the word line 306L and the bit line 310L. Among them, the source line 308SL, the drain line 308DL and the first One direction 400 is parallel, the word line 306L and the bit line 310L are parallel along the second direction 402, and surrounded by these four lines, a basic stacking unit can be defined. Of course, as shown in FIG. 1, one stacking area 302 may also include a plurality of stacking units (extending toward the second direction 402), or may have a plurality of stacking areas 302 (extending toward the first direction 400), each stacking area Between 302 is surrounded by shallow trench isolation (STI).

For the component configuration of a basic unit, please refer to the upper view of Figure 2, and the cross-sectional views of Figure 3, Figure 4 and Figure 5, where Figures 3 to 5 are the second figure along the first Drawn by CC' tangent, DD' tangent and EE' tangent. Please refer to FIG. 2 first, in the area surrounded by the source line 308SL, the drain line 308DL, the word line 306L, and the bit line 310L in the stacking area 302A, a plurality of gates 306 and a plurality of source/drain areas are provided 308 and one-bit area 310. The gate 306 has a rail-like arrangement, and the source/drain regions 308 are embedded therein. Therefore, in the middle region, the gate 306 and the source/drain regions 308 are arranged in parallel along a first direction 400 and are staggered . The bit area 310 is located at the right end of the gate 306 and the source/drain area 308.

Regarding the word line 306L and the gate electrode 306, please refer to FIGS. 2 and 5, the word line 306L is electrically connected to the gate electrode 306 downward by a metal interconnection system, for example, through a plug 309. The plug 309 may be located above the shallow trench isolation 304, but in another embodiment, it may not be above the shallow trench isolation 304. The gate electrode 306 extends from the left to the right of the stack region 302 along the first direction 400 to one side of the bit region 310. The bit region 310 has a dopant of the second conductivity type, for example, P type. Similarly, bit zone 310 It is also connected to the bit line 310L through the plug 309. A gate dielectric layer 307 is provided between the gate 306 and the substrate 301, or a sidewall 309 may be provided on the sidewall of the gate 306. The gate electrode 306 may be made of various conductive materials, such as poly silicon or metal.

Regarding the source line 308SL and the source/drain region 308, please refer to FIGS. 2 and 3, the source/drain region 308 located at the upper end of the stacking region 302A is electrically connected to the source line 308SL through the metal interconnection system Sexual connection. A metal interconnection system such as a plurality of contact plugs 309C and one or more metal layers 309M, such as the first metal layer (metal one, M ₁ ), and the source line 308S is disposed above the metal layer 309M At the position of the second metal layer (metal two, M ₂ ). The source/drain region 308 has a dopant of the first conductivity type, for example, N type.

For the flow direction of the signal transmission of the stacked transistor 300 of the present invention, please refer to FIG. 2 and FIG. 4, the present invention is provided with 8 gates 306 and 9 source/drain regions 308 interleaved in the stacking region 302 When you want to operate, turn on the word line 306L of the stacking area 302 (please refer to Figure 5), the signal will be distributed to the source line 308SL of the same column by a source line 308SC, and the source line When the line 308S enters the source/drain region 308 located at the edge of the stacking region 302 through the metal layer 309M and the contact plug 309C (refer to FIG. 3 together), the signal passes from the second direction 402 through the series connected transistor Finally, the source/drain region 308 located at the other end of the stacking region 320A enters the drain line 308DL through the metal layer 309M and the contact plug 309C, and then outputs through the drain collection line 308DC, or; or through metal Layer 309M enters bit line 308 (please refer to Figure 5). Because of this, one of the features of the present invention is that when circulating between different transistors, the intermediate source/drain region 308 (located between the source line 308SL and the drain line 308DL) does not require additional Contact plugs are electrically floating. Compared with the conventional transistor stack structure as a high-voltage conductive design, the source/drain regions connected in series in each stacking region must be provided with plugs in order to pass the electronic signal to the next series connected Transistor, the invention Design can save many costs.

The above are only the preferred embodiments of the present invention, and all changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

302A, 302B: Stacking area

304: Shallow trench isolation

306: Gate

306L: Word line

308: source/drain region

308SL: source line

308SC: source assembly line

308DL: Drain line

308DC: Drain line

310: bit area

310L: bit line

Claims (12)

A transistor stack structure includes: a plurality of stacking regions, each of which is surrounded by a shallow trench isolation (STI); a plurality of gates are arranged in each of the stacking regions, and are arranged parallel to each other along a first direction A plurality of source/drain regions are arranged in the stacking regions, arranged parallel to each other along the first direction, the gates and the source/drain regions are interleaved; a source line is along the The first direction extends and is electrically connected to one of the source/drain regions in different stacking regions; and a drain line extends along the first direction and is electrically connected to one of the sources in different stacking regions Pole/drain region, wherein the source/drain regions between the source line and the drain line are electrically floating, wherein in one of the stacked regions, at the source line The source/drain regions between the drain line and the drain line are not electrically connected to any contact plugs. The transistor stack structure as described in item 1 of the scope of the patent application further includes a bit region disposed on each side of the stack region away from the source line, the bit region extending along the first direction. The transistor stack structure as described in item 2 of the patent application scope further includes a bit line electrically connected to the bit area, and the bit line extends along the second direction. The transistor stack structure as described in item 1 of the patent scope, wherein the source line is electrically connected to the source/drain regions in the same column in different stacking regions; the drain line is electrically The source/drain regions in the same row in different stacking regions are connected. The transistor stack structure as described in item 1 of the patent scope, in which one of the stacking areas In the example, the number of the gates between the source line and the drain line is N. The transistor stack structure as described in item 3 of the patent application scope, wherein the number of transistor stacks of the transistor stack structure is N. The transistor stack structure as described in item 3 of the patent application scope, wherein the stacking direction of the transistor stack structure is parallel to the gates. The transistor stack structure as described in item 1 of the patent application scope further includes a source assembly line, which is disposed on one side of the stacking regions, is electrically connected to the source line, and extends along a second direction . As in the transistor stack structure described in Item 8 of the patent application, the first direction is substantially perpendicular to the second direction. The transistor stack structure as described in item 9 of the patent application scope further includes a drain collecting line, which is disposed on the other side of the stacking regions relative to the source collecting line, the drain collecting line and the drain The wires are electrically connected and extend along the second direction. According to the transistor stack structure described in item 1 of the patent application scope, each stacking area has a word line on one side, and in each stacking area, the gate line is in electrical contact with the gates, And the gate lines extend along a second direction. The transistor stack structure as described in item 1 of the patent application scope, wherein the transistor stack structure is used in a radio frequency (radio frequency, RF) circuit.

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