CN113497026B - SOI grid grounding MOS device structure for electrostatic protection and manufacturing method thereof - Google Patents

SOI grid grounding MOS device structure for electrostatic protection and manufacturing method thereof Download PDF

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CN113497026B
CN113497026B CN202010257792.6A CN202010257792A CN113497026B CN 113497026 B CN113497026 B CN 113497026B CN 202010257792 A CN202010257792 A CN 202010257792A CN 113497026 B CN113497026 B CN 113497026B
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composite
drain
soi
esd
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CN113497026A (en
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陈晓亮
陈天
钱忠健
金兴成
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Wuxi China Resources Microelectronics Co Ltd
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Wuxi China Resources Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

The application relates to an SOI grid grounding MOS device structure for static electricity protection and a manufacturing method thereof, wherein the device structure comprises the following components: the well region is arranged on the insulating layer; the drain region is arranged at the upper part in the well region, and the outline of the drain region is a regular polygon; the composite region surrounds the drain region and is arranged at the upper part in the well region, the outline of the composite region is regular polygon on a plane, the composite region comprises a source region and a body contact region, and the body contact region is electrically connected with the source region; the grid electrode is arranged above the well region between the drain region and the composite region and forms a closed ring; the insulation isolation structure is arranged between the MOS tubes; wherein, the geometric centers of the outer contours of the drain region and the composite region on a plane are coincident, and each MOS tube is mutually connected in parallel. The application has large effective ESD area, is widely applicable to ESD device structures of fully-depleted SOI and partially-depleted SOI processes.

Description

SOI grid grounding MOS device structure for electrostatic protection and manufacturing method thereof
Technical Field
The application relates to the field of semiconductor manufacturing, in particular to an SOI grid grounding MOS device structure for electrostatic protection, and also relates to a method for manufacturing the SOI grid grounding MOS device structure for electrostatic protection.
Background
ESD (electro static discharge) for short, electrostatic discharge, ESD failure is one of the most common problems facing the electronics industry in terms of reliability, and up to 35% of integrated circuit failures are statistically ESD-induced, with losses to the electronics industry being in the billions of dollars each year. The ESD protection device is therefore critical to the stability and safe operation of the integrated circuit. The requirements of the industry on the ESD protection structure are also higher and higher, especially for applications under special environments such as high temperature, high humidity, strong radiation, etc., and the ESD device structure is required to have extremely high stability.
Silicon-on-insulator (SOI, silicon on Insulator) materials have an insulating layer (typically silicon dioxide) between the top silicon film and the substrate as isolation. The integrated circuit technology of the material is adopted to make devices such as MOS (metal oxide semiconductor field effect transistor) and the like on the top silicon film, and is an all-dielectric isolation technology. The latch-up effect of the traditional bulk silicon process is thoroughly eliminated by the technology; the method has the advantages of small parasitic capacitance, high speed, low power consumption, high integration level and the like. However, due to the existence of the electrically neutral body region and the influence of the full-dielectric isolation structure, when the MOS device works in a body suspension state, electron hole pairs generated by carrier impact ionization flow to the body region and accumulate in the body region, so that the potential of the body region is increased. Therefore, a series of parasitic effects such as a Kink effect, a single-tube latch-up effect, a memory effect and the like are brought to influence the characteristics of the MOS tube and the performance of the integrated circuit. To solve the body floating effect, the body is usually led out of the source or grounded to form a discharge path for the body charges.
SOI MOS devices can be classified into fully Depleted (see fig. 1) and partially Depleted (see fig. 2) SOI, depending on the relationship between the device depletion depth and the top silicon film thickness. GT in fig. 1 and 2 shows a gate electrode, PW shows a P well, BOX shows a buried oxide layer (insulating layer), and the blocks connected by the dotted lines in fig. 2 show the equivalent resistance between the P well and the p+ body contact region. Because of the isolation of the insulating medium under the top silicon film, the body region of the SOI device becomes a potential floating region, thereby causing phenomena such as warpage effect, single tube latch-up and the like, which are collectively called a body floating effect (Body floating effect). In order to eliminate the body-floating effect of this technique, a body contact technique is required to achieve control of the body potential. Existing SOI bulk contact techniques include: a BTS (Body Tied Source) structure (shown in fig. 3) in which the body contact region is connected to the body region via the source region bottom; and an "H" structure (as shown in fig. 4), and there is also a modification of the "H" structure, i.e., a "T" structure. The BTS structure is suitable for an SOI process that a depletion layer of a source region does not contact an oxygen-buried layer; the "T" or "H" type body contact structure sacrifices integrated circuit integration and body potential non-uniformity in the channel.
Disclosure of Invention
Based on this, it is necessary to provide a novel structure of an SOI gate grounded MOS device for electrostatic protection and a method for manufacturing the same.
An SOI gate-grounded MOS device structure for electrostatic protection comprising a substrate, an insulating layer on the substrate, and at least one ESD structure on the insulating layer, each of the ESD structures being a gate-grounded metal oxide semiconductor field effect transistor, comprising: a well region having a second conductivity type and provided on the insulating layer; a drain region having a first conductivity type, which is provided at an upper portion within the well region, an outer contour of the drain region being a regular polygon or a circle on a plane, the first conductivity type being a conductivity type opposite to the second conductivity type; the composite region surrounds the drain region and is arranged at the upper part in the well region, the outline of the composite region is regular polygon or circular on a plane, the composite region comprises a source region of a first conductivity type and a body contact region of a second conductivity type, and the body contact region is electrically connected with the source region; the grid electrode is arranged above the well region between the drain region and the composite region and forms a closed ring, and the body contact region is in direct contact with the well region positioned at the inner side of the composite region and below the grid electrode; the insulating isolation structure is arranged between the metal oxide semiconductor field effect transistors; the geometric center of the outer contour of the drain region on the plane coincides with the geometric center of the outer contour of the composite region on the plane, and the grid electrodes, the source electrodes and the drain electrodes of the metal oxide semiconductor field effect transistors are electrically connected with each other.
In one embodiment, the outer contours of the drain region, the composite region and the grid electrode are regular polygons on a plane, the number of sides is the same, and the connecting line of each corner of the composite region and the geometric center of the drain region passes through one corner of the drain region on the plane.
In one embodiment, the body contact regions are uniformly distributed in the composite region.
In one embodiment, the body contact region comprises a plurality of sub-regions distributed in the composite region, the sub-regions being separated from each other and separated by the source region.
In one embodiment, the regular polygon is a center symmetrical pattern.
In one embodiment, the regular polygon is a regular hexagon.
In one embodiment, each of the metal oxide semiconductor field effect transistors further includes a metal silicide layer disposed on an upper surface of the source region and an upper surface of the body contact region, the metal silicide layer shorting the source region and the body contact region.
In one embodiment, the metal silicide layer is further arranged on the upper surface of the grid electrode and the upper surface of the drain region, and the metal silicide layer is not arranged on the outer ring of the upper surface of the drain region, so that a silicon thin film resistor is formed on the outer ring.
In one embodiment, the insulating isolation structures extend down to the insulating layer, the insulating isolation structures being shallow trench isolation structures.
In one embodiment, the outer contour of the composite region is regular polygon in plane, and at least one side of the composite region of each metal oxide semiconductor field effect transistor is adjacent to one side of the composite region of another metal oxide semiconductor field effect transistor and is separated by the insulating isolation structure.
In one embodiment, each of the mosfet further includes an ESD doped region located in the well region in contact with a bottom surface of the drain region, the ESD doped region having a second conductivity type and a doping concentration greater than a doping concentration of the well region.
A method for manufacturing an SOI gate grounded MOS device structure for electrostatic protection comprises the step of carrying out ESD implantation, wherein the implanted ions are of a second conductivity type, and the implantation depth is the position, in the well region, in contact with the bottom surface of the drain region, so that an ESD doped region is formed at the position, in contact with the bottom surface of the drain region, of the well region, and the doping concentration of the ESD doped region is larger than that of the well region.
A method of fabricating an SOI gate grounded MOS device structure for electrostatic protection, the device structure comprising a substrate, an insulating layer on the substrate, and at least one ESD structure on the insulating layer, each of the ESD structures being a gate grounded metal oxide semiconductor field effect transistor, comprising: a well region having a second conductivity type and provided on the insulating layer; a drain region having a first conductivity type, which is provided at an upper portion within the well region, an outer contour of the drain region being a regular polygon or a circle on a plane, the first conductivity type being a conductivity type opposite to the second conductivity type; the composite region surrounds the drain region and is arranged at the upper part in the well region, the outline of the composite region is regular polygon or circular on a plane, the composite region comprises a source region of a first conductivity type and a body contact region of a second conductivity type, and the body contact region is electrically connected with the source region; the grid electrode is arranged above the well region between the drain region and the composite region and forms a closed ring, and the body contact region is in direct contact with the well region positioned at the inner side of the composite region and below the grid electrode; the insulating isolation structure is arranged between the metal oxide semiconductor field effect transistors; wherein, the geometric center of the outer contour of the drain region on the plane coincides with the geometric center of the outer contour of the composite region on the plane, the grid electrodes of the metal oxide semiconductor field effect transistors are electrically connected with each other, the source electrodes are electrically connected with each other, and the drain electrodes are electrically connected with each other; the method comprises the following steps: forming a metal silicide blocking layer on the outer ring of the upper surface of the drain region; and forming a metal silicide layer, wherein the metal silicide layer is formed on the upper surface of the source region, the upper surface of the body contact region, the upper surface of the grid electrode and the upper surface of the drain region, and the metal silicide layer is short-circuited with the source region and the body contact region. .
In one embodiment, the outer contours of the drain region, the composite region, the gate electrode and the metal silicide blocking layer are regular polygons in plane and have the same number of sides.
In the above-mentioned SOI gate grounded MOS device structure for electrostatic protection, an annular composite region (including a source region and a body contact region) is used to surround the drain region, and the body contact region is electrically connected with the source region, the gate is a closed ring, and the portion of the whole gate grounded metal oxide semiconductor field effect transistor surrounded by the insulating isolation structure is an effective ESD area, so that the effective ESD area occupies a large proportion of the total area of the gate grounded metal oxide semiconductor field effect transistor. And the body contact region of the device structure is in direct contact with the well region at the inner side of the composite region and below the grid electrode, so that the ESD device structure commonly used for the fully-depleted SOI and partially-depleted SOI processes has good process compatibility and wide application range.
Drawings
For a better description and illustration of embodiments and/or examples of those applications disclosed herein, reference may be made to one or more of the accompanying drawings. Additional details or examples used to describe the drawings should not be construed as limiting the scope of the disclosed application, the presently described embodiments and/or examples, and any of the presently understood modes of carrying out the application.
FIG. 1 is a schematic diagram of an exemplary fully depleted SOI structure;
FIG. 2 is a schematic diagram of an exemplary partially depleted SOI structure;
fig. 3 is a schematic diagram of an exemplary BTS body contact architecture;
FIG. 4 is a schematic illustration of an exemplary "H" shaped body contact configuration;
FIG. 5 is a schematic plan view of a single grounded gate MOSFET in one embodiment;
FIG. 6 is a schematic cross-sectional view of an embodiment of a partially depleted SOI structure taken along line A-A' of FIG. 5;
FIG. 7 is a schematic cross-sectional view of an embodiment of a partially depleted SOI structure taken along line B-B' of FIG. 5;
FIG. 8 is a schematic plan view of a plurality of regular hexagonal ESD cells according to one embodiment;
FIG. 9 is a schematic plan view of a plurality of regular hexagonal ESD cells in another embodiment;
FIG. 10 is a schematic cross-sectional view of an embodiment of a fully depleted SOI structure taken along line A-A' of FIG. 5;
fig. 11 is a schematic cross-sectional view of an embodiment of a fully depleted SOI structure along the line B-B' shown in fig. 5.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.
The term "semiconductor" used herein is a technical term commonly used by those skilled in the art, for example, for P-type and N-type impurities, p+ type represents P type with heavy doping concentration, P type with medium doping concentration, P-type represents P type with light doping concentration, n+ type represents N type with heavy doping concentration, N type represents N type with medium doping concentration, and N type represents N type with light doping concentration.
The present application proposes an ESD protection unit with a ring structure, fig. 5 is a schematic plan view of a single grounded gate mosfet in an embodiment, fig. 6 is a schematic cross-sectional view of a partially depleted SOI structure along line A-A 'shown in fig. 5, and fig. 7 is a schematic cross-sectional view of a partially depleted SOI structure along line B-B' shown in fig. 5. Referring to fig. 5-7, an SOI gate grounded MOS device structure for electrostatic protection includes a substrate 110, an insulating layer 120 on the substrate 110, and at least one ESD structure (ESD cell) on the insulating layer 120, each ESD structure being a gate grounded metal oxide semiconductor field effect transistor (GGNMOS or GGPMOS). Fig. 5 to fig. 7 illustrate the technical scheme of the present application by taking GGNMOS as an example, and it can be understood that the structure of the SOI gate grounding MOS device for electrostatic protection of the present application is also applicable to GGPMOS.
Each GGNMOS (shown in fig. 5-7) includes a well region 130, a drain region 10, a source region 50, a gate 40, a body contact region 60, and an insulating isolation structure 70. The well region 130 has a second conductivity type and is disposed on the insulating layer 120 to serve as a body region of the device. In one embodiment, the drain region 10, the source region 50, and the body contact region 60 are implanted to the same depth. In one embodiment, the body contact region 60 has an implant depth that is less than the implant depth of the source region 50. In one embodiment, body contact region 60 has an implant depth greater than the implant depth of source region 50. The drain region 10 has a first conductivity type and is disposed in an upper portion of the well region 130. The outer contour of the drain region 10 is regular polygon or circular in plan, and regular hexagon in the embodiment shown in fig. 5. The source region 50 of the first conductivity type and the body contact region 60 of the second conductivity type constitute a composite region disposed around the drain region 10 at an upper portion within the well region 130, and the body contact region 60 is electrically connected to the source region 50, the body contact region 60 being in direct contact with the well region 130 located inside the composite region and below the gate 40 (i.e., the body contact region 60 is in direct contact with the well region 130 surrounded by the composite region). The outer contour of the composite region is regular polygon or circular in plan, and regular hexagon in the embodiment shown in fig. 5. The gate electrode 40 is disposed over the well region 130 between the drain region 10 and the composite region and forms a closed loop. The insulating isolation structure 70 is disposed between the mosfets to realize insulating isolation between the well regions 130 of the mosfets.
Wherein, the geometric center of the outer contour of the drain region 10 on the plane coincides with the geometric center of the outer contour of the composite region on the plane, the grids of the metal oxide semiconductor field effect transistors are electrically connected with each other, the sources are electrically connected with each other, and the drains are electrically connected with each other, namely, the ESD units are connected in parallel.
For the embodiment of GGNMOS (gate grounded N-channel metal oxide semiconductor field effect transistor), the first conductivity type is N-type and the second conductivity type is P-type; for the GGPMOS (gate grounded pmos field effect transistor) embodiment, the first conductivity type is P-type and the second conductivity type is N-type.
In the above-mentioned structure of the SOI gate grounding MOS device for electrostatic protection, the annular composite region (including the source region 50 and the body contact region 60) is used to surround the drain region 10, and the body contact region 60 is electrically connected with the source region 50, the gate 40 is a closed loop, and the portion of the whole gate grounding mosfet surrounded by the insulating isolation structure 70 is an effective ESD area, so that the effective ESD area occupies a large proportion of the total area of the gate grounding mosfet. In one embodiment, the body contact regions 60 are uniformly distributed in the composite region, so that the parasitic triode base series resistance of the device is approximately equal everywhere, and when an electrostatic discharge (ESD) event occurs, the ESD device cells are guaranteed to be turned on substantially uniformly in all directions at the same time, thereby improving the bleeder efficiency and thus improving the ESD capability. In one embodiment, body contact region 60 is a plurality of sub-regions distributed in a composite region, the sub-regions being separated from each other and separated by source region 50; in a further embodiment, these subregions are centrosymmetric, the centre of symmetry being the geometric centre of the drain region 10. In one embodiment, body contact region 60 is a single region distributed in a composite local area. In the embodiment shown in fig. 5, the cross-sectional area of body contact region 60 (i.e., the area in the plane of fig. 5) is less than the cross-sectional area of source region 50. In the embodiment shown in fig. 5, the sub-regions extend in plan from the midpoint of each side of the composite region inner profile (gate 40 outer profile) to the midpoint of each side of the outer profile (insulating isolation structure 70 inner profile).
In one embodiment, the drain region 10 and the outer contour of the composite region are collinear in their plane of symmetry (here the axis of symmetry of a regular polygon, in particular the axis of symmetry passing through the midpoint of at least one side of the polygon). The symmetry of the ESD unit can be ensured by the arrangement, so that the ESD unit is enabled to be opened uniformly in all directions at the same time, and the discharging uniformity of the ESD current is improved. Also to achieve this effect, in one embodiment the pattern of the outer contours of the drain region 10 and the composite region in plan is a centrosymmetric pattern. In one embodiment, the outer contours of the drain region 10, the composite region and the gate electrode 40 are regular polygons in a plane, and the number of sides is the same, and the connection line between each corner of the composite region and the geometric center of the drain region passes through one corner of the drain region 10 and one corner of the gate electrode 40 in the plane. This layout is also intended to improve ESD current drain uniformity. In one embodiment, each side of the composite region is parallel to a corresponding side of the projection of gate 40 onto the horizontal plane.
Referring to fig. 6 and 7, in some embodiments, each mosfet further includes a metal silicide layer 80 disposed on the upper surface of source region 50 and the upper surface of body contact region 60, metal silicide layer 80 shorting source region 50 to body contact region 60. Body contact region 60 and source region 50 form an ohmic contact with metal silicide 80.
In the embodiment shown in fig. 6 and 7, the metal silicide layer 80 is further provided on the upper surface of the gate electrode 40 and the upper surface of the drain region 10, and the outer periphery of the upper surface of the drain region 10 is not provided with the metal silicide layer so that the position is free of a conductive structure (conductive film), thereby forming a silicon thin film resistor at the position, which can resist the impact of a part of ESD current.
In the embodiment shown in fig. 5, the metal silicide blocking layer (SAB) 30 is provided so that the outer periphery of the drain region 10 does not form a metal silicide layer. Note that, the dashed hexagon in fig. 5 indicates the inner contour of the metal silicide blocking layer 30, but in fig. 5, the outer contour of the drain region 10 is not the inner contour of the metal silicide blocking layer 30, and the outer contour of the drain region 10 is blocked by the metal silicide blocking layer 30. In the embodiment shown in fig. 5, the outer contour of the drain region 10 coincides in plan with the outer contour of the metal silicide blocking layer 30 (i.e., at the location of the inner contour of the gate electrode 40).
A suitable number of ESD cells may be combined as an SOI gate grounded MOS device structure for electrostatic protection according to the present application, each isolated by an insulating isolation structure 70, depending on the actually required ESD capability. Increasing the number of the ESD units can provide more and more uniform discharge paths for the discharge flow of the drain-side ESD, and improve the ESD protection capability. One skilled in the art can adjust the number of ESD cells according to the ESD design requirements to achieve various ESD specifications.
In one embodiment, the outer contours of the drain region 10, the composite region and the gate electrode 40 are regular polygons in plan and are centrosymmetric, i.e. regular polygons with an even number of sides, such as squares, regular hexagons, regular octagons, regular dodecagons or regular dodecagons. Regular polygons with even sides are orderly arranged on a wafer (wafer) to have higher utilization rate of the wafer area.
In one embodiment, the outer contour of the composite region is a regular polygon in plan, at least one side of the regular polygon being adjacent to one side of the composite region of another mosfet and being separated by an insulating isolation structure 70.
Fig. 8 is a schematic plan layout view of a plurality of regular hexagonal ESD cells in an embodiment, which may be centered on one ESD cell, and one or more circles of ESD cells are disposed around the periphery thereof. Fig. 8 shows only the outline of the body contact region of each ESD cell, omitting the specific structure of the ESD cells, and the white region between each black ESD cell is an insulating isolation structure. Fig. 9 shows a specific structure of each ESD cell. In the embodiment shown in fig. 6 and 7, the insulating isolation structure 70 extends down to the insulating layer 120, thereby forming a closed insulating structure with the insulating layer 120. Isolation structure 70 separates the ESD cells to prevent the ESD cells from interfering with each other and from parasitic turn-on.
In the embodiment shown in fig. 6 and 7, a gate dielectric layer, specifically, a gate oxide layer, is further disposed on the well region 130 and under the gate electrode 40.
In the embodiment shown in fig. 6 and 7, the two sides of the gate 40 are further provided with side walls, and Lightly Doped Drain (LDD) regions, specifically NLDD regions in fig. 6 and 7, are further provided below the side walls at positions adjacent to the drain 10 and the source region 50.
In one embodiment, drain region 10, source region 50, and body contact region 60 are all heavily doped regions having a doping concentration greater than the doping concentration of well region 130.
In one embodiment, gate 40 is a polysilicon gate.
In one embodiment, the insulating isolation structure 70 is a shallow trench isolation Structure (STI).
In one embodiment, insulating layer 120 is a buried oxide layer.
In one embodiment, the substrate 110 is a silicon substrate.
In one embodiment, the mosfet further includes an ESD doped region having the second conductivity type and a doping concentration greater than that of the well region 130, wherein the ESD doped region is located in the vicinity of a position in the well region 130 in contact with the bottom surface of the drain region 10 in the vertical direction. The purpose of the ESD doped region is to increase the doping concentration of the well region 130 at the location of the PN junction formed with the drain region 10, thereby reducing the breakdown voltage of the PN junction. In one embodiment, the ESD doped region has a slightly larger area in the plane than the area of the drain region 10 in the plane (e.g., may be the same and slightly larger shape as the drain region, with an orthographic projection covering the drain region 10); it will be appreciated that in other embodiments, the area of the ESD doped region is set smaller (e.g. the orthographic projection coincides with the drain region 10 or is smaller than the drain region 10), and the effect of reducing the breakdown voltage of the PN junction can be obtained as well, but the effect may be worse.
In the embodiment shown in fig. 5, the outer contours of the drain region 10, the metal silicide blocking layer 30, the gate electrode 40 and the composite region are all regular hexagons in plan. In other embodiments, the drain region 10, the metal silicide blocking layer 30, the gate electrode 40, and the outer contour of the composite region of the same ESD cell may not be the same pattern in a plane, for example, a partial region is regular hexagon, a partial region is square, and a partial region is circular.
Fig. 10 and 11 illustrate embodiments of fully depleted SOI structures. For embodiments of fully depleted SOI structures, the depletion layer of source region 50 contacts insulating layer 120 and well region 130 tends to be thinner. In some embodiments, drain region 10 is formed by a single ion implantation step with source region 50, which may result in drain region 10 and source region 50 contacting insulating layer 120 in a thin SOI structure of well region 130, resulting in isolation of body region (well region 130) from source region 50. The body contact region 60 of the device structure is in direct contact with the well region 130 inside the composite region and below the gate 40, so that the ESD device structure commonly used in the fully-depleted SOI and partially-depleted SOI processes has good process compatibility and wide application range.
The application also correspondingly provides a method for manufacturing the SOI grid grounding MOS device structure for static electricity protection. In one embodiment, the forming of the ESD doped region specifically includes ESD implantation, wherein the implanted ions are of the second conductivity type, and the depth of implantation is a position in the well region in contact with the bottom surface of the drain region, so that the ESD doped region is formed at a position in contact with the bottom surface of the drain region, and the doping concentration of the ESD doped region is greater than that of the well region.
In one embodiment, the method comprises:
and forming a metal silicide blocking layer on the upper surface of the outer ring of the drain region.
And forming a metal silicide layer. The metal silicide layer is formed on the upper surface of the source region, the upper surface of the body contact region, the upper surface of the grid electrode and the upper surface of the drain region, and is not provided with a metal silicide blocking layer, and the metal silicide layer short-circuits the source region and the body contact region.
In one embodiment, the outer contours of the drain region, the composite region grid electrode and the metal silicide blocking layer are regular polygons in plane and have the same edge number.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.

Claims (14)

1. An SOI gate grounded MOS device structure for electrostatic protection comprising a substrate, an insulating layer on the substrate, and at least one ESD structure on the insulating layer, characterized in that,
each of the ESD structures is a grounded gate mosfet comprising:
a well region having a second conductivity type and provided on the insulating layer;
a drain region having a first conductivity type, which is provided at an upper portion within the well region, an outer contour of the drain region being a regular polygon or a circle on a plane, the first conductivity type being a conductivity type opposite to the second conductivity type;
the composite region surrounds the drain region and is arranged at the upper part in the well region, the outline of the composite region is regular polygon or circular on a plane, the composite region comprises a source region of a first conductivity type and a body contact region of a second conductivity type, and the body contact region is electrically connected with the source region;
the grid electrode is arranged above the well region between the drain region and the composite region and forms a closed ring, and the body contact region is in direct contact with the well region positioned at the inner side of the composite region and below the grid electrode;
the insulating isolation structure is arranged between the metal oxide semiconductor field effect transistors;
the geometric center of the outer contour of the drain region on the plane coincides with the geometric center of the outer contour of the composite region on the plane, and the grid electrodes, the source electrodes and the drain electrodes of the metal oxide semiconductor field effect transistors are electrically connected with each other.
2. The structure of claim 1, wherein the outer contours of the drain region, the composite region and the gate are regular polygons and have the same number of sides, and the line connecting each corner of the composite region and the geometric center of the drain region passes through one corner of the drain region.
3. The SOI gate grounded MOS device structure for electrostatic protection of claim 1, wherein the body contact regions are uniformly distributed in the composite region.
4. The SOI gate grounded MOS device structure for electrostatic protection of claim 3, wherein the body contact region comprises a plurality of sub-regions distributed in the composite region, each sub-region being separated from each other and separated by the source region.
5. The SOI gate grounded MOS device structure for electrostatic protection of claim 2, wherein the regular polygon is a center symmetric pattern.
6. The SOI gate grounded MOS device structure for electrostatic protection of any one of claims 2-5, wherein the regular polygon is a regular hexagon.
7. The SOI gate grounded MOS device structure of claim 1, wherein each of the metal oxide semiconductor field effect transistors further comprises a metal silicide layer disposed on an upper surface of the source region and an upper surface of a body contact region, the metal silicide layer shorting the source region and the body contact region.
8. The structure of claim 7, wherein the metal silicide layer is further disposed on the upper surface of the gate and the upper surface of the drain, and the outer periphery of the upper surface of the drain is not disposed with the metal silicide layer so as to form a silicon thin film resistor on the outer periphery.
9. The SOI gate grounded MOS device structure for electrostatic protection of claim 1, wherein the insulating isolation structure extends down to the insulating layer, the insulating isolation structure being a shallow trench isolation structure.
10. The SOI gate grounded MOS device structure of claim 1, wherein the outer contour of the composite region is regular polygon in plan, at least one side of the composite region of each of the mosfets being adjacent to one side of the composite region of another mosfet and separated by the insulating isolation structure.
11. The SOI gate grounded MOS device structure of claim 1, wherein each of the mosfet further comprises an ESD doped region in the well region in contact with a bottom surface of the drain region, the ESD doped region having a second conductivity type and a doping concentration greater than a doping concentration of the well region.
12. A method of fabricating an SOI gate grounded MOS device structure for electrostatic protection as claimed in any one of claims 1 to 10 comprising the step of performing an ESD implant of a second conductivity type to a depth of the well region where it contacts the bottom surface of the drain region, thereby forming an ESD doped region where it contacts the bottom surface of the drain region, the ESD doped region having a doping concentration greater than the doping concentration of the well region.
13. A method of forming a grounded-SOI MOS device structure for electrostatic protection as defined in claim 12 comprising the step of forming a metal silicide blocking layer on an outer periphery of an upper surface of the drain region.
14. The method of claim 13, wherein the outer contours of the drain region, the composite region, the gate and the metal silicide blocking layer are regular polygons in plan and have the same number of sides.
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