JP2987105B2 - Flash EEprom memory system and its use - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD OF THE INVENTION

The present invention generally relates to electrically programmable read only memory (Eprom) semiconductors and electrically erasable and programmable read only memory (EEprom), and more particularly to such semiconductors. Related to technology that utilizes

[0002]

[Prior art]

BACKGROUND OF THE INVENTION An electrically programmable read only memory (Eprom) has a field effect transistor structure and a floating conductive gate (disconnected) provided between a source and a drain region insulated from a channel of a semiconductor substrate region. ) Is used. The control gate is provided above the floating gate and is insulated therefrom. The threshold voltage characteristics of the transistor are controlled by the amount of charge trapped on the floating gate. That is, to allow conduction between its source and drain regions, the voltage that must be applied to its control gate before the transistor is turned on, ie, its voltage is its threshold voltage, its minimum voltage Threshold voltage). Transistors operate in one of two states by accelerating electrons to the floating gate through a thin dielectric gate in the channel region of the substrate.
You can program one.

[0003] The state of a transistor in a memory cell can be read by applying operating voltages to the source, drain and control gate of the transistor, and then detecting the current flowing between the source and drain when the control gate voltage is selected. By doing so, it is possible to know whether the device is programmed on or off. To address a particular cell in a two-dimensional array of Eprom cells for reading, the source and drain voltages are applied between the source and drain lines of the column containing the cell to be addressed. And applying a control voltage to the control gate of the matrix containing the cell to be addressed.

[0004] Examples of such memory cells are triple polysilicon, channel-separated electrically erasable and programmable read only memory (Eprom). Since the floating and control gates extend over adjacent portions of the channel, which is split Cha
It is called a channel device . Thus, the transistor structure acts as two transistors in series, one having a variable threshold channel responsive to the charge level on the floating gate, the other being unaffected by the charge on the floating gate, Rather, it works in response to the voltage applied to its control gate, similar to a normal field effect transistor.

[0005] Such a memory cell is called triple polysilicon. This is because it has a triple conductive layer of polysilicon material. An erase gate is included in addition to the floating and control gates. The erase gate passes close to the floating gate surface of each memory cell transistor,
They are insulated from them by a thin tunnel dielectric (having a tunnel effect). Charge is removed from the floating gate of the cell to the erase gate when the appropriate voltage is applied to all transistors. When the entire array of cells or a particular group of cells are erased at the same time (ie, by flash), such Eprom's cells are referred to as flash Eprom arrays.

EEprom has become known to have a finite useful life. The number of times such devices can be programmed and erased before performance degrades is finite. Its features are dependent on the particular structure, but its programmability decreases after more than 10,000 use cycles. After such a device has been used for more than 100,000 cycles, it can no longer be programmed and properly erased. This is believed to be the result of the charge being transferred or removed to the floating gate for programming or erasing being trapped in the dielectric.

[0007]

The object of the present invention is to provide an Ep
It is an object of the present invention to provide techniques, methods and systems for increasing the amount of information stored in an array of roms or EEproms.

[0008]

SUMMARY OF THE INVENTION To achieve the above object, a method according to the present invention comprises: (1) an array of electrically changeable memory cells that can change state and are addressable for reading. Wherein each memory cell includes a field effect transistor having a floating gate and has a threshold voltage level, the level having a given level when there is no net charge on said floating gate,
For a memory array that is variable by the net amount of charge held by the floating gate, in a method of changing the state of addressed cells of the array: corresponding to the state of more than two detectable individual cells Establishing a plurality of more than two effective threshold voltage levels, wherein at least two of the plurality of effective threshold voltage levels are derived from a net positive charge of the floating gate. And until the effective threshold voltage of the addressed cell is substantially equal to one of the plurality of effective threshold voltage levels.
Setting the detectable state of the addressed cell by changing the amount of charge on the floating gate of the addressed cell.

(2) The method according to (1), wherein the set of detectable states is the voltage of the effective threshold of the addressed cell by applying a negative charge to the floating gate of the addressed cell. Changing the level. (3) The method according to (1), further comprising, before setting the detectable state of the addressed cell, presetting an effective threshold voltage of the addressed cell to a preset level. . (4) The method according to (1), wherein prior to setting the detectable state of the addressed cells, an array including cells addressed by varying the amount of charge on a floating gate of the group of cells. Presetting the effective threshold voltage level of the group of cells at a preset level.

(5) The method according to (4), wherein the presetting of the group of cells includes setting the group of cells to a preset effective threshold voltage level that is outside the range of the plurality of effective threshold voltage levels. Including the step of presetting. (6) In the method according to (4), the presetting of the group of cells is performed by removing a negative charge of the floating gate to thereby reduce the plurality of effective threshold levels corresponding to the states of the plurality of cells. Establishing a preset effective threshold voltage level of the group of cells at a level lower than a lowest one, and a set of detectable states of the addressed cell is determined by a floating gate of the addressed cell Applying a negative charge to (7) The method according to (4), further comprising, after setting the detectable state of the addressed cell, reading the set state of the addressed cell. (8) The method according to (7), wherein the reading of the set state of the addressed cell includes flowing a current through the addressed cell, and at the same time, a level of the current and two or more reference currents. Comparing with the level. (9) In the method according to (1), after setting the detectable state of the addressed cell, flowing a current through the addressed cell and simultaneously referring to the level of the current by more than one reference. An additional step of reading the set state of the addressed cell by comparing with the current level is included. (10) The method according to (9), wherein the level of the current is compared with a plurality of reference current levels one less than the plurality of effective threshold levels.

(11) In the method according to any one of (1) to (10), the step of establishing a plurality of effective threshold voltage levels is generated from a net positive charge on the floating gate. Establishing a majority of said threshold level. (12) In the method according to any one of the above (1-10), establishing a plurality of effective threshold voltage levels comprises establishing at least four such threshold voltage levels. . (13) The method according to any one of (1 to 10), wherein the given threshold level of the individual cell is set to at least 3 volts.

(14) Any one of the above (3-5)
The method of any one of the preceding claims, further comprising the step of adding a total count of the number of times the group of cells is preset. (15) The method according to any one of (3 to 5), further comprising the step of replacing the group of cells with an auxiliary block of cells in the array when the group of cells becomes unavailable. (16) The method according to any one of (1) and (3), further comprising a step of replacing the addressed cell with an auxiliary good cell in the array in a case where the addressed cell is destroyed.

To achieve the above object, a system according to the present invention comprises: (17) an array of a plurality of electrically erasable and programmable read-only memory cells, each cell formed on a semiconductor substrate, wherein said substrate is A transistor having a source and a drain separated by a channel region, a floating gate located on and insulated from at least a portion of the channel region, and a control gate extending over and insulated from the floating gate. Has an effective threshold voltage derived from a combination of a natural threshold voltage and a voltage corresponding to the level of controllable charge on its floating gate, wherein the natural threshold voltage is Has a charge level equal to zero,
Correspondingly, in a system for erasing, programming and reading memory states of cells in said array: operatively connected to said array to address a selected one or group of memory cells. Means for driving the effective threshold voltage of the addressed cell or group of cells to a ground level by altering the charge on the floating gate of each addressed cell. Erasing means and programming means operatively connected to the array, for changing the charge on the floating gate of the addressed cell, providing two corresponding to more than two individual detectable states. Changing to one of a plurality of exceeding effective threshold voltage levels until the effective threshold voltage is substantially equal; Wherein at least two of the plurality of effective threshold voltage levels are derived from a controllable charge level on the floating gate that is positive, and to determine an amount of current flowing through the addressed cell. And read means operably connected to said array, whereby the state of the cell addressed is determined by the measured current level flowing therethrough.

(18) In the memory system according to (17), the program means has an effective threshold voltage of one of at least four effective threshold voltage levels.
And means for altering the charge on the floating gate of the addressed cell until they are substantially equal, whereby the individual cells of said array are programmable to four or more states. (19) In the memory system according to (17),
The natural threshold voltage level is at least 3 volts. (20) In the memory system of (17), the means responsive to the erasing means drives an effective threshold voltage of the addressed cell or group of cells to a ground level, and the addressed cell or cell Additionally includes means for accumulating the running count stored in the array for the number of times that the group has been erased and increasing by one.

Further and other advantages and advantages of the present invention, together with the preferred embodiments, will be described with reference to the accompanying drawings.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, there is shown the structure of a channel-separated Eprom or EEprom cell, which is an improved memory array and its operation according to the present invention. It is suitable. Semiconductor substrate 11
Has a source region 13 and a drain 15, which are usually formed by ion implantation. A channel region 17 is provided between the source and the drain.
A floating gate 19 is provided above the portion of the channel region labeled L1 and is separated from the substrate by a thin gate oxide 21. A control gate 23 is formed in an upper portion of the channel region where L2 is attached, and is separated from the substrate 11 by a thin gate oxide layer 25. Control 23 is also electrically isolated from floating gate 19 by oxide layer 27. The amount of charge on floating gate 19 is programmed to correspond to the desired state to be stored in the cell. If the level of this charge exceeds a predetermined threshold, the cell is considered to be in one state. If it is below that threshold, it is defined to be in another state. The desired charge level is achieved by applying electrons to the substrate 1 by applying a suitable combination of voltages to the source, drain, substrate and control gate for a fixed period of time.
Moving from 1 to floating gate 19 programs the desired charge. The floating gate is confined within one memory cell, and the gate is electrically isolated from all other parts of the structure. On the other hand, the control gate 23 extends over many cells and functions as a common word line. As will be mentioned hereinafter, the channel-separated type provides the same function as two field-effect transistors connected in series, one of which has floating gate 19 as its control gate and the other has a control gate. The gate 23 is used as the control gate.

The primitive channel-separated Eprom or EEProm shown in FIG. 1 has a flash E by adding an erase gate (not shown).
It becomes an Eprom device. The erase gate is a separate electrode located beside the floating gate 27 and separated therefrom by a tunnel dielectric. When an appropriate voltage is applied to the source, drain, substrate, control gate, and erase gate, the amount of charge on the floating gate is reduced. Since one erase gate extends over many memory cells, they are erased at the same time, if not the entire array. In one prior art flash EEprom cell, a source or drain diffusion region provided below the floating gate is used as an erase electrode, while in other cells the erase electrode is the same as the layer as the control gate. Layers or separated conductive layers.

[Multi-State Storage] The channel separation type flash EEprom device is shown in FIG.
, Two transistors T1 and T2
Can be regarded as a synthetic transistor composed of a series of The transistor T1 is a floating gate transistor and has an effective channel length L1.
And has a variable threshold voltage V _T1 . Transistor T2 has a fixed (enhancement) threshold voltage V _T2 and an effective channel length L
2. Ep of synthetic transistor
The program characteristics of the rom are shown in the curve (a) of FIG. The programmed threshold voltage V _tx is plotted as a function of time t when program conditions are given. These program conditions are typically described as V _CG =
12V, V _D = 9V, a V _S = V _BB = 0V. When either V _CG or V _D is 0V, the program (not programmed, has not been cleared) not occur devices, V _T1 is + 1.5V, V _T2 has a + 1.0 V. After approximately 100 milliseconds of programming, the device reaches a threshold voltage V _tx ≧ + 6.0V. This indicates an off ("0") state. This is because, the composite device V _CG
This is because conduction does not occur at +5.0 V. Conventional devices use a so-called "intelligent programming" algorithm. This typically means
A programming pulse lasting 1 microsecond from 100 microseconds is provided, followed by a sensing (reading) operation. The pulse continues to be applied until it is detected that the device has turned off altogether, and then three extra programming pulses are provided to verify that the programmability is assured. In the prior art channel-separated flash EEprom device, erasing is performed with one pulse having a sufficient voltage V _ERASE and a sufficient period, and V _T1 is set to V _T2
(Curve (b) in FIG. 3) It is checked whether or not the voltage has been erased. The floating gate transistor continues to erase until it is erased to depletion mode operation (line (c) in FIG. 3), but the presence of series transistor T2 obscures this depletion threshold voltage. I have. Therefore, the state erased to the (“1”) state is represented by the threshold voltage V _tx = V _T2 = + 1.0 V. The memory storage “window” is ΔV = V
_tx (“0”) − V _tx (“1”) = 6.0−1.0 = 5.0V However, the true storage window should be represented by the full swing of V _tx of transistor T1. For example, if the transistor T1
Has been erased to a depletion threshold voltage V _T1 = −3.0 V, so that the true window is ΔV = 6.
It should be given at 0V-(-3.0) = 9.0V. None of the prior art flash EEprom devices utilize this true storage window. In fact, those of the prior art show that the operation of the device in (the area shown as the hatched area D in FIG. 3), here the area where V _T1 is lower than V _T2 Ignored.

The present invention first proposes a plan that makes use of the features of this full storage window. This allows for more than two binary states of storage by using a wider storage window, and consequently more than one bit per cell. For example, it is possible to store 4 instead of 2 in one cell, and this state has the following threshold voltage. State “3”: −V _T1 = −3.0 V, V _T2 = + 1.0 V (most conductive state) = 1,1. State "2": a _{-V T1 = -0.5 V, V T2} = + 1.0V ( intermediate conduction) = 1,0. State "1": the _{-V T1 = + 2.0V, V T2} = + 1.0V ( lower conduction) = 0. State "0": and _{-V T1 = + 4.5V, V T2} = + 1.0V ( non-conductive) = 0,0. To detect any of these four conditions, the control gate is raised to V _CG = + 5.0V. Then, the source / drain current I _DS is detected via the composite device. For all four threshold states, V _T2 = +
Since it is 1.0V, transistor T2 simply acts as a series resistor. FIG. 4 shows the conduction current I _DS corresponding to the four states of the composite transistor as a function of V _CG . The current sense amplifier can easily distinguish between these four conduction states. The number of possible states in practice is affected by the sensitivity of the noise of the sense amplifier and the loss of charge over the expected time course when the temperature rises. Eight identifiable conduction states are required for storage of three bits per cell,
Storing 4 bits in one cell requires 16 identifiable conduction states. For multi-state storage cells, ROM (read only memory) and DRAM
(Dynamic Random Access Memory) has been proposed. In ROM, different channel ion implantations can have one of several fixed conduction states by creating two or more permanent threshold voltages. Prior art multi-stage DRAM cells have been proposed, where each cell of the array is physically identical to the other cells. However, the charge stored in each cell capacitor is quantized, resulting in several different read signal levels. For storage of such prior art multi-stage DRAMs, see IEEE Journal of Solid-State Circuits, 1988.
M. on page 27 of the year. A paper by M. Horiguchi et al., “A large-scale semiconductor file memory using 16 levels of cell storage” (“An Experimental Large-Capa
citySemiconductor File Memory Using 16-Levels / Cell
Storage ”), a second example of a multi-stage DRAM is described at the IEE Custom Integrated Circuits Conference on P4.4.1 in May 1988 by T. Furuyama et al. Experiment on DRAM that Stores 2 Bits per Cell for Operation "
(“An Experimental 2-Bit / Cell Storage DRAM for Ma
crocell or Mem-ory-on-Logic Applications ”).

In order to make effective use of multi-stage storage in Eprom, it is necessary for the algorithm of the program of the device to allow programming in any of several conduction states. First, "3" state of (in this example +3.0 V) needs to be erased to a negative voltage V _T1 more than. The device is then programmed with a short program pulse (typically 1 to 10 microseconds in duration).
Command pulse). The program condition is that one pulse does not transfer effects that exceed the threshold of the device by more than half the threshold difference between the two states that follow it. In the device, the conduction current I _DS and i (i = 0, 1, 2, 3) of the reference power supply I _REF correspond to a desired conduction state (in order to correspond to four states, four reference levels are required). Is required) and the current is compared. The programming pulse is sustained (dashed line in FIG. 4) until the sensed current (solid line in FIG. 4) is slightly below the reference current corresponding to the four desired situations. To better illustrate this point, each programming pulse rises linearly to V _tx at 200 millivolts. And further assume that the device is initially erased by V _T1 = −3.2V. Then the required programming / sensing pulses are as follows: Relative state _{"3" (V T1 = -3.0V} ) number of pulses = (3.2-3.0) /. 2 = 1 For state "2" (V _T1 = -0.5 V) Number of pulses = (3.2-0.5) /. 2 = 14 For state “1”, (V _T1 = + 2.0 V) Number of pulses = (3.2 − (− 2.0)) /. 2 = 26 For state “0” (V _T1 = + 4.5 V) Number of pulses = (3.2 − (− 4.5)) /. 2 = 39 As a practical matter, V _tx is not linear with time. This is shown in curve (a) of FIG. as a result,
More pulses are required than indicated in state "1" or "0". If 2 microseconds is the width of the programming pulse, 0.1 microseconds
If de is it was time required for detection, the maximum time required to program any of the device 4 states is approximately 39 × 2 + 39 × 0.1 = 81.9 micro cell con
The de. This is less than the time required by prior art devices "intelligent programming algorithms". In fact, in the new programming algorithm only a carefully measured group of electrons is injected during the program. Yet another advantage of this approach is that sensing when reading is the same sensing as when programming.
And the same reference current source can be used for both programming and reading operations. This means that all memories in the array can be programmed and sensed with the same reference level. This provides good tracking even in very large arrays of memory. Larger memory systems typically have built-in error detection and correction procedures, which are designed to handle a small number of hardware defects, such as cells that respond badly to flash. Designed to withstand. For this reason, after a certain amount of the maximum number of program cycles have been performed, even when there is an indication that the memory cell is malfunctioning without the cell being programmed to the desired threshold. The algorithm of the programming and sensing cycle can be stopped automatically.

However, there are several concepts of multi-state storage associated with an array of EEprom transistors. An example of such a circuit is shown in FIG. In this circuit, one array of memory cells has a decoded word line and a decoded bit line, each connected to the control gate and drain of a row and column cell, respectively. Each bit line is usually 1.0 during read or program or erase time.
It is pre-charged to a voltage between V and 2.0V. Due to the four stages of accumulation, the four sense amplifiers each have their own reference level at I _REF 0, I _REF 1, I _REF 2, I _REF 3
Has a reference voltage for the decoded output of each bit line. During a read, the current through the flash EEprom transistor is compared (in parallel) with these four reference levels. This operation can also be performed during four successive reading periods (i.e., having one sense amplifier and having a different reference applied to each cycle). This is useful when it does not matter if additional time is required for this purpose.). The data output is supplied from four Di buffers (D0, D1, D2 and D3) via four detection amplifiers. During programming, four data inputs Ii (I0, I1, I2 and I3) are provided to a comparator circuit, which also supplies the outputs of the four sensor amplifiers for the accessed cell. If D
If i and Ii match then the cell is in the correct state and no programming is required. However, if all four Dis do not match all four Ii, the output of the comparator will activate the program control circuit. This circuit controls the bit line (VPBL) and word line (VPWL) program pulse generators. One short programming pulse is applied to both the selected word line and the selected bit line. This is followed by a second reading cycle to determine if Di and Ii match. This sequence is repeated until the multiplexed program and readout pulses match (or in the first step, no match is found, then
(Determined when the preset maximum number of pulses has been reached). As a result of such a multi-stage programming algorithm, each cell is programmed to four conduction states directly related to said reference conduction state I _REF , i. fact,
The same sense amplifier is used for the program and read pulse generator, and it is also used for the detection period (during normal reading). This allows good tracking in large memory arrays between the reference level (dashed line in FIG. 4) and the programmed conduction level (solid line in FIG. 4) and within a very wide operating temperature range. In addition,
Because carefully metered electrons are injected into and removed from the floating gate during programming or erasing, the device is subjected to a minimal amount of tolerable stress. In fact, four reference levels and four sense amplifiers are used to bring the cell into one of the four conducting states, but only three sense amplifiers and three reference levels are required for the four storage strips. Needed to detect one of the correct states. For example, in FIG. 4, I _REF (“2”) is in the conductive state “3”.
And "2", I _REF ("1") can be correctly distinguished between conducting states "2" and "1", and I _REF ("0") can be distinguished between conducting states "2" and "1". It is correctly discriminated between "1" and "0". In a practical configuration of the circuit of FIG. 6, the reference levels I _REF , i (i = 0,1,2) are used to detect the corresponding lower and higher cell conduction states during that period. They may be moved closer to their center points. Note that the same principles used in the circuit of FIG. 6 apply to two-stage storage or to more than three states per cell. Of course, a circuit other than that shown in FIG. 6 is also possible. For example, the present invention can be similarly used not for sensing the conduction level but for sensing the voltage level.

[Improvement of Charge Holding Power] In the above-described example, states “3” and “2” are the result of positive charges in the floating gate, whereas states “1” and “0” are This is due to negative charges (electrons) on the floating gate. In order to properly detect the correct conduction during the life of the device (which can be specified as 10 years at 125 ° C.), this charge must be transferred from the floating gate to the V _{T2 at} approximately 20 V.
It is necessary not to leak more than equivalent to a shift of 0 millivolt. This condition applies to the stored electrons in this example or in all prior art Epro.
m or flash EEprom. Due to the physical considerations of the device, the retention of holes trapped in the floating gate should be clearly better than the retention of trapped electrons. This is because the trapped holes are neutralized only when electrons are injected into the floating gate. Without the injection described above, it is almost impossible for a hole to overcome the electric field barrier at the silicon-silicon dioxide interface of about 5.0 electron volts (the electric field barrier of trapped electrons is 3.1V). Therefore, improving the retention of this device can be improved by using the area where the holes captured in conduction are relevant. For example, in the state “1”, V _T1
Is + 2.0V, which is associated with the trapped electrons, and in a virgin device V _T1 is 1.5V. However, in a virgin device, its V _T1 is _raised to a higher threshold voltage, for example, V _T1 = + 3.0 V ( channel region
(By increasing the p-type doping concentration ), the same state "1" results in V _T1 = + 2.0V, which is caused by trapped holes. This value of V _T1 will provide better retention. Of course, it is also possible to the reference level most or all of the state set a reference voltage to have a value of lower V _T1 than V _T1 of the virgin device.

[Erase of Information for Improved Endurance]
The endurance of flash EEprom devices is their ability to resist a given number of write and erase cycles. A physical phenomenon that limits the durability of prior art flash EEprom devices is that electrons are trapped in the active dielectric film of the device. The dielectric element used during programming captures some of the injected electrons during thermionic channel injection. During the erase, the tunnel erase dielectric also captures some of the tunnel electrons. Since the captured electrons will resist the applied electric field in the subsequent erase cycle,
This causes a decrease in threshold voltage and a shift in V _tx . This can be observed as a progressive closing of the voltage window between the "0" and "1" states (see FIG. 5).
Beyond approximately 1 × 10 ⁴ program erase cycles, the degree of closing of the window is such that the detection circuit may malfunction. If this cycle is continued, the device will experience a critical collapse phenomenon due to dielectric damage and decay. This typically occurs between 1 × 10 ⁶ and 1 × 10 ⁷ cycles. And it is known as breakdown due to impurities in this device. In the prior art memory device, the practical limit of how to close the window is approximately 1 × 10 ⁴ cycles. At a given erase voltage V _ERASE , the time required to fully erase the device can reach from the original 100 milliseconds (ie, in a virgin device) to 10 seconds in a device that has been performed 1 × 10 ⁴ times. . The quality degradation in such prior art flash EEprom devices is 1
In order to allow sufficient erasure after use of × 10 ⁴ times or more, an extremely long erasing pulse time had to be specified. However, this was excessive erasure in the virgin device, resulting in unnecessary excessive distortion. A second problem with prior art devices was that the tunnel dielectric was exposed to unnecessarily high peak stress during the erase pulse. This is because the state “0” (V _T1
= + 4.5V or higher). This device has a large negative charge Q
Have. When V _ERASE is applied, the tunnel dielectric, like V _ERASE , is momentarily exposed to a sharp electric field due to the influence of Q. This peak electric field gradually decreases when the charge Q changes to 0 in the tunnel erasing process. Nevertheless, permanent and cumulative damage is added in the course of this erasure.
This results in premature device collapse. To overcome the two problems of overstress and window closing, a new erasure algorithm has been disclosed. It is applicable to any of the preceding flash EEproms. Without such a new erasure algorithm, implementing a multi-state device would result from curve (b) of FIG. 5 where the conduction state would be from 1 × 10 ⁴ if V _T1 is more negative than V _T2. It will be extinguished in 1 × 10 ⁵ write / erase cycles.

FIG. 7 shows the main steps of the new erasure algorithm. Assume that a block array of m × n memory cells has been completely erased by flash erase to state “3”, which is the highest conductive state and the lowest _VT1 state. Certain parameters are set in connection with the erasure algorithm. They are listed in FIG. 7, where V ₁ is the erase voltage of the first erase pulse. V ₁ is probably less than 5 volts from the erase voltage required to erase the virgin to state “3” with an erase pulse of 1 second. t is approximately 1/1 of the time required to completely erase the virgin device to state "3".
Selected as 0. Typically, V ₁ is between from 10V to 20V, whereas t is between 10 and 100 ms. The algorithm assumes a small number X of bad bits that the system can withstand (this system level is determined in the process of error detection and correction as an example. Without any error detection and correction, In that case, X = 0). These are bits that are shorted or very leaky tunnel dielectrics that are not erased by applying a sufficiently long erase pulse. To prevent over-erasure, the total number of erase pulses can be limited to a preset n _max in the erase cycle of all blocks. ΔV is the voltage by which the subsequent erase pulse is boosted. Typically, ΔV is from 0.25V to 1.
Between 0V. As an example, if V ₁ = 15.0 V and ΔV = 1.0 V, then the seventh erase pulse has a magnitude of V _ERASE = 21.0 V and a duration of t
It is. One cell is considered completely erased. That is, when the conductance of the reading becomes greater than I _"3" . The number of complete erase cycles S experienced by each block is very important information at the system level. If S is known for each block, S is 1 × 10
^If a program erase cycle of ⁶ (or another set number) is reached, those elements can be automatically replaced with new auxiliary blocks. S is initially set to 0, and is incremented sequentially for each complete block erase multiple pulse cycles. As the value of S, for example, 20 bits (2 ²⁰ corresponds to approximately 1 × 10 ⁶ ) can be prepared and accumulated in each block, for each time. In that way, each block can maintain its own durable record. Alternatively, the S can be stored in a system remote from the chip.

The sequence of the complete erase cycle of the new algorithm is as follows (see FIG. 7). 1. Read S. This value can be stored in a register file. (This step can be omitted if S is not expected to reach that limit during the operating life of the device). 1a. First erase pulse V _ERASE = V ₁ + nΔV, n =
Apply 0, pulse duration = t. Although this pulse (and the next few consecutive pulses) is sufficient to erase all memory cells, it will reduce the charge Q of the programmed cell, which is a relatively low erase field. It is stress. That is, it is 1
This is equivalent to two "condition making" pulses. 1b. Read the sparse patterns in the array. A diagonal reading pattern would read, for example, m + n cells (rather than a complete reading by m × n), and retrieve at least one cell from each row, and one cell from each column It will be. The number N and X of the cells that have not been completely erased by the state “3” are compared. 1c. If N is x (not fully erased array)
If so, the second erase pulse is larger than the first pulse by ΔV and a second erase pulse having the same duration t is applied. Read diagonal cells, count N.
In this erasing cycle, the erasing pulse of pulse / read / addition is continued until N ≦ X or the number n of erasing pulses exceeds _nmax . The first one of these two conditions leads to the final erase pulse. 2a. A final erase pulse is applied to confirm that the array has been completely and fully erased. The magnitude of V _ERASE is larger than the previous pulse by a fraction of ΔV. The duration can be between 1t and 5t. 2b. 100% of the array is read. The number N of cells that have not been completely erased is counted. If N is less than or equal to X, pulsing for erasure is completed at this point. 2c. If N is greater than X, then the address of the presence of the unerased bit N is generated. It is to exchange spare good bits at this system level. If N is significantly greater than X (if N equals 5% of all cells), flag in such a case and let the user reach the limit of their patience and at the end of life Indicates that it has become. 2d. The pulse for erasing is terminated. 3a. One S is added. The new S is then saved for future reference. This step is optional. The new S is written into the newly erased block or stored in a register file separate from the chip. 3b. The erase cycle is terminated. A complete cycle is 10 to 20 erase pulses and is expected to be erased in about 1 second.

The new algorithm has the following features. (A) No cells in the array are subject to peak electric field stress. By time V _ERASE , the relatively high voltage and any charge Q has already been removed from the floating gate by a previous low voltage erase. (B) The total erase time is much shorter than in the prior art using fixed V _ERASE pulses. In a virgin device, the required erasing time is a minimum pulse. Even in a device that has survived 1 × 10 ⁴ cycles or more, a voltage increase several times ΔV is not required to overcome the dielectric trapped charge. And the charge trapped in the dielectric only increases its total erase time by a few hundred milliseconds. (C) The narrowing of the window on the erasing side (see curve (b) in FIG. 5) can be avoided indefinitely (until the device fails due to sudden destruction). This is because V _ERASE is simply increased until the device is in the correct erased state “3”. The new erasure algorithm can save the entire storage window.

FIG. 8 shows a flash EEpro according to the present invention.
4 shows the four conduction states of the m device as a function of the number of program erase times. All four states, always is possible to fix the reference conduction states by the program or erase is complete, in any state, not that at least 1 × 10 ⁶ cycles window until is narrowed. In a flash EEprom memory chip, a voltage increasing device for generating nΔV from a voltage V ₁ and a voltage increment ΔV required on the chip (or on another control chip) to effectively execute a new erase program; It is possible to provide a coefficient circuit for counting N and comparing it with a stored value X, a register for storing an address of a position of a defective bit, and a control and sequence circuit including an instruction for executing the aforementioned erase sequence. . What has been described in detail as embodiments of the present invention are preferred embodiments, and those skilled in the art will recognize many variations in this regard. Accordingly, the present invention is entitled to protection within the full scope of the appended claims.

[Brief description of the drawings]

FIG. 1 Channel-separated type Eprom or EEpro
m is a sectional view of an embodiment.

FIG. 2 is a schematic diagram showing a specific transistor representation for forming a channel-separated Eprom transistor.

FIG. 3 is a diagram showing characteristics of programming and erasing of a flash EEprom device of a channel separation type.

FIG. 4 shows a channel-separated flash E according to the invention.
It is a figure showing four conduction states of an Eprom device.

FIG. 5 is a diagram showing a life characteristic of a program erase cycle of a conventional flash EEprom device.

FIG. 6 is a diagram showing a circuit diagram and a program write voltage pulse required in the multi-stage storage device.

FIG. 7 is a schematic diagram showing a basic state in a new algorithm that can be erased with minimum stress.

FIG. 8 is a diagram showing a program erase cycle life characteristic of a channel separation type flash EEprom device using a multi-stage program and an information algorithm for reducing stress at the time of erase.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Substrate 13 ... Source region 15 ... Drain region 17 ... Channel region 19 ... Floating gate 21 ... Gate oxide 23 ... Control gate

Claims (20)

(57) [Claims] 1. An array of electrically changeable memory cells that can change state and are addressable for reading, wherein each memory cell includes a field effect transistor having a floating gate and a threshold voltage. For a memory array having a voltage level, the level having a given level when there is no net charge on the floating gate, but being variable due to the net charge held by the floating gate, In a method of changing the state of an addressed cell of an array: establishing more than two effective threshold voltage levels corresponding to more than two detectable individual cell states, wherein: At least two of the plurality of effective threshold levels are the net positive threshold of the floating gate. The floating gate of the addressed cell until the effective threshold voltage of the addressed cell is substantially equal to one of the plurality of effective threshold voltage levels. Setting the detectable state of the addressed cell by varying the amount of charge of the cell. 2. The method of claim 1, wherein said set of detectable states comprises: applying a negative charge to a floating gate of the addressed cell to increase a voltage level of an effective threshold of the addressed cell. A method comprising the step of changing. 3. The method of claim 1, further comprising the step of presetting an effective threshold voltage of the addressed cell to a preset level before setting the detectable state of the addressed cell. Including methods. 4. A method according to claim 1, wherein, before setting the detectable states of the addressed cells, including the addressed cell by changing the charge amount of floating gate of a group of cells A method comprising presetting an effective threshold voltage level of a group of cells in an array to a preset level. 5. The method of claim 4, wherein presetting the group of cells presets the group of cells to a preset effective threshold voltage level that is outside the plurality of effective threshold voltage levels. A method that includes a step. 6. The method of claim 4, wherein the presetting of the group of cells comprises removing the negative charge on the floating gate to thereby effect the plurality of effective threshold levels corresponding to a plurality of cell states. Establishing a preset effective threshold voltage level of the group of cells at a level lower than the lowest one of the plurality of cells and a set of detectable states of the addressed cells comprises a floating of the addressed cells. A method comprising applying a negative charge to a gate. 7. The method of claim 4, further comprising the step of reading the set state of the addressed cell after setting the detectable state of the addressed cell. 8. The method of claim 7, wherein the reading of the set state of the addressed cell causes a current to flow through the addressed cell, and simultaneously the level of the current and two or more references. Comparing to a current level. 9. The method of claim 1, wherein after setting the detectable state of the addressed cell, flowing a current through the addressed cell and simultaneously increasing the level of the current by more than one. A method additionally comprising reading the state in which the addressed cell is set by comparing to a reference current level. 10. The method of claim 9, wherein the level of the current is one more than the plurality of effective threshold levels.
A plurality of reference current levels that are compared simultaneously. 11. The method according to claim 1, wherein the step of establishing a plurality of effective threshold voltage levels comprises the step of generating a threshold from a net positive charge on the floating gate. A method comprising establishing a majority of the value levels. 12. The method according to claim 1, wherein establishing a plurality of effective threshold voltage levels comprises establishing at least four such threshold voltage levels. Method. 13. The method of claim 1, wherein said given threshold level of said individual cells is set to at least 3 volts. 14. The method according to any one of claims 3 to 5, further comprising the step of adding a total count of the number of times the group of cells is preset. 15. The method of claim 3, further comprising the step of replacing the group of cells with an auxiliary block of cells in the array when the group of cells becomes unavailable. 16. The method of claim 1 or 3, further comprising the step of replacing the addressed cell with a secondary good cell in the array in response to a corrupted cell. 17. An array of a plurality of electrically erasable and programmable read-only memory cells, each cell formed on a semiconductor substrate, said substrate comprising a source and a drain separated by a channel region, and a channel region. A floating gate located on at least a portion of and isolated from the floating gate, and a control gate extending above and floating from the floating gate, wherein the transistor has a natural threshold voltage and a controllable voltage on the floating gate. Having an effective threshold voltage derived from a combination with a voltage corresponding to the charge level, wherein the natural threshold voltage corresponds to the floating gate having a charge level equal to zero when the floating gate has a charge level equal to zero. Erases the memory state of the cells in the array, and In a programming and reading system: means operatively connected to the array to address a selected one or group of memory cells; and an effective threshold voltage of the addressed cell or group of cells. Erasing means operatively connected to said array, and programming means operatively connected to said array, for driving to the ground level by changing the charge on the floating gate of each addressed cell. The effective threshold voltage to one of more than two effective threshold voltage levels corresponding to more than two individual detectable states to alter the charge on the floating gate of the addressed cell Changing until the voltages are substantially equal, wherein at least two of the plurality of effective threshold voltage levels are And program means derived from a controllable level of charge on the floating gate is,
And reading means operatively connected to the array to determine the amount of current flowing in the addressed cell, whereby the state of the addressed cell is determined by the measured current level flowing therethrough. System including a reading means. 18. The memory system according to claim 17, wherein said programming means is configured to address cells until its effective threshold voltage is substantially equal to one of at least four effective threshold voltage levels. Means for altering the charge on the floating gate of the array, whereby individual cells of the array are programmable to four or more states. 19. The memory system according to claim 17, wherein said natural threshold voltage level is at least 3 volts. 20. The memory system of claim 17, wherein the means responsive to the erasing means drives an effective threshold voltage of the addressed cell or group of cells to a ground level, and A system additionally comprising means for accumulating a running count stored in said array of the number of times a group of cells has been erased and increasing by one.