JPH09120690A - Flash eeprom memory system and its usage method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lengthen the lifetime of a memory. SOLUTION: This device has a field-effect transistor with a floating gate 19, and a memory array, in which the level of threshold voltage is set at a certain given level when there is no charge in the floating gate 19 and is varied by charges held by the floating gate 19, is used as the device. When the state of an addressed cell is changed at that time, effective threshold voltage corresponding to the state of detectable each cell exceeding 2 and exceeding 2 results from the quantity of the positive charges of the floating gate 19, and the quantity of charges on the floating gate 19 of the addressed cell is altered until the threshold voltage of the addressed cell is equalized approximately to one of a plurality of the above-mentioned threshold levels. Accordingly, the state, in which the addressed cell can be detected, is set.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD OF THE INVENTION

This invention relates generally to electrically programmable read only memory (Eprom) semiconductors and electrically erasable programmable programmable read only memories (EEprom). Related to the technology of using.

[0002]

[Prior art]

BACKGROUND OF THE INVENTION An electrically programmable read-only memory (Eprom) is a field effect transistor structure that has a floating conduction gate (not connected) that is insulated from a channel in a semiconductor substrate region and provided between a source and a drain region. ) Is used. The control gate is provided above the floating gate and is insulated from it. The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, to allow conduction between its source and drain regions, the voltage that must be applied to its control gate before the transistor is turned on, that is, its voltage is the threshold voltage, its minimum voltage ( Threshold voltage). A transistor is one of two states by accelerating electrons to a floating gate through a thin dielectric gate in the channel region of its substrate.
Can be programmed.

The state of a memory cell transistor can be read by applying an operating voltage to the source and drain of the transistor and the control gate, and then detecting the current flowing between the source and drain when the control gate voltage is selected. Can tell if the device is programmed on or off. To address a particular one cell in a two-dimensional array of Eprom cells for reading, the source and drain voltages are applied across the source and drain lines of the column containing the cell to which the cell is to be addressed. , And by applying a control voltage to the control gate of the matrix containing the cell to be addressed.

An example of such a memory cell is triple polysilicon, a channel-separated electrically erasable and programmable read-only memory (Eprom). This is referred to as a spirit channel device because the floating and control gates extend over adjacent portions of the channel. This allows the transistor structure to act as two transistors in series, one with a variable threshold channel responsive to the charge level on the floating gate, the other unaffected by the charge on the floating gate, Rather, it works in response to a voltage applied to its control gate, similar to a normal field effect transistor.

Such a memory cell is called triple polysilicon. This is because it has triple conductive layers of polysilicon material. In addition to the floating and control gates, an erase gate is also included. The erase gate passes near the floating gate surface of each memory cell transistor,
It is insulated from them by a thin tunnel dielectric (which has the effect of tunneling). Charge is removed from the floating gate of the cell when the appropriate voltage is applied to all the transistors at the erase gate. A cell of such an Eprom is called a flash Eprom array when the entire array of cells or a particular group of cells are simultaneously erased (ie by flash).

It has become known that EEprom has a finite useful life. There is a finite number of times that such a device can be programmed and erased before performance is degraded. Its characteristics depend on the particular structure, but its programmability diminishes after more than 10,000 cycles of use. After such a device has been used for more than 100,000 cycles, it can no longer be programmed or properly erased. It is believed that this is a result of trapped charges in the dielectric that are transferred to or removed from the floating gate for programming or erasing.

[0007]

It is an object of the present invention to provide an EEprom array with increased storage capacity and lifetime. Further, it is to provide a technique for increasing the number of programming and erasing times that one EEprom can withstand. Still another object of the present invention is to provide
It is to provide a technique for increasing the amount of information stored in an Eprom or array of EEproms of a given size. Still another object of the present invention is to provide an EEprom semiconductor chip that can be used as a solid-state memory that can replace a magnetic disk storage device.

[0008]

Various objects can be achieved from various aspects of the present invention. Here, in brief and general terms, each Eprom or EEpr
om memory cells One or more data can be stored by dividing the programmed charge into three or more ranges. Each cell can thereby be programmed into one of three ranges. If four ranges are used,
2-bit data is stored in one cell. If 4
If one range is specified, then 3 bits are stored. In this way, it is sequentially performed. An information program and a sensing technique that allow a realistic configuration capable of such multi-stage storage are provided.

In addition, an algorithm for erasing information is provided that effectively removes the electrical stress applied to the erasing tunnel dielectric, resulting in higher endurance for the program and erase cycles. Can be given, and the life of the memory can be increased.

The method of using the flash EEprom memory system according to the present invention is as follows: (1) An electrically changeable memory cell whose state can be changed and which is addressable for reading,
Each memory cell includes a field effect transistor having a floating gate, which has a threshold voltage level, which level has a given level when no charge is present on the floating gate, but is held by said floating gate. In a method of changing the state of the addressed cells of the array for a memory array that is variable by the charge that is charged: more than 2 effective, corresponding to more than 2 detectable individual cell states. Establishing a threshold voltage, wherein the at least two effective threshold levels result from the amount of positive charge on the floating gate, and the threshold voltage of the addressed cell. Of the addressed cells until is approximately equal to one of the threshold levels. It is configured to include a step of setting a detectable state of the addressed cell by changing the amount of charge on the over Te Ing gate. (2) In the method of (1) above, the set of detectable states is the effective threshold voltage of the addressed cell by applying a negative charge to the floating gate of the addressed cell. It is configured to include a step of changing the level. (3) In the method described in (1) above, an additional step of presetting an effective threshold voltage of the addressed cell is added before the detectable state of the addressed cell is set. It is configured to include. (4) The method of (1) above, wherein the array of addressed cells is included by changing the charge of the floating gate of the group of cells prior to setting the detectable state of the addressed cells. Comprising the step of presetting the effective threshold voltage of the group of cells to be preset to a preset level. (5) In the method described in (4) above, the presetting of the group of cells includes a step of presetting to a preset effective threshold voltage level outside a range of the plurality of effective threshold voltage levels. Has been done. (6) In the method described in (4) above, the presetting of the group of cells is carried out by removing a negative charge of the floating gate to a certain level lower than the lowest one of the plurality of effective threshold levels. Establishing a current effective threshold voltage level for the group of cells, and setting a detectable state of the addressed cell adds a negative charge to the floating gate of the addressed cell. It is configured to include a step of performing. (7) The method according to (4) above, further comprising a step of reading the set state of the addressed cell after setting the detectable state of the addressed cell. There is. (8) In the method described in (7) above, the reading of the state in which the addressed cell is set causes a current to flow through the addressed cell, and at the same time refers to the level of the current and / or a reference level higher than that. It is configured to compare with a current level. (9) In the method described in (1) above, after setting the detectable state of the addressed cell, a current is passed through the addressed cell and the current is simultaneously compared with a higher reference current level. It is configured to additionally include the steps to be performed. (10) In the method described in (9) above, including a step of comparing the current with a plurality of reference voltage levels, which are one less than the plurality of effective threshold levels. It is composed of. (11) Any one of the methods described in (1) to (11) above
In one method, establishing a plurality of effective threshold voltage levels comprises establishing a majority of the threshold levels resulting from positive charge on the floating gate. (12) In the method of any of (1)-(11) above, establishing a plurality of effective threshold voltage levels includes establishing at least four such threshold voltage levels. It is configured. (13) In the method according to any one of (1) to (11), the given threshold level of the individual cells is set to at least 3 volts. (14) The method according to any one of (3) to (5) above, which is configured to include a step of adding the total number of times the group of cells is preset. (15) The method according to any one of (3) to (5) above, further comprising a block that replaces a block of auxiliary cells in the array when the group of cells becomes unavailable. ing. (16) In the method according to any one of (1) and (3) above, including a step of replacing the addressed cell with an auxiliary good cell in the array in response to the destruction. It is composed of. (17) An electrically changeable memory cell whose state can be changed and which is addressable for reading, each memory cell including a field effect transistor having a floating gate and having a threshold voltage level. For a memory array whose level has a given level when there is no charge on the floating gate, but which is variable by the charge held by the charge on the floating gate, the address of the array is A method of changing the state of a cell, the method comprising: establishing an effective threshold voltage greater than two corresponding to a plurality of individual detectable states greater than two, and one of the plurality of effective threshold voltage levels. To the effective threshold voltage of the addressed cell until substantially equal to Setting a detectable cell of the addressed cell to one of the plurality of states by changing the amount of charge on the floating gate of the cell, and electrically interrogating the addressed cell. And reading the set state of the addressed cell by comparing the number of reference levels above 2 and the level of the electrical parameter of the addressed cell. (18) In the method of (17) above, the step of establishing a plurality of effective threshold voltage levels comprises the step of establishing at least four such threshold voltage levels. (19) In the method described in (18), the threshold level applied to each cell is established to be at least 3 volts. (20) In the method described in (17) above, the step of reading a state in which an addressed cell is set compares the number of reference levels, which is one less than the plurality of states, with the electrical parameter level at the same time. It is composed of steps.

The flash EEpro according to the present invention
An m memory system is (21) an array of a plurality of electrically erasable and programmable read-only memory cells, each cell being formed on a semiconductor substrate with a source and a drain separated by a channel and a floating gate. Insulated from the channel region and at least partially formed thereon, and a control gate insulated from and extending above the floating gate, the transistor having a natural threshold voltage and a controllable charge on the floating gate. Of the array having an effective threshold level resulting from a combination with a voltage corresponding to the level of, the natural threshold voltage corresponding to the floating gate having a charge equal to zero. Erase, program, and read memory states inside And a means operatively connected to the array for addressing a selected one or a group of memory cells and an effective threshold voltage of the addressed cell or group of cells, respectively. An erase means operatively connected to the array and a program means operatively connected to the array for driving the ground level by changing the charge of the addressed floating gate are addressed as one. To change the charge on the floating gate of the cell, the threshold voltage level being changed to one of a plurality of effective threshold voltage levels in excess of two until the effective threshold voltage level is substantially equal. The level corresponds to more than two detectable levels, wherein at least two of the plurality of effective threshold voltage levels are positive. Programmable means from a controllable level on the floating gate, and read means operatively connected to the array for determining the amount of current flowing through the addressed cell, the cell addressed therein. The state of s is determined by the reading means determined by the measured current level flowing therethrough. (22) In the memory system according to (21), the programming means is on the floating gate of the addressed cell until its effective threshold voltage is substantially equal to one of at least four threshold voltage levels. A means for altering the charge by which individual cells of the array are programmable to four or more states. (23) In the memory system according to (21), the natural threshold voltage level is at least 3 volts. (24) In the memory system according to (21), the responsive means of the erasing means drives to a base level of an effective threshold voltage of the addressed cell or group of cells, and The number of times the group has been erased is stored as a running count in the array and incremented by one. (25) In an array of a plurality of electrically erasable and programmable read-only memory cells, the cells are formed on a semiconductor substrate, a source and a drain are separated by a channel region, and at least a part of the floating gate is a channel region. Formed above and insulated from it, and one control gate formed above and insulated from the floating gate, the transistor having a natural threshold voltage and controllable charge level on the floating gate. At an effective threshold level resulting from a combination with a voltage corresponding to, the natural threshold voltage corresponding to the floating gate having a charge equal to zero. Erase memory, program, and read A system for issuing: a means operably connected to the array for addressing a selected one or a group of memory cells, an erase means operably connected to the array, The effective threshold voltage of an addressed cell or group of cells by changing the charge on the floating gates of the individually addressed cells to a ground level of the effective threshold voltage of the addressed cell or group of cells. Erasing means operatively connected to the array for driving the array and programming means operatively connected to the array to modify the charge on the floating gate of one addressed cell, Changing to one of a plurality of effective threshold voltage levels above 2 until said effective threshold voltage level is substantially equal, The threshold levels determine the amount of current flowing through the addressed cells, programming means corresponding to more than two detectable levels, a plurality of reference sources providing two or more different reference current levels. Means for operatively connecting to the array for reading the state of the addressed cell by instantaneously comparing the amount of current flowing through the addressed cell with the reference current level, or 2 It is configured to include means having the above sense amplifier. (26) In the memory system according to (25), at least two of the plurality of effective threshold voltage levels in the program means are derived from positive charges on the floating gate. (27) In the memory system described in (25), the majority of the plurality of effective threshold voltage levels in the program means are derived from a net positive charge on the floating gate. (28) In the memory system described in (25), the program means substantially charges the floating gate of the addressed cell with an effective threshold voltage of one of at least four effective threshold voltage levels. It includes means for changing to equality, where individual cells of the array are programmable to four or more states. (29) In the memory system according to (28), the plurality of reference sources provide three or more different current levels.

A flash EEprom memory system and method of using the same according to the present invention includes: (30) An array of electrically modifiable memory cells is divided into blocks of cells which address individual cells within said block. Means for reading and modifying its contents, said memory cell having field effect transistors each having a floating gate, having a threshold voltage level, said level being provided when there is no net charge on said floating gate. In a method of operating the array for an array of memory cells at a given level, the level being variable by the net charge held on the floating gate: a threshold voltage level greater than 2. Is the step of establishing multiple Corresponding to a plurality of states and setting the effective threshold level of at least one cell in the block to one of a plurality of levels, the charge of the at least one floating gate being addressed. The amount of
Changing the effective threshold voltage of the at least one addressed cell until one of the plurality of effective threshold voltages is reached, whereby the effective threshold voltage of the at least one addressed cell is changed. The state is set to one of the plurality of states, and counting until the cells in each one of the block of cells is equal to the total number of times set to one of the plurality of states Is stored. (31) In the method described in (30) above, the step of accumulating the counts of the individual blocks is a step of accumulating the counts in the individual blocks. (32) The method of (30) above, further comprising the step of providing at least one auxiliary memory block, and a set number with one said count of individual blocks exceeding the set number. In response to exceeding each of the blocks, substituting the auxiliary block for each individual one of the blocks. (33) In the method according to (30) above, providing at least a plurality of auxiliary memory cells, and at least some auxiliary cells are addressed in response to at least some addressed memory cells being defective. It comprises a step of substituting at least one of the cells. (34) A method according to any of (30)-(33) above, wherein the step of establishing a plurality of effective threshold voltages comprises the step of establishing at least 4 such thresholds. Has been done. (35) In a system in which electrically modifiable memory cells are separated into a plurality of distinct blocks of cells and having means for accessing individual cells in said block to read and modify their states, Each cell includes a field effect transistor having a floating gate, each cell having a threshold voltage level, the level being variable according to the net charge held by the floating gate, A method of operating a memory system consists of the following steps: (a) A threshold voltage level of memory cells above 2, which level corresponds to a state of individually detectable memory cells above 2. And (b) establishing one specified memory cell threshold voltage level; Providing an auxiliary cell in place of any defective cell within the memory cell, the amount of charge on the floating gate of the memory cell in at least one of the blocks of cells being determined by the effective base threshold. An altering step of presetting its effective threshold voltage by instantaneously altering in the direction of the level and the amount of charge on at least one floating gate of said memory cell in at least one of the blocks of cells. To
This moves at least one memory cell into a plurality of detectable states to move the effective threshold voltage in the direction of a plurality of effective threshold voltage levels.
And changing the address of any cell in at least one of the blocks of cells without changing the level to a desired effective threshold voltage level, and Here, the setting step includes substituting any one of the cells addressed as described above with at least one of the auxiliary cells. (36) In the method according to (35), the method further includes the step of separately storing a total number of preset numbers of blocks of individual cells. (37) In the method according to (35) above, the presetting step includes at least one of the blocks of the cell.
Continuing to change the amount of charge on the floating gates of the memory flanges in one of the two until the effective threshold level other than the Nth cell in at least one block reaches the effective base level, where: The step of generating an address comprises generating the Nth address of the cell. (38) In any one of (35) to (37) above, establishing the plurality of effective threshold voltage levels includes establishing at least four such threshold voltages. It is composed of. (39) An array of electrically modifiable memory cells, the array being divided into blocks of cells, the array having means for addressing individual cells within the block to read and change its state. The cell separately comprises a field effect transistor having a floating gate, having a threshold voltage level, said level corresponding to a level at which there is no net charge held on said floating gate, but the net of said floating gate. The steps of operating the array, which are variable by charge, include the following steps: Establishing more than two effective threshold voltage levels corresponding to more than two detectable states of individual cells. The step of setting an effective threshold voltage level in each of the plurality of cells, The amount of charge on each of the plurality of floating gates addressed to one cell of the block to one of the levels of the effective threshold voltage of the plurality of effective threshold voltage levels. Changing and setting until substantially equal to one, wherein the states of the plurality of addressed cells are set to one of the plurality of states; Appointing at least one block other than the block as an auxiliary block,
And replacing the sub-block of cells with the one block, the plurality of cells in the sub-block of cells are configured to set their effective threshold voltage level to one of the plurality of levels. The replacement step is made addressable. (40) The method of (39) above, further comprising the step of monitoring a block of individual cells and detecting that one of the blocks of cells has reached a patience limit. Correspondingly, it comprises the step of initiating the step of replacing said auxiliary cell. (41) In an electrically modifiable memory cell array, the cells are divided into distinct blocks of cells, and the cells access individual cells within the block to read and change their states. Have the means of
The memory cell having a field effect transistor having a separate floating gate, the cell having a threshold voltage, the level being a level provided when there is no net charge on the floating gate; The method of operating the includes the following steps: 2
Establishing a plurality of effective threshold voltage levels greater than, said levels corresponding to a plurality of detectable states of more than two individual cells, and a plurality of memories in one of said blocks. Changing the effective threshold level of each of the cells to one of a plurality of effective threshold voltage levels, changing the amount of charge on the floating gate of each of the cells until the effective threshold voltage is equal. And thereby setting the states of the plurality of cells individually to one of the plurality of states, and reading the plurality of states of the memory cell to aid in error correction planning. It is configured to include. (42) With an array of electrically modifiable memory cells divided into blocks of cells, each memory cell having means for reading or addressing to modify its state, said memory cells being individually A field effect transistor having a floating gate, having a threshold voltage level provided when there is no net charge on the floating gate, the threshold voltage being determined by the net charge held by the floating gate. In a method of operating said array for an array to be modified: more than two at multiple execution threshold voltage levels and more than two detectable programmable over individual cells. Establishing the one corresponding to the detectable level, and Also, the execution threshold level of one cell is substantially equal to the amount of charge on the floating gate of the addressed cell, and the execution threshold voltage of the addressed cell is substantially equal to one of the plurality of execution threshold voltages. Changing from a start level to one of a plurality of threshold voltages, the state of the addressed cell being set to one of the plurality of programmed states. In the step of setting the execution threshold voltage of the addressed cell, the predetermined execution voltage of the addressed cell is sufficient to move from the starting level to one of the plurality of threshold voltage levels. Applying a constant voltage to the addressed cell for a period of time, and then changing the electrical parameters of the addressed cell to the addressed cell. Reading to determine whether the execution threshold of the cell has reached one of a plurality of threshold voltage levels, and a plurality of execution threshold voltages of the addressed cell. The step of repeating voltage application and reading is detected until it is detected that the one of the threshold voltages is set. (43) In the method described in (42) above, the voltage applying step may be performed by setting the applied voltage and the predetermined time such that the execution threshold voltage of the addressed cell is equal to the plurality of effective voltages. It includes the step of causing a change of less than half between two adjacent ones in the threshold voltage. (44) In the method described in (42) above, the step of reading electrically queries the addressed cell and at the same time refers to the resulting level of the electrical parameter of the addressed cell by two or more. It consists of steps to compare with levels simultaneously. (45) In the method described in (42) above,
At least one addressed in one of said blocks
Resetting the effective threshold voltage of cells in said at least one block to a preset level, which is the following step, prior to setting one effective threshold level: to cells in said at least one block. , Applying a given voltage to the cells in the at least one block in the direction of the preset level for a predetermined time sufficient to move to the effective threshold voltage, after which the at least one Reading the electrical parameter of the cells in the block to determine if the effective threshold voltage of the individual cells in the at least one block has reached the preset level; and Applying a voltage to a cell in at least one block to read its state, said at least Repeating until the running threshold voltage of cells within a block has reached the preset level. (46) In the method of (45) above, the preset level is configured to be substantially equal to one of the plurality of preset levels corresponding to one of the detectable programmed states of the individual cells. There is. (47) In the method described in (45), the threshold voltage is applied to the cells in the at least one block when the applied voltage is applied and the voltage applying and reading steps are repeated. It is configured to continue while the voltage is rising. (48) In the method described in (45), the step of reading the electrical parameter of the cell in the at least one block electrically queries the cell in the at least one block, It is configured to simultaneously compare the obtained results of the individual electrical parameters of the cells in the two or more reference levels simultaneously. (49) In the method according to any one of (42) to (48), at least two of the plurality of effective threshold levels are due to a net positive charge on the floating gates of the individual cells. Is configured to be. (50) In any one of the methods (42) to (48), the given threshold level of the individual cells is at least 3 volts. (51) In the method according to any one of (42) to (48), repeating the voltage application and the reading while the effective threshold voltage level of the at least one addressed cell is set. , A preset maximum number of repetitions of the voltage application and reading steps of the setting that does not set the effective threshold voltage level of the addressed set to one of the plurality of threshold voltage levels. It is finished after getting up in the meantime. (52) In the method according to any of (42) to (48), the voltage application and the reading are repeated at least during the resetting of the effective threshold voltage level of cells in the at least one block. It is terminated after a preset maximum number of voltage application and read iterations has occurred during a reset period without resetting the effective threshold voltage levels of some of the individual cells in a block. (53) A method according to any one of (42) to (48) above, wherein in response to at least one addressed cell becoming defective, substituting a good auxiliary cell in the array. Is further included. (54) In the method according to any one of (42) to (48), the block of at least one auxiliary cell in the array is replaced in response to a defect of at least one addressed cell. It further comprises a step of performing. (55) In the method according to any one of (42) to (48), the method further includes accumulating the total number of times at least one block of the cell has been set.

An embodiment of a fault management error correction code for a flash EEprom memory system according to the present invention is: (A1) The integrated circuit memory system includes non-volatile floating gate memory cells, each cell programming their state, A method of operating an integrated circuit memory system that is addressable for reading includes the following steps: providing a plurality of distinct blocks of memory cells, the cells of the individual blocks together. Erasable, performing an erase operation on the memory cells in the at least one block, and unerased cells in the at least one block after the erase operation is performed Determines whether or not exists, and if so, removes such In the steps of determining the number of non-erased cells and comparing the number of non-erased cells with the acceptable number, the acceptable number is substantially the maximum number of cells and the data in the cell is A comparing step that can be corrected by an error correction scheme, and if the number of non-erased cells in a block is less than the allowed number, the memory of at least one erased block is replaced with new data. Reprogramming, and replacing the non-erased cells with another auxiliary memory if the number of non-erased cells in a block is more than allowed.
It is composed of (A2) In the method described in (A1), the step of replacing determines the address location of an unerased cell in at least one block, stores the address location, and assigns a good secondary cell to it. It is composed of the steps of replacing. (A3) The method according to (A1) above further comprises the step of setting a flag if the number of unerased cells in at least one block exceeds another number considerably larger than the allowed number. (A4) In the method described in (A1) above, the erase operation is performed as follows: addressing at least a block, initiating an erase cycle of a memory cell therein, and during the erase cycle. Determining the state of the memory cells within at least some blocks in the block, and when it is determined that all memory cells in at least one block should be erased, or when a predetermined condition is reached. , At least 1
Terminating the erase cycle before all cells of one block are erased. (A5) In the method according to (A4), the predetermined condition reaches a condition that all the memory cells in one block are erased leaving a predetermined number or a smaller number. It is configured to include conditions. (A6) An integrated circuit memory system includes an array of non-volatile floating gate memory cells, each cell of which is capable of addressing its state for programming and reading, in a method of operating said memory system: memory cell Provides multiple distinct blocks of
There the cells of the individual blocks can be erased together to form some ground state, where 1
Memory cells in one or more erased blocks are subsequently provided with a block to be reprogrammed, addressing one of the plurality of blocks and initiating an erase cycle of the memory cells therewith; Determining the state of that memory cell in at least a block during a cycle, and at least when it is determined that all memory cells in a block should be erased to the ground state, or at least in all of a block Terminating the erase cycle when a predefined condition is reached before all cells in the block are erased, at least if the erase cycle is terminated before all cells in a block are erased. At least the number of unerased memory cells in a block is A step of determining whether the error correction plan is less than or more than the maximum number of cells that can be corrected when the data is incorrect, and if the number of cells not erased within at least a block is less than the allowed number, Reprogramming the memory cells in the at least one erased block with new data;
At least when the number of non-erased cells in a block is greater than the allowed number, then using other auxiliary memory cells in place of the non-erased memory cells. (A7) In the method described in (A5), the substituting step includes a step of determining an address position of a cell which is not erased in at least a block. (A8) In the method according to (A5), the predetermined condition of the erase cycle is that a certain condition is reached, and the condition is the allowable number of memory cells in at least one block or less. Except in the case, all the memory cells in the at least one block are erased. (A9) In the method described in (A5), the erase cycle includes a step of applying a plurality of erase pulses to the memory cells in at least one block in a state determined between erase pulses. Has been done. (A10) In the method described in (A9), the predetermined condition of the erase cycle includes a step of reaching a given number of erase pulses during the erase cycle. (A11) In the method described in (A9), the plurality of erase pulses increase in amplitude during the erase cycle, and the predetermined condition is that the amplitude of the erase pulse is a predetermined maximum level. It consists of steps to reach.

An embodiment of an algorithm for erasing a flash EEprom memory system according to the present invention includes: (B1) targeting a block of addressed cells in an array of electrically erasable and programmable read only memory rows and columns. In the method of erasing to an erase charge level, each cell has a field effect transistor with a threshold voltage, said voltage being changeable by controlling the charge level at its floating gate, The method includes the following steps:
Applying a controlled voltage compatible with the cells of the block of addressed cells towards a target erase charge level for a time sufficient to change their respective charge levels, and thereafter addressing Reading the level of charge on the floating gates of at least a plurality of cells in the block of stored cells; determining whether one of a plurality of conditions has occurred associated with some of the plurality of cells; Until it is determined whether one of the plurality of conditions occurs in at least some of the plurality of cells,
Repeating the above steps as many times as necessary, followed by reading the floating gates and charge levels of the cells of the block of addressed cells, and then during the block of addressed cells, the cells are targeted. Determining the number of cells N that have not reached the erase charge level to be erased, and thereafter comparing the number of cells N with an acceptable number X of unerased cells. There is. (B2) In the method according to (B1) above, at least some of the plurality of cells are made up of substantially less than all cells in the block of addressed cells. (B3) In the method of (B1) above, an erase pulse is applied to the block of addressed cells after it has been determined that one of a plurality of conditions occurred in association with the plurality of cells. The method further includes the step of applying. (B4) In the method according to (B1), in addition to the fact that it is confirmed in the comparison step that the number of cells N has not reached an erase level exceeding an allowable number X, ) Generating the address location of the cells not reaching the erase level when the number of cells not reaching the erase level is less than or equal to a second number of cells higher than the acceptable number; (b) A method including any of the steps of generating a patience limit flag if the number of cells N that have not reached the erased level exceeds the second number of cells. (B5) In the method according to (B1), the plurality of conditions include a condition that the number of cells N that have not reached an erase target voltage level of an addressed block of cells is equal to or less than an allowable number. It is composed of. (B6) A method of erasing memory states from a block of addressed cells of an array of electrically erasable and programmable read only memory (EEPROM) cells, the cells programming the states into the cells. ,
A natural threshold voltage that has a means for addressing the cells for reading and erasing, and each cell can control and change the floating gate charge level to obtain an effective threshold voltage. In a method having a field-effect transistor with a voltage corresponding to that when the level of charge on its floating gate is equal to zero, the natural threshold voltage comprises: Pulse the addressed cells with a predetermined period and voltage sufficient to change their individual threshold voltages, but not enough to reach the erase threshold level. Pulse, followed by reading the current through a selected number of cells to ensure their effective threshold voltage. The steps of applying and reading are repeated a plurality of times, after which any one of the following conditions occurs, after which the step of applying and reading the pulse is terminated: the effect of each of a selected number of blocks of addressed cells. The threshold voltage has reached an erased threshold level; the pulse applying step has reached a preset maximum number; or a predetermined maximum voltage for the pulse is the most A recent pulsing step has been reached; the number of selected cells, N, left unerased completely is equal to or less than the number of unerasable cells that can be accepted. (B7) By the method according to (B6), the predetermined voltage is raised by a certain increment from that of the previous pulse applying step. (B8) In the method according to (B6) above, after first detecting that one of the plurality of conditions has occurred,
The method further comprises the step of applying an erase pulse to the addressed cell. (B9) In the method according to (B6) above, the selected number of cells is clearly less than the total number of addressed cells.

The flash EEprom memory system according to the present invention comprises: (a) a flash electrically erasable and programmable read having a memory state defined by the actual charge on the floating gate electrode capable of modulating the conduction of the transistor channel. In the only memory cell,
Means for introducing one of more than a given amount of charge into the floating gate for indefinite storage until removed by electronic erase provides a distinct and distinct memory state. It is characterized in that the given quantity corresponds to the definite memory status. (A) The floating gate modulates the conduction of some of the channels of the transistor. (C) An array of electrically erasable and programmable read-only memory cells with means for addressing in order to read and erase individual cells for programming and to erase their state, each cell being a field effect transistor. , The transistor has a natural threshold voltage, which can be modified by applying a level of charge to the floating gate to select one valid threshold voltage. , The natural threshold voltage corresponds to a state of zero charge on the floating gate, and is a method for programming memory states of cells in an addressed array, the method comprising the steps of: In the process of determining the effective threshold voltage of a plurality of levels, the levels of which are more than 2, and the detection of which is greater than 2. Erasing a cell by lowering its threshold voltage to a base level, which corresponds to the state of each active cell whose base level is the state of multiple detectable cells, which state is the charge of the floating gate. Is lower than the lowest of those determined by increasing. Programming the cell into its plurality of states The programming is accomplished by adding a negative charge to its floating gate until its effective threshold voltage is substantially equal to the plurality of effective threshold voltages. . (D) In the method described in (c) above, the step of establishing a plurality of effective threshold voltages includes at least establishing four such voltage levels, wherein the cell stores at least two bits of information. It becomes possible to do. (E) In the method described in (d) above, the step of establishing the threshold voltage level includes the step of selecting at least two voltages lower than the natural threshold voltage of the cell transistor. (F) In the method described in (c) above, the step of programming the cell to one of the plurality of threshold voltage levels, the step of sending a pulse to the cell by a short programming pulse, and the programming pulse being applied. Later, it alternates readings of the current flowing through it and continues until the level of that current is at the desired one of the effective threshold voltages, the short program pulse being two The program pulse is short enough to change the threshold voltage which is half the threshold voltage difference. (G) In the method described in (c) above, the step of erasing the cell comprises pulsing the cell with an erase pulse,
The current flowing through it is read and continued until it reaches the desired base threshold voltage, the magnitude and duration of each erase pulse being such that the first erase pulse is not sufficient to completely erase the cell. And the subsequent erase pulse is raised by a defined amount until the cell is completely erased. (H) The method according to (G) above, further comprising the step of adding 1 to a counter after the cell is completely erased to the base threshold level to monitor the number of times the cell is erased. It is a waste. (X) In the method described in (X), the step of erasing the cell includes the step of stopping the generation of the erase pulse when the number of erase pulses exceeds a predetermined number. (Co) Read and program individual cells for
To erase its state, an array of electrically erasable and programmable read only memory cells with addressing means, each cell having a field effect transistor,
The transistor has a natural threshold voltage,
The threshold voltage can be modified by applying a level of charge to the floating gate to select one valid threshold voltage, the natural threshold voltage being equal to zero charge on the floating gate. The first and second memory states correspond to the first and second valid threshold levels, respectively, and address the cells of the array to the first or first A method for programming the two states, comprising the steps of: The addressed cell is pulsed at a predetermined time and voltage to change the charge on its floating gate and change its threshold voltage, the threshold voltage of which is the first and second. 1 of effective threshold voltage
½ is not sufficient to change the current then flowing through the cell to determine if the self-threshold voltage has reached a new desired first or second state. The pulse generation is repeated, and until the addressed cell reaches the desired first or second memory state, the programming of the addressed cell of that cell is completed. An array of electrically erasable and programmable read-only memory cells having means for addressing the cells for programming and reading and erasing the states, each cell being valid Effect transistor with a natural threshold voltage that is variable by controlling the level of charge on the floating gate to obtain a uniform threshold voltage And the natural threshold voltage is a method for erasing the memory state of a group of addressed array cells for such an array corresponding to when the floating gate charge is zero. And including the steps of: pulsing the addressed cell at a predetermined time and voltage for changing the threshold voltage, but completely pulsing the cell at a level that cannot be erased. Reading the current flowing through the addressed cells to identify their altered threshold levels.Pulsing the pulse.Retrieving the pulse multiple times, with each repetition of the pulsing the voltage of the last pulse. It has a repetitive process of increasing the process by a fixed amount. (Vi) The memory erasing method described in (v) above includes an additional step of accumulating a count equal to the total number of times the cell has been erased. (S) In the memory erasing method described in (S), the repetition of the pulse applying and reading steps is terminated when any one of the following conditions occurs first for each addressed cell. The threshold voltage of each has reached the erased state, the predetermined number of erase pulses have been applied, the maximum voltage of the predetermined erase pulse has been reached, or the When the non-erasables fall below a predetermined acceptable non-erasable number. (C) An electrically erasable and programmable read-only memory cell, each cell including a channel isolation field effect transistor, the transistor being a source and drain region separated by a channel region in a semiconductor substrate. A transistor having a floating gate insulated from the channel region adjacent to the drain and located thereon, a control gate insulated from the floating gate and provided on the floating gate, and another portion of the channel adjacent to the source Where the transistor has a first portion with a natural threshold voltage by which the level of charge on the floating gate can be modified by control to obtain an effective threshold voltage, where the natural threshold is Value voltage is floating Corresponding to the case where the charge of the gate is equal to 0, and the conductance of the first transistor portion is determined by the voltage of the control gate and the level of the charge of the floating gate.
The transistor then has a second portion in series with the first portion, which has a conductivity determined by the charge on the control gate to erase the storage state of cells in the array. , A system for programming and reading includes the following arrangements: means for connecting one or a group of memory cells selected for addressing the array means for connecting the array for erasing the addressed cell Or move the effective threshold voltage of a group of cells to the base level by moving the charge on the floating gate of each cell in the positive direction to add a negative charge to the floating gate of the addressed cell. Programming means connected to said array for one of two or more effective threshold voltages Substantially until the corresponding, whereby each cell of the array is programmed to a state corresponding to one of two or more states to determine the amount of current flowing through the addressed cell. Connected read-out means are provided for detecting individual currents corresponding to a number corresponding to the effective threshold voltage level, by means of which the state of the measured current level of the addressed cell is determined. decide. (B) In the memory array erasing, programming, and reading system according to (b), the array of memory cells has a common connection between the control gates of the rows of memory cells, and the programming means is common to the cells of the rows. Means for applying said first high back voltage to the connection;
Means are provided for applying the second high voltage to the drains of the memory cells contained in the row that do not reach the desired effective effective voltage level to be programmed therein. (A) A read-only electrically erasable and programmable memory system including the following structure: a semiconductor substrate including an array of storage cells in rows and columns, each cell including a transistor, the transistor being It has a floating gate with a source region and a drain region and a channel region provided between them, the charge of which affects the level of conduction between the source and the drain. Column Means Affecting Conduction Level Between Drains Can be Connected to Addressed Columns of the Storage Cell Transistors to Control Voltage Applied to Source and Drain of Cells. Column Means Programmable Means Connectable to Addressed Rows of the Cell Transistors to Control the Voltage of the Control Gate of the Cells Voltage Means to Cells Addressed to Row Means and Column Means in Response to Addresses of Specific Cells Reduce the conductance of the addressed cell transistor by applying a voltage to the floating cell to increase the charge on its floating gate. The state is detected by detecting the level of the current flowing between the drain and the source of the addressed cell by applying a voltage to the column means and further increasing the voltage level of the control gate of the addressed row. Erasing means connected to the storage cells of the array The following improvements are included in the system for removing the charge from the floating gates of a plurality of storage cell transistors: the read means includes means for distinguishing between the two current ranges of the addressed cell, whereby each cell is The programming means having corresponding two or more states has a means corresponding to the reading means, supplies a programming voltage to the cells addressed to the row means and the column means, and flows to the addressed cells. The charge on the floating gate is increased until the read current is in one of two current ranges. (H) The improved memory system described in (t) above includes means for counting and storing the number of times the plurality of storage transistor cells have been erased. (T) In the improved memory system according to (T), the read means additionally has at least one sense amplifier, which sense amplifier is connectable to the drain of the addressed cell. The above reference levels are provided by the actuation sense amplifiers, thereby providing two or more programmable conductance levels to each addressed cell. (T) In the improved memory system according to (T), the erase means has an improved means selected for the row means and the column means, applies an erase voltage and a short erase pulse, and then outputs a cell current. With a repeated cycle of reading, the initial erase voltage is chosen to be insufficient enough to completely erase the cell, and the amount of pulse is gradually increased from pulse to pulse, and the pulse is desired because the cell current increases. Is increased to the level that causes the cell to be completely erased. (G) In the improved memory system according to (g) above, the erase means continues the erase cycle until the first occurrence of one of the following conditions. Reaching the erased base level, or supplying a predetermined number of erase pulses,
Or a predetermined maximum erase pulse voltage has been reached, or the number of addressed cells that are not completely erased is less than a predetermined, non-erased, acceptable number. (N) In the improved memory system according to (T), the floating gate of the transistor is
The conductance level of the first portion of the channel between the source and drain regions is affected, and the conductance level of the second portion of the channel between the source and drain regions is determined by the voltage on the control gate. Further, other additional objects, advantages of the present invention, and preferred embodiments will be described with reference to the accompanying drawings.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, the structure of a channel-separated Eprom or EEprom cell is shown, which structure is suitable for the improved memory array and its operation according to the present invention. Semiconductor substrate 11
Has a source region 13 and a drain 15, which are usually formed by ion implantation. A channel region 17 is provided between the source and the drain.
A floating gate 19 is provided above the portion of the channel region labeled L1 and is separated from the substrate by a thin gate oxide 21. A control gate 23 is formed in the upper portion of the channel region labeled L2 and is separated from the substrate 11 by a thin gate oxide layer 25. Control 23 is also electrically isolated from floating gate 19 by oxide layer 27. The amount of charge on floating gate 19 is programmed to correspond to the desired state to be stored in the cell. If the level of this charge exceeds a certain threshold, the cell is considered to be in one state. If it is below that threshold, it is defined to be in another state. The desired charge level can be obtained by applying electrons to the substrate 1 by applying an appropriate voltage combination to the source, drain, substrate and control gate for a fixed period of time.
The desired charge is programmed by moving from 1 to floating gate 19. The floating gate is confined in one memory cell, and the gate is electrically isolated from all other parts of the structure. In contrast, control gate 23 extends across many cells and serves as a common word line. As will be referred to hereinafter, the channel-separated type provides the same function as two field-effect transistors connected in series, one of which has its floating gate 19 as its control gate and the other of which controls. The gate 23 is used as the control gate.

The primitive channel-separated Eprom or EEprom shown in FIG. 1 has a flash E by adding an erase gate (not shown).
Become an Eprom device. The erase gate is a separate electrode, located beside the floating gate 27 and is then separated by a tunnel dielectric. The amount of charge on the floating gate is reduced when the appropriate voltages are applied to the source, drain, substrate, control gate and erase gate. Since one erase gate extends over many memory cells, they are erased at the same time, if not the entire array. In one prior art flash EEprom cell, the source or drain diffusion region underneath the floating gate is used as the erase electrode, while in other cells the erase electrode is the same layer as the control gate. It is provided in a layer or a separated conductive layer.

[Other State Storage] The channel-separated flash EEprom device has two states as shown in FIG.
It can be regarded as a composite transistor composed of two transistors T1 and T2 connected in series. Transistor T1 is a floating gate transistor having an effective channel length L1 and a variable threshold voltage V _T1 . Transistor T2 is a transistor having a fixed (enhancement) threshold voltage V _T2 and an effective channel length L2. The Eprom programming characteristic of the composite transistor is shown by the curve (a) in FIG. The programmed threshold voltage V _tx is plotted as a function of time t given the programming conditions. These programming conditions are typically V _CG = 12V, V _D = 9V, V _S =
V _BB = 0V. When either V _CG or V _D is 0V, programming does not occur (unprogrammed, not erased) devices have V _T1 of + 1.5V.
Therefore, V _T2 has + 1.0V. After programming for approximately 100 milliseconds, the device has a threshold voltage V _tx ≧ + 6.0.
Reach V. This indicates an off (“0”) state. This is because the composite device does not conduct at V _CG = + 0.5V. Conventional devices used so-called "intelligent programming" algorithms. This typically provides programming pulses each lasting 100 to 1 millisecond, followed by a sensing (reading) operation. The pulses are applied continuously until it is detected that the device has been turned off altogether, then three extra programming pulses are provided to ensure that it has positive programmability. In the prior art channel-separated flash EEprom device, a sufficient voltage V
Erase with one pulse with _ERASE and a sufficient period,
See if V _T1 has been erased to a voltage below V _T2 (curve (b) in FIG. 3). The floating gate transistor continues to be erased until it is erased by depletion mode operation (line (c) in FIG. 3).
The presence of the series transistor T2 makes this depletion threshold voltage unclear. Therefore,
The threshold voltage V _tx = erased state (“1”)
It is represented by V _T2 = + 1.0V. The memory storage “window” is ΔV = V _tx (“0”) − V
_{It is} given by _tx (“1”) = 6.0−1.0 = 5.0V.
However, the true memory storage window should be represented by the total swing of V _tx of transistor T1. For example, if transistor T1 is erased to a depletion threshold voltage V _T1 = -3.0 V,
As a result, the true window is ΔV = 6.0V-(-3.0)
= 9.0V should be provided. None of the prior art flash EEprom devices utilized this true storage window. In fact, those of the prior art show that the operation of the device in the region (shown as hatched region D in FIG. 3), here V _T1
Ignores all regions below V _T2 .

The present invention first proposes a plan that takes advantage of this full storage window feature. This allows more than two binary states of storage by using a wider storage window, and consequently more than one bit per cell. For example, it is possible to store 4 instead of 2 in one cell, this state having the following threshold voltage: State “3”: −V _T1 = −3.0 V, V _T2 = + 1.0 V (most conductive state) = 1,1. State “2”: −V _T1 = −5.0 V, V _T2 = + 1.0 V (intermediate conduction) = 1,0. State “1”: −V _T1 = + 2.0 V, V _T2 = + 1.0 V (low conduction) = 0,1. State “0”: −V _T1 = −4.5 V, V _T2 = + 1.0 V (non-conduction) = 0,0. To detect any of these four states, the control gate is raised to V _CG = + 5.0V. Then, the source / drain current _IDS is sensed through the composite device. V _T2 = + for all four threshold states
Since it is 1.0 V, the transistor T2 simply behaves as a series resistance. The conduction current I _DS corresponding to the four states of the composite transistor is shown in FIG. 4 as a function of V _CG . The current sense amplifier can easily distinguish between these four conduction states. The number of possible states in practice is affected by the noise sensitivity of the sense amplifier and the loss of charge over the expected time when the temperature rises. Eight distinct conduction states are needed for storage of 3 bits per cell,
Sixteen distinct conduction states are required to store four bits in one cell. For multi-state memory cells, already read-only memory (ROM) and DRAM
It has been proposed in connection with (Dynamic Random Access Memory). In ROM, it is possible to have one of several fixed conducting states by forming two or more permanent threshold voltages by making different channel implants. Prior art multi-stage DRAM cells have been proposed in which each cell of the array is physically identical to the other cells. However, the charge stored in the capacitor of each cell is quantized, resulting in several different read signal levels. For storage of such prior art multi-stage DRAMs, see IEEE Journal of Solid-State Circuits, 1988.
Page 27 of the year. As a paper by M. Horiguchi et al., "A large-capacity semiconductor file memory by using 16 levels of cell storage"("An Experimental Large-Capa
citySemiconductor File Memory Using 16-Levels / Cell
Storage ”), a second example of a multi-stage DRAM, at TEE Furuyama et al. Experiment for DRAM that stores 2 bits per cell for
(“An Experimental 2-Bit / Cell Storage DRAM for Ma
crocell or Mem-ory-on-Logic Applications ”).

In order to make effective use of multi-stage storage in Eprom, it is necessary that the algorithm of the program of the device allows the program to be in any of several conduction states. First of all, it is necessary to be able to erase up to the voltage V _T1 which is more negative than the state of “3” (-0.3 V in this embodiment). The device is then programmed with a short program pulse, typically a pulse of duration 1 to 10 milliseconds. Program condition is 1
One pulse does not move the effect over the threshold of the device by more than half the difference in threshold between two subsequent states. The device is such that its conduction current I _DS and i of the reference power supply I _REF (i = 0, 1, 2, 3) correspond to the desired conduction states (in order to correspond to the four states,
4 reference levels are required) and are detected by current comparison. The programming pulse is sustained (dashed line in FIG. 4) until the sensed current (solid line in FIG. 4) is just below the reference current corresponding to the four desired situations. To better illustrate this point, each programming pulse rises linearly to V _tx at 200 millivolts. And, further, this device initially has V _T1 = −
Assume erased by 3.2V. Then the required programming / sensing pulses are: For state "3" (V _T1 = -3.0 V) Number of pulses = (3.2-3.0) /. 2 = 1 For state “2” (V _T1 = −0.5 V) Number of pulses = (3.2−0.5) /. 2 = 14 for state "1" (V _T1 = + 2.0 V) Number of pulses = (3.2-(− 2.0)) /. 2 = 26 for state “0” (V _T1 = + 4.5 V) Number of pulses = (3.2 − (− 4.5)) /. 2 = 39 As a matter of fact, V _tx is not a straight line with respect to time. This is shown in curve (a) of FIG. as a result,
More pulses are needed than indicated by the state "1" or "0". If 2ms is the width of the programming pulse and 0.1ms is the time required for detection, then the maximum time required to program the device to any of the four states is About 39 × 2 + 3
9 × 0.1 = 81.9 milliseconds. This is less than the time required by prior art devices "intelligent programming algorithms". In fact, in the new programming algorithms, only a carefully measured set of electrons is injected during the program. Yet another advantage of this approach is that sensing on reading is the same sensing as programming. And the same reference current source can be used for both programming and reading operations. This means that all memories in the array can be programmed and sensed with the same reference level. This provides excellent tracking even on very large memory arrays. Large memory systems typically have built-in error detection and correction procedures that protect against a small number of defects in the hardware, such as cells that react badly to flash. Designed to withstand. For this reason, even after a certain amount of maximum number of program cycles has been performed, even when there is an indication that the memory cell is malfunctioning without it reaching the desired threshold, it has been programmed. , Programming and sensing cycle algorithms can be stopped automatically.

However, there are some of the concepts of multi-strip storage associated with arrays of EEprom transistors. An example of such a circuit is shown in FIG. In this circuit, one array of memory cells has a decoded word line and a decoded bit line, each connected to the control gates and drains of the row and column cells, respectively. Each bit line is normally 1. during the read, program or erase time.
Pre-charged to a voltage between 0V and 2.0V. 4
Due to the accumulation of stages, the four sense amplifiers each have their own reference level, I _REF 0, I _REF 1, I _REF 2, I _REF.
3 has a reference voltage for the decoded output of each bit line. During a read, the current through the flash EEprom transistor is compared (in parallel) with these four reference levels at the same time.
This operation can likewise be carried out by having four consecutive read periods (i.e. with one sense amplifier and a different reference applied to each cycle). This is useful when additional time is required because of no problem.). The data output is provided by four Di buffers (D0, D1, D2 and D3) via four sense amplifiers. During programming, four data inputs Ii (I0, I1, I2 and I3) are provided to the comparison circuit, which is also provided with the outputs of the four sensor amplifiers for the accessed cell. If D
If i and Ii match, then the cell is in the correct state and no programming is required. However, if all four Di do not match all four Ii, the comparator output will activate the program control circuit. This circuit controls the bit line (VPBL) and word line (VPWL) program pulse generators. One short programming pulse is applied to both the selected word line and the selected bit line. This is followed by a second read cycle to determine if Di and Ii match. This sequence is repeated for multiple program and read pulses, until they match (or no match at the beginning, then
It is determined when the preset maximum number of pulses is reached). As a result of such a multi-step programming algorithm, each cell is programmed into four conduction states directly related to the reference conduction state I _REF , i. fact,
The same sense amplifier is used for the program and read pulse generator, and it is also used for the detection period (normal reading period). This allows good tracking in large memory arrays between the reference level (dashed line in FIG. 4) and the programmed conduction level (solid line in FIG. 4) and within a very wide operating temperature range. In addition,
The device will experience a minimal amount of tolerable stress as carefully measured electrons are injected into or removed from the floating gate during programming or erasing. In fact, four reference levels and four sense amplifiers are used to bring the cell to the conducting state of one of the four, but only three sense amplifiers and three reference levels are needed for the four storage strips. It is necessary to detect one of the correct states in. For example, in FIG. 4, I _REF (“2”) is in the conductive state “3”.
And "2" are correctly discriminated, I _REF ("1") can be correctly discriminated between conducting states "2" and "1", and I _REF ("0") is conducting state " It is correctly discriminated between "1" and "0". In a realistic configuration of the circuit of FIG. 6, the reference levels I _REF , i (i = 0,1,2) are to detect the conduction states of the corresponding lower and higher cells during that period. You may move so that it may come closer to those center points. Note that the same principles used in the circuit of FIG. 6 apply to two stages of storage or more than four states per cell. Of course, other circuits than those shown in FIG. 6 are also possible. For example, rather than conducting level sensing, it could be used for voltage level sensing as well.

[Improving Charge Retention] In the above-mentioned example, the states “3” and “2” are the result of the positive charge in the floating gate, whereas the states “1” and “0” are the states. This is due to the negative charges (electrons) on the floating gate. Life of this device (125 ℃
In order to properly detect the correct conduction state during 10 years), this charge must not leak from the floating gate more than equivalent to a shift of 200 millivolts at about V _T2 above. is necessary. This condition is readily applicable to the stored electrons, Eprom or flash EEprom in this embodiment or in all prior art. Due to the physical considerations of the device, the retention of holes trapped in the floating gate should be distinctly better than the retention of trapped electrons. This is because the trapped holes are neutralized only when electrons are injected into the floating gate.
It is a field barrier at the silicon-silicon dioxide interface of about 5.
It is almost impossible for holes to overcome 0 electron volt (the field barrier of trapped electrons is 3.1V). Therefore, improving the holding power of this device can be improved by using the area associated with holes trapped in the conductive state. For example, in the state “1”, V _T1 is +2.0 V
Which is related to the trapped electrons,
In the virgin device, V _T1 is 1.5V. However, in the virgin device, if one raises its V _T1 to a higher threshold voltage, for example V _T1 = + 3.0 V (by increasing the p-type doping concentration of the channel region 560a in FIG. 5a), then the same State "1" is V _T1 =
It will be + 2.0V, which will be done by the trapped holes. This value of V _T1 will give better retention. Of course, the reference level little, or less more than V _T1 of the virgin device all states V _T1
It is also possible to set the reference voltage to have a value of.

[Erasure of Information for Improved Endurance]
The endurance of flash EEprom devices is their ability to withstand a given number of write and erase cycles. A physical phenomenon that limits the durability of prior art flash EEprom devices is the trapping of electrons in the active dielectric film of the device. The dielectric element used during programming traps some of the injected electrons during thermionic channel injection. During erase, the tunnel erase dielectric also traps some of the tunnel electrons. Since the trapped electrons resist the applied electric field in the subsequent erase cycle,
This causes a decrease in the threshold voltage and a shift in V _tx . This can be observed as the window of voltage between the “0” and “1” states gradually closing (see FIG. 5).
When the program erase cycle of approximately 1 × 10 ⁴ is exceeded, the degree to which the window is closed causes the detection circuit to malfunction. If this cycle is continued, the device will experience a critical collapse phenomenon due to damage and decay of the dielectric. This typically occurs between 1 × 10 ⁶ and 1 × 10 ⁷ cycles. And it is known as the breakdown due to impurities in this device. In the memory device as the prior art, the practical limit of how to close the window is 1 × 10 ⁴ cycles. For a given erase voltage V _ERASE , the time required to fully erase the device reaches 100 seconds from the initial 100 milliseconds (ie, in the virgin device) to 10 seconds in the device which has been performed 1 × 10 ⁴ times. . One such quality degradation in prior art flash EEprom devices is
In order to allow sufficient erasing after using × 10 ⁴ times or more, an extremely long erasing pulse time had to be defined. However, this was an excessive erasure in the virgin device, resulting in unnecessary excessive distortion. A second problem with prior art devices was that the tunnel dielectric was exposed to unnecessarily high peak stress during the erase pulse. This is the state "0" (V _T1
= + 4.5V or higher). This device has a large negative charge Q
Have. When V _ERASE is applied, the tunnel dielectric will be momentarily exposed to a peak electric field due to the effect of Q as with V _ERASE . This peak electric field gradually decreases when the charge Q changes to 0 in the process of tunnel erasing. Nevertheless, permanent and cumulative damage is added in the process of this erasure.
This results in premature device collapse. To overcome these two problems of overstress and window closing, a new erasure algorithm was disclosed. It is applicable to any of the preceding flash EEproms. Without such a new erasure algorithm, implementing a multi-state device would be from curve (b) of FIG. 5 from 1 × 10 ⁴ if the conduction state is V _T1 is more negative than V _T2. It will be erased in 1 × 10 ⁵ write / erase cycles.

FIG. 7 shows the main steps of the new erasure algorithm. Assume that a block array of m × n memory cells has been completely erased by flash erase to state “3”, which is the highest conductive state and lowest V _T1 state. Certain parameters are set in relation to the erasure algorithm. They are listed in FIG. 7, where V ₁ is the erase voltage of the first erase pulse. V ₁ is probably less than 5V from the erase voltage required to erase the virgin device to state "3" with an erase pulse of 1 second. t is approximately 1/1 of the time required to completely erase the virgin device to state "3"
Selected as 0. Typically, V ₁ is between 10V and 20V, while t is between 10 and 100 milliseconds. This algorithm assumes some small number X of bad bits that the system can tolerate (this system level is determined in the process of error detection and correction as an example. If there is no error detection and correction, In that case X = 0). These are the bits that are shorted or very leaky tunnel dielectrics that are not erased by the application of a sufficiently long erase pulse. To prevent excessive erase, the total number of erase pulses can be limited to a preset n _max in the erase cycle of all blocks. ΔV is a voltage by which subsequent erase pulses are enhanced. Typically, ΔV is 0.25V to 1.
It is between 0V. As an example, if V ₁ = 15.0V and ΔV = 1.0V, then the seventh erase pulse has a magnitude of V _ERASE = 21.0V and a duration of t.
It is. One cell is considered completely erased. That is, it is when the read conductance becomes larger than I _"3" . The number S of complete erase cycles experienced by each block is very important information at the system level. If S is known for each block, then S is 1 × 10
^{When the 6} (or other set number) program erase cycle is reached, those devices can be automatically replaced with new auxiliary blocks. S is initially set to 0, and is sequentially incremented with every multiple block cycle of each complete block erase. As the value of S, for example, 20 bits (2 ²⁰ corresponds to approximately 1 × 10 ⁶ ) can be prepared and stored in each block for each time. That way, each block can keep its own record of endurance. Alternatively, the S can be stored in a system separate from the chip.

The sequence of the complete erase cycle of the new algorithm is as follows (see FIG. 7). 1. Read S. This value can be stored in the register file. (This step can be omitted if S is expected not to reach its limit during the operating life of this device). 1a. First erase pulse V _ERASE = V ₁ + nΔV, n =
Apply 0, pulse duration = t. This pulse (and the next few consecutive pulses) is sufficient to erase all memory cells, but it will reduce the charge Q of the programmed cell, which is a relatively low erase field. It's stress. Ie it is 1
It is equivalent to one "condition making" pulse. 1b. Read the sparse patterns in the array. A diagonal reading pattern would, for example, read m + n cells (rather than a complete reading by m × n), and take at least one cell from each row and one cell from each column. It will be. Compare the number N and X of cells that have not been completely erased by state "3". 1c. If N is x (array not fully erased)
If it is larger than the second erase pulse, the second erase pulse is applied by ΔV larger than the first pulse and the second erase pulse having the same duration t is applied. You can read the diagonal cells and count N.
In this erase cycle, the erase pulse of pulse / read / add is continued until N ≦ X or the number n of erase pulses exceeds n _max . The first of these two conditions leads to the final erase pulse. 2a. A final erase pulse is applied to confirm that the array has been completely and fully erased. The magnitude of this V _ERASE is larger than the previous pulse by a fraction of ΔV. The duration can be between 1t and 5t. 2b. 100% of the array is read. The number N of cells that have not been completely erased is counted. If N is less than or equal to X, erasing pulsing is completed at this point. 2c. If N is greater than X, then the address of the existence of the non-erased bit N is generated. It is for good spare bit swapping at this system level. If N is significantly greater than X (if N is 5% of the total cells), flag it in such a case and let the user reach its patience limit at the end of life. Indicates that it has become. 2d. The erase pulse is terminated. 3a. One S is added. The new S is then saved for future reference. This step is optional. The new S is either written into the newly erased block or stored in a register file separate from the chip. 3b. The erase cycle is terminated. A complete cycle is 10 to 20 erase pulses, expected to be erased in about 1 second.

The new algorithm has the following features. (A) No cells in the array are subject to peak electric field stress. By time V _ERASE , the relatively high voltage and any charge Q has already been removed from the floating gate by the previous low voltage erase. (B) The total erase time is much shorter than that of the prior art using a fixed V _ERASE pulse. In a virgin device, the erase time required is a minimum pulse. Even a device capable of withstanding 1 × 10 ⁴ cycles or more is not required to increase the voltage by several times ΔV in order to overcome the dielectric trapped charges. And the charge trapped in the dielectric only increases its total erase time by a few hundred milliseconds. (C) The narrowing of the window on the erase side (see curve (b) in FIG. 5) can be avoided infinitely (until the device is spoiled by sudden destruction). This is because V _ERASE is simply increased until the device is in the erased proper state "3". The new erasure algorithm can save the whole storage window.

FIG. 8 shows a flash EEpro according to the present invention.
4 shows the four conduction states of the m device as a function of the number of program erase times. All four states, always is possible to fix the reference conduction states by the program or erase is complete, in any state, not that at least 1 × 10 ⁶ cycles window until is narrowed. In a flash EEprom memory chip, a voltage increasing device for generating a voltage V ₁ required on the chip (or on another control chip) to effectively execute a new erase program and an increment ΔV to nΔV of the voltage increase, A control and sequence circuit can be provided that includes a coefficient circuit that counts N and compares it to a stored value X, a register that stores the address of the location of the bad bit, and instructions for executing the erase sequence described above. . What has been described in detail as an embodiment of the present invention is a preferred embodiment, and those skilled in the art will appreciate many variations in this connection. Accordingly, the invention is entitled to protection within the full scope of the claims set forth herein.

[Brief description of the drawings]

FIG. 1 Channel-separated Eprom or EEpro
3 is a cross-sectional view of an example of m.

FIG. 2 is a schematic diagram showing a specific transistor representation for forming a channel-separated Eprom transistor.

FIG. 3 is a diagram showing programming and erasing characteristics of a channel-separated type flash EEprom apparatus.

FIG. 4 shows a channel-separated flash E according to the invention.
It is a figure which shows four conduction states of an Eprom apparatus.

FIG. 5 is a diagram showing life characteristics of a program erase cycle of a conventional flash EEprom device.

FIG. 6 is a circuit diagram and a diagram showing a program write voltage pulse required in a multi-stage memory device.

FIG. 7 is a schematic diagram showing the basic state of a new algorithm that can be erased with minimal stress.

FIG. 8 is a diagram showing a life cycle characteristic of a program / erase cycle of a flash EEprom device of a channel separation type using an information algorithm for reducing stress in multi-step program and erase.

[Explanation of symbols]

 11 ... Substrate 13 ... Source region 15 ... Drain region 17 ... Channel region 19 ... Floating gate 21 ... Gate oxide 23 ... Control gate

Claims (55)

[Claims] 1. An electrically changeable memory cell that is state changeable and addressable for reading, each memory cell including a field effect transistor having a floating gate. For a memory array whose level has a given level when no charge is present on the floating gate, but which is variable by the charge held by the floating gate. In a method of changing a state of a cell: establishing an effective threshold voltage above 2 corresponding to more than 2 detectable individual cell states, wherein at least two of said effective threshold voltages are established. The level is derived from the amount of positive charge on the floating gate, and Addressed cells can be detected by changing the amount of charge on the floating gate of the addressed cell until the threshold voltage of the addressed cell is approximately equal to one of the plurality of threshold levels. Setting a state. 2. The method of claim 1, wherein the set of detectable states is the effective threshold of an addressed cell by applying a negative charge to the floating gate of the addressed cell. A method comprising changing a voltage level. 3. The method of claim 1, further comprising the step of presetting the effective threshold voltage of the addressed cell prior to setting the detectable state of the addressed cell. Method included in. 4. The method of claim 1, wherein the array addressed is altered by changing the charge of the floating gate of the group of cells prior to setting the detectable state of the addressed cells. A method comprising presetting an effective threshold voltage of a group of included cells to a preset level. 5. The method of claim 4, wherein presetting the group of cells comprises presetting to a preset effective threshold voltage level outside the plurality of effective threshold voltage levels. . 6. The method of claim 4, wherein the presetting of the group of cells is lower than the lowest of the plurality of effective threshold levels by removing the negative charge of the floating gate. Establishing to the level the current effective threshold voltage level of the group of cells, and setting the detectable state of the addressed cell adds a negative charge to the floating gate of the addressed cell. A method including the steps of: 7. The method of claim 4, additionally comprising the step of reading the set state of the addressed cell after setting the detectable state of the addressed cell. 8. The method of claim 7, wherein reading the addressed cell in a set state causes a current to flow through the addressed cell, and at the same time at or above the level of the current. Method by comparing with reference current level. 9. The method of claim 1, wherein after setting the detectable state of the addressed cell, a current is passed through the addressed cell while the current is compared to a higher reference current level. The method additionally comprising the steps of: 10. The method of claim 9, wherein the current level is compared to a plurality of reference voltage levels that are one less than the plurality of effective threshold levels. How to include. 11. Any one of the methods of claims 1-11.
In one method, establishing a plurality of effective threshold voltage levels comprises establishing a majority of the threshold levels resulting from positive charges on the floating gate. 12. The method of any of claims 1-11, wherein establishing a plurality of effective threshold voltage levels comprises establishing at least four such threshold voltage levels. 13. A method according to any of claims 1 to 11, wherein the given threshold level of the individual cells is set to at least 3 volts. 14. A method according to any one of claims 3 to 5, comprising adding the total number of times the group of cells is preset. 15. The method of any of claims 3-5, including a block that replaces a block of auxiliary cells in the array when the group of cells becomes unavailable. 16. A method according to claim 1 or claim 3 including the step of replacing the addressed cell with an auxiliary good cell in the array in case the cell is destroyed. . 17. An electrically changeable memory cell that is changeable in state and addressable for reading, each memory cell including a field effect transistor having a floating gate and a threshold voltage. For a memory array having a level, the level having a given level when no charge is present on the floating gate, but variable by the charge held by the charge on the floating gate In the method of changing the state of the addressed cell: 2
Establishing an effective threshold voltage greater than 2 corresponding to a plurality of individual detectable states greater than, said addressing until substantially equal to one of said plurality of effective threshold voltage levels. The detectable cell of the addressed cell to one of the plurality of states by changing the amount of charge on the floating gate of the addressed cell to the effective threshold voltage of the addressed cell. The addressed cell is set by electrically interrogating the addressed cell and comparing the number of reference levels greater than 2 with the level of the electrical parameter of the addressed cell. A method that includes reading a state. 18. The method of claim 17, wherein establishing a plurality of effective threshold voltage levels comprises establishing at least four such threshold voltage levels. 19. The method of claim 18, wherein the threshold level applied to individual cells is established at least 3 volts. 20. The method of claim 17, wherein the step of reading the set state of the addressed cell comprises:
A method comprising simultaneously comparing an electrical parameter level with a number of reference levels that is one less than the plurality of states. 21. An array of a plurality of electrically erasable and programmable read only memory cells, each cell being formed on a semiconductor substrate with a source and a drain separated by a channel, and a floating gate from the channel region. Insulated and at least partially formed thereon, and a control gate insulated from and extending above the floating gate, the transistor being at a natural threshold voltage and controllable charge level on the floating gate. It has an effective threshold level derived from the combination with the corresponding voltage,
A system for erasing, programming, and reading storage states in the array, wherein the natural threshold voltage corresponds to the floating gate having a charge equal to zero, wherein: Means operatively connected to the array for addressing a plurality of memory cells of a group and modifying the effective threshold voltage of the addressed cell or cells of the group, respectively, the charge of the addressed floating gate. To drive to the base level by
Erase means operatively connected to the array and programming means operatively connected to the array
Changing the charge on the floating gates of one addressed cell to one of a plurality of effective threshold voltage levels in excess of two until the effective threshold voltage level is substantially equal; The threshold level corresponds to a detectable level greater than 2, wherein at least two of said plurality of effective threshold voltage levels are programming means derived from a controllable level on the floating gate; Read means operatively connected to said array for determining the amount of current flowing through the addressed cell,
A system including read means in which the state of the addressed cell is determined by the measured current level flowing therethrough. 22. The memory system according to claim 21, wherein said programming means is on the floating gate of the addressed cell until its effective threshold voltage is substantially equal to one of at least four threshold voltage levels. A system for altering the charge of the array, whereby individual cells of the array are programmable to four or more states. 23. A memory system according to claim 21, wherein
The system wherein the natural threshold voltage level is at least 3 volts. 24. The memory system according to claim 21, wherein
Responsive means of the erase means drive to a ground level of the effective threshold voltage of the addressed cell or group of cells and determine the number of times the addressed cell or group of cells has been erased in the array. A system that accumulates as a running count in and raises only one. 25. In an array of electrically erasable and programmable read-only memory cells, the cells are formed on a semiconductor substrate, the source and drain are separated by a channel region, and at least a portion of the floating gate is the channel. Formed over and above the region, and one control gate formed over and above the floating gate, wherein the transistor has a natural threshold voltage and a controllable charge on the floating gate. Of the array having an effective threshold level resulting from a combination with a voltage corresponding to the level of, the natural threshold voltage corresponding to the floating gate having a charge equal to zero. Erase, program, and Read Te A system: it has been selected 1
Or means for operatively connecting to said array for addressing a plurality of memory cells of a group, erasing means operatively connected to said array, and effective means for addressing the cell or group of cells. A threshold voltage is operative to the array for driving the effective threshold voltage of the addressed cell or group of cells to a ground level by modifying the charge on the floating gates of the individually addressed cells. Erase means connected to the array and programming means operably connected to the array
Changing the charge on the floating gates of one addressed cell to one of a plurality of effective threshold voltage levels in excess of two until the effective threshold voltage level is substantially equal; The threshold level determines the amount of current flowing through the addressed cells, programming means corresponding to more than two detectable levels, a plurality of reference sources providing two or more different reference current levels. Means for operatively connecting to the array for reading the state of the addressed cell by instantaneously comparing the amount of current flowing through the addressed cell with the reference current level, or 2 A system including a means having the above sense amplifier. 26. The memory system of claim 25, wherein at least two of the plurality of effective threshold voltage levels in the programming means are from positive charge on the floating gate. 27. The memory system of claim 25, wherein a majority of the plurality of effective threshold voltage levels in the programming means results from a net positive charge on the floating gate. 28. The memory system of claim 25, wherein the programming means substantially charges the floating gate of the addressed cell with an effective threshold voltage of one of at least four effective threshold voltage levels. A system in which the individual cells of the array are programmable to four or more states. 29. The memory system of claim 28, wherein the plurality of reference sources provide three or more different current levels. 30. An array of electrically modifiable memory cells is divided into blocks of cells, which has means for addressing individual cells within said block to read and modify their contents. The cell has field effect transistors each having a floating gate, has a threshold voltage level, said level being the level provided when there is no net charge on said floating gate, said level being retained on said floating gate. In a method of operating the array for an array of memory cells that is variable by the net charge being applied: establishing a plurality of threshold voltage levels greater than 2, said levels being individual cells. Corresponding to a plurality of detectable states of at least one of the blocks In the step of setting the effective threshold level of the cell to one of a plurality of levels,
Altering the amount of charge in the addressed at least one floating gate until the effective threshold voltage of the addressed at least one cell reaches one of a plurality of the effective threshold voltages. Wherein the state of said at least one addressed cell is set to one of said plurality of states, and the cells within each one of the blocks of said cells are of said plurality of states. Storing a count until it equals the total number of times set to one of the. 31. The method of claim 30, wherein the step of accumulating the counts of the individual blocks comprises accumulating the counts in the individual blocks. 32. The method of claim 30, further comprising the step of providing at least one auxiliary memory block, and said count of one of the individual blocks exceeding a set number being set. Responsive to exceeding a number, substituting the auxiliary block for each individual one of the blocks. 33. The method according to claim 30, comprising providing a plurality of auxiliary memory cells and at least some of the auxiliary cells are addressed in response to at least some of the addressed memory cells being defective. And replacing with at least one of the cells. 34. The method according to any of claims 30 to 33, wherein establishing a plurality of effective threshold voltages comprises establishing at least four such thresholds. 35. A system having electrically modifiable memory cells separated into blocks of distinct cells and having means for accessing individual cells in the block to read and modify their states. , Each cell includes a field effect transistor having a floating gate, each cell having a threshold voltage level, the level being variable according to the net charge held by said floating gate. , A method of operating the memory system comprises the following steps: (a) a threshold voltage level of memory cells above 2 wherein the level is above 2 individually detectable memory cell states. And (b) establishing one specified memory cell threshold voltage level, the memory cell Providing an auxiliary cell in place of any defective cell in the block of cells, the amount of charge on the floating gate of the memory cell in at least one of the block of cells being determined by the effective basis threshold A changing step of presetting its effective threshold voltage by instantaneously changing in the direction of the value level, and An amount to move its effective threshold voltage towards multiple effective threshold voltage levels, thereby setting at least one memory cell to one of a plurality of detectable states. The changing step and the address of any cell in at least one of the blocks of cells, said level being the desired effective threshold. Occurring without changing to a voltage level of a value, and wherein the setting step includes replacing any one of the cells addressed as described above with at least one of the auxiliary cells. A method that includes substituting in. 36. The method according to claim 35, wherein the method further comprises the step of separately storing a total number of preset numbers of blocks of individual cells. 37. The method according to claim 35, wherein the presetting step comprises changing an amount of charge on a floating gate of a memory flange in at least one of the blocks of cells, N in at least one block. Continuing until a valid threshold level other than the th cell reaches the effective base level, wherein the step of generating the address comprises generating the Nth address of the cell. 38. The method of claim 35, wherein establishing a plurality of effective threshold voltage levels comprises establishing at least four such threshold voltages. Method. 39. An array of electrically modifiable memory cells, wherein the array is divided into blocks of cells, the array having means for addressing individual cells within the block to read and change its state, The memory cell includes a field effect transistor having a separate floating gate, having a threshold voltage level, the level corresponding to a level at which there is no net charge retained on the floating gate. The net charge is variable and the step of operating the array includes the following steps: a plurality of effective threshold voltage levels greater than two corresponding to a plurality of detectable states of individual cells greater than two. Establishing and setting an effective threshold voltage level for each of the plurality of cells. Is addressed to one cell of the block at one of a plurality of levels, the amount of charge on each of the plurality of floating gates is determined by the effective threshold voltage of the cell. Varying and setting until substantially equal to one of the levels, wherein one of the plurality of states sets a state of the plurality of addressed cells; Appointing at least one block other than the one block as an auxiliary block, and replacing the ancillary block of cells with the one block, the plurality of cells in the ancillary block of cells are A replaceable step that is addressable to set a typical threshold voltage level to one of the plurality of levels. Law. 40. The method of claim 39, further comprising the step of monitoring a block of individual cells and detecting that one of the blocks of cells has reached a patience limit. Corresponding to, the method including initiating the step of replacing the auxiliary cell. 41. In an electrically modifiable memory cell array, the cells are divided into distinct blocks of cells, and the cells access individual cells within the block to read and change their state. The memory cell has a field effect transistor having a separate floating gate, the cell has a threshold voltage, and the level is a level provided when there is no net charge on the floating gate. In an array, the method of operating the array comprises the steps of: establishing a plurality of effective threshold voltage levels greater than 2, said levels being a plurality of detecting more than 2 individual cells. And a threshold level effective for each of a plurality of memory cells in one of the blocks. Set by changing the amount of charge on the floating gate of each of the cells to one of a plurality of effective threshold voltage levels until the effective threshold voltage is equal, thereby causing the plurality of cells to The states are individually set to one of the states, and the states of the memory cell are read to assist in error correction planning. 42. Means for addressing to read or change the state of individual cells in said block with an array of electrically changeable memory cells divided into blocks of cells, said memory cells comprising: Field effect transistors each having a floating gate, having a threshold voltage level provided when there is no net charge on the floating gate, the threshold voltage being the net voltage held by the floating gate. In a method of operating an array for an array that is modified by charge: a plurality of detectable programs of more than two at a plurality of execution threshold voltage levels and more than two individual cells. Establishing a corresponding one of the detected levels identified in the block. 1 executes the threshold voltage of at least one cell to perform threshold level is the address of the amount of charge of the floating gate of the addressed cell of the cell of said plurality of execution threshold voltage
Changing from a start level to one of a plurality of threshold voltages, the state of the addressed cell being equal to one of the plurality of programmed states. In the step of setting the execution threshold voltage to one, the execution threshold voltage of the addressed cell is sufficient to move from the starting level to one of the plurality of threshold voltage levels. Applying a constant voltage to the addressed cell for a predetermined time, and thereafter determining electrical parameters of the addressed cell, the execution threshold of the addressed cell being a plurality of thresholds. Reading to determine if one of the voltage levels has been reached, and a plurality of execution threshold voltages of the addressed cell. It said of the threshold voltage 1
The method comprises the steps of applying a voltage and repeating reading until it is detected that the two are set. 43. The method of claim 42, wherein the step of applying a voltage includes the applied voltage and the predetermined time for the execution threshold voltage of the addressed cell to be the plurality of effective voltages. A method comprising causing the change in the threshold voltage to be less than half between two adjacent ones. 44. The method of claim 42, wherein the step of reading electrically interrogates the addressed cell, while at the same time providing a resulting level of electrical parameters of the addressed cell of two or more. A method that is a step of comparing with a reference level at the same time. 45. The method of claim 42, further comprising at least one addressed one of said ones of said blocks.
Resetting the effective threshold voltage of cells in said at least one block to a preset level, which is the following step, prior to setting one effective threshold level: to cells in said at least one block. , Applying a given voltage to the cells in the at least one block in the direction of the preset level for a predetermined time sufficient to move to the effective threshold voltage, after which the at least one Reading the electrical parameter of the cells in the block to determine if the effective threshold voltage of the individual cells in the at least one block has reached the preset level; and Applying a voltage to a cell in at least one block to read its state, said at least Repeating until the running threshold voltage of cells in a block has reached the preset level. 46. The method of claim 45, wherein the preset level is substantially equal to one of the plurality of preset levels that corresponds to one of the detectable programmed states of the individual cells. 47. The method of claim 45, wherein cells in said at least one block are applied with said applied voltage and their thresholds are repeated when said applying and reading steps are repeated. How to continue while the value voltage rises. 48. The method of claim 45, wherein the step of reading the electrical parameter of a cell in the at least one block electrically interrogates a cell in the at least one block. A method of simultaneously comparing the obtained results of individual said electrical parameters of cells in a block with two or more reference levels. 49. The method of any of claims 42-48, wherein at least two of the plurality of effective threshold levels are due to a net positive charge on the floating gates of the individual cells. There is a way. 50. The method of any of claims 42-48, wherein the applied threshold level of the individual cells is at least 3 volts. 51. The method of any of claims 42-48, wherein the repeating application of voltage and reading while the effective threshold voltage level of the at least one addressed cell is set. A preset maximum number of repetitions of the voltage application and read steps is performed during a setting in which the effective threshold voltage level of the addressed set is not set to one of the plurality of threshold voltage levels. How to be terminated after waking up. 52. The method of any of claims 42-48, wherein the repeating of energizing and reading the at least one of the at least one of the at least one blocks during resetting of an effective threshold voltage level of a cell in the at least one block. A method that is terminated after a preset maximum number of voltage application and read iterations has occurred during a reset period without resetting the effective threshold voltage levels of some of the individual cells in the block. 53. A method according to any of claims 42 to 48, comprising the step of substituting an auxiliary good cell in the array in response to at least one addressed cell becoming defective. A method that further includes. 54. The method of any of claims 42-48, wherein in response to at least one addressed cell becoming defective, replacing a block of at least one auxiliary cell in the array. The method further comprising a step. 55. The method of any of claims 42-48, further comprising accumulating the total number of times at least one block of cells has been set.