JPH0729385A - Eeprom device - Google Patents

Abstract

PURPOSE:To provide an EEPROM whose reliability against the number of rewriting times and reduction of a power voltage is heightened by providing a variable resistance element functioning as a level shifting means on a reference voltage forming preamplifier. CONSTITUTION:A P channel type MOSFETQ 8 as the variable resistance element is provided on the drain side of the amplification MOSFETQ 7 of a preamplifier B for forming a reference voltage Vref, a grounding potential is given to a gate side and a power voltage VCC is supplied to a source side via a load MOSFETQ 9. Thus, when the voltage VCC is relatively high, as relatively large conductance is provided, the amount of level shifting by a drop in the voltage is made small and when the voltage VCC is reduced, the conductance is slightly changed and the amount of level shifting is increased. In this way, a level change is increased corresponding to the drop in the voltage VCC and the EEPROM whose reliability is heightened against the number of rewriting times and the power voltage reduction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an EEPROM (Electrical Erasable & Programmable Read
Only memory) devices, such as MNO
The present invention relates to a technique effectively applied to a device using an S transistor.

[0002]

2. Description of the Related Art A semiconductor nonvolatile memory element capable of electrically writing and erasing data, such as MNOS (Metal Nitride Oxide Semiconductor), is a relatively thin silicon oxide film and a relatively thin silicon oxide film formed thereon. Insulated gate field effect transistor (hereinafter, referred to as a gate insulating film having a double-layered gate insulating film with a thick silicon nitride film (nitride)
This is simply referred to as an MNOS transistor), and not only writing of stored information but also erasing can be performed electrically. M
The NOS technique is described in, for example, Japanese Patent Laid-Open No. 56-156370.

In the erased state or the state in which stored information is not written, the threshold voltage of the N-channel type MNOS transistor is a negative voltage. For writing or erasing stored information, a high electric field is applied to the gate insulating film so that carriers are injected by a tunnel phenomenon. According to the above publication, the MNOS transistor is
It is formed in a P-type well region formed in an N-type semiconductor substrate. In addition, the MOSFET forming the peripheral circuit is
It is formed in a well region independent of the well region for the S transistor.

In the write operation, for example, a ground potential of 0 V of the circuit is applied to the well region as the body gate of the MNOS transistor, and a high voltage for writing is applied to the gate. A low voltage of about 0 V or a high voltage of the write level is applied to the source region and the drain region depending on the information to be written. At this time MN
In the channel forming region of the OS transistor, that is, in the surface of the silicon region between the source region and the drain region, a channel is induced according to the positive high voltage of the gate. The potential of this channel becomes equal to the potential of the source region and the drain region. When the voltage of 0 V is applied to the source region and the drain region as described above, a high electric field corresponding to the high voltage of the gate acts on the gate insulating film.
As a result, electrons as carriers are injected from the channel into the gate insulating film by the tunnel phenomenon. As a result, the threshold voltage of the MNOS changes from a negative voltage to a positive voltage, for example.

When a write level high voltage is applied to the source region and the drain region, the potential difference between the gate and the channel is set to a small value. Such a small voltage difference is insufficient to cause injection of electrons due to the tunnel phenomenon. Therefore, the threshold voltage of MNOS does not change. In the case of erasing, a positive high voltage is applied to the well region serving as the body gate of the MNOS transistor while applying 0 V to the gate of the MNOS transistor to cause a tunneling phenomenon in the reverse direction and return electrons serving as carriers to the body gate. It is done by

[0006]

[Problems to be Solved by the Invention] MNOS as described above
Data is repeatedly rewritten in the transistor. By repeating such data rewriting, the threshold voltage Vth shifts to the high level side from about 10 ⁵ times. Further, in the MNOS transistor, its data retention characteristic approaches the initial threshold voltage (virgin level) with the passage of time. Therefore, due to the above-mentioned rewriting characteristics, particularly on the erasing side, if left for a long time, the current tends to decrease, and there is no margin with respect to the reference voltage, making discrimination difficult. Further, when the power supply voltage is low, the amplification characteristic of the preamplifier equivalently forming the reference voltage is deteriorated, and the read signal L on the low level side is approached to lose the operation margin.

An object of the present invention is to provide an EEPROM device which has high reliability against the number of times of rewriting and a decrease in power supply voltage. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, as a reference voltage of a read signal from a memory array configured by arranging memory cells including nonvolatile memory elements that are electrically writable and erasable in a matrix, a dummy cell including a nonvolatile memory element in an initial state is used. A variable resistance element whose resistance value is inversely proportional to the power supply voltage is provided between the drain of the amplification MOSFET receiving the read signal at the source and the load means.

[0009]

According to the above means, the high level of the reference voltage is biased by inserting the variable resistance element, and the level bias amount is increased in response to the decrease of the power supply voltage.
A level margin for the read voltage on the low level side can be secured when the threshold voltage of the storage element changes depending on the number of times of rewriting and the power supply voltage drops.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows a circuit diagram of essential parts of an embodiment of an EEPROM device according to the present invention. The EEPROM device of this embodiment has an address buffer (not shown) and an X
An address selection circuit including a decoder X-DCR and a Y decoder Y-DCR, a circuit that forms a voltage for a write / erase operation in response to an output signal and a control signal of the address selection circuit, and the control signal. It includes a control circuit CONT for controlling.

The EEPROM device is operated by a relatively low power supply voltage VCC such as + 5V supplied externally and a negative high voltage -Vpp such as -12V, although not particularly limited thereto. The X address decoder X-DCR and the like forming the selection circuit are formed by CMOS circuits. The CMOS circuit operates by being supplied with a relatively low power supply voltage VCC such as + 5V.
Therefore, the address decoders X-DCR and Y-DC
The level of the selection / non-selection signal formed by R is about + 5V, and the low level is about 0 of the ground potential of the circuit.
Set to V.

Although the element structure itself which constitutes the illustrated EEPROM device is not shown because it is not directly related to the present invention, its outline is as follows. That is, the entire illustrated device is formed on a semiconductor substrate made of N-type single crystal silicon. The MNOS transistor is
It is of N-channel type and is formed on a P-type well region or a P-type semiconductor region formed on the surface of the semiconductor substrate. The N-channel MOSFET is similarly formed on the P-type semiconductor region. P-channel type MOS
The FET is formed on the semiconductor substrate.

Although not particularly limited, one memory cell is composed of one MNOS transistor and two MOSFETs connected in series to it. In one memory cell, one MNOS transistor and two MOSFETs have a so-called stacked gate structure in which, for example, the gate electrodes of the MNOS transistor partially overlap with the gate electrodes of the two MOSFETs. . As a result, the size of the memory cell is reduced because the one MNOS transistor and the two MOSFETs forming the memory cell are substantially integrated.

Although not particularly limited, each memory cell is formed in a common well region. N channel M for constructing a CMOS circuit such as an X decoder and a Y decoder
The OSFET is formed in a P-type well region that is independent of the common P-type well region for each memory cell. In this structure, the N-type semiconductor substrate constitutes a common substrate gate for a plurality of P-channel MOSFETs formed thereon, and is set to the power supply voltage VCC level of the circuit. N channel M for forming a CMOS circuit
The well region as the substrate gate of the OSFET is maintained at the circuit ground potential of 0 volt.

In FIG. 2, the memory array M-ARY is shown.
Includes a plurality of memory cells arranged in a matrix. One memory cell is the MNOS transistor Q2
And an address selection MOS provided between the drain and the data line (bit line or digit line) D1
It is composed of an FET Q1 and, although not particularly limited, a separation MOSFET Q3 provided between the source of the MNOS transistor Q2 and a common source line. If the stacked gate structure as described above is adopted, M
A MOS is formed in the channel formation region of the NOS transistor Q2.
The channel forming regions of the FETs Q1 and Q3 are directly adjacent to each other. Therefore, MNOS transistor Q
It should be understood that the two drains and sources are terms for convenience.

The gates of the address selecting MOSFETs Q1 and the like of the memory cells arranged in the same row are commonly connected to the first word line W11, and M corresponding thereto is connected.
The gates of the NOS transistor Q2 and the like are connected to the second word line W
12 are commonly connected. Similarly, memory cell address selecting MOSFETs and MNs arranged in the same row
The gates of the OS transistors have the first word line W, respectively.
21 and W22 are commonly connected.

The drains of the address selecting MOSFETs Q1 and the like of the memory cells arranged in the same column are commonly connected to the data line D1. Similarly, the drains of the address selecting MOSFETs of the memory cells arranged in the other same column are commonly connected to the data line D2.
The separation MOSFET Q3 has a common source in each memory cell.

The memory array M-ARY of this embodiment is
It is operated by the following potentials. First, in the read operation, the potential Vw of the well region WELL1 in which the memory array M-ARY is formed is set to the low level which is equal to the ground potential 0 V of the circuit. Separation MOS
The control line (Vig) coupled to the gate of FET Q3 is driven high to approximately turn on these MOSFETs Q3, which is approximately equal to the supply voltage VCC.
The second word lines W12 to W22, which are respectively coupled to the gate electrodes of the MNOS transistors, have a potential substantially equal to the ground potential, that is, a high threshold voltage (positive) and a low threshold voltage (negative) of the MNOS transistor. The voltage between and.

A word line to be selected among the first word lines W11 to W21 is set to a selection level or a high level which is approximately equal to the power supply voltage VCC, and the remaining word lines, that is, non-selected word lines are almost set. It is set to a non-selection level or a low level that is equal to the ground potential. A sense current is supplied from a sense amplifier SA, which will be described later, to the data line to be selected among the data lines D1 and D2. If the MNOS transistor in the memory cell selected by the first word line has a low threshold voltage, that memory cell forms a current path for the data line to which it is coupled. If the MNOS transistor in the selected memory cell has a high threshold voltage, that memory cell will form substantially no current path. Therefore, the data read from the memory cell is performed by detecting the sense current.

The sense amplifier SA is the memory array M.
The read signal output to the common data line CD by -ARY addressing is referred to a reference voltage Vref formed by a reference voltage circuit using a dummy cell to determine high level / low level.

In the write operation, the well region WEL
L1 is brought to a negative high voltage equal to about -Vpp,
The control line (Vig) coupled to the gate electrode of the isolation MOSFET Q3 is set to a negative high potential so as to turn off the MOSFET Q3. First word line W11
Through W21 are set to a non-selection level or a low level which is almost equal to the ground potential. Second word line W12
One of the word lines W22 to W22 is set to a selection level approximately equal to the power supply voltage VCC, and the remaining second word line is set to a negative high voltage close to the voltage -Vpp. The data line is set to a high level almost equal to the power supply voltage VCC or a low level having a negative high voltage close to the negative voltage −Vpp, depending on the data to be written in the memory cell.

In the erase operation, the well region WELL1
Is set to an erase level or a high level approximately equal to the power supply voltage VCC. First word lines W11 to W
21 and the second word lines W12 to W22 are basically set at a level substantially equal to the power supply voltage VCC of the circuit and a voltage substantially equal to the voltage -Vpp, respectively, for erasing. However, according to this embodiment, although not particularly limited, the levels of the first and second word lines are determined so that the memory cells in each memory row can be erased. Of the first word lines W11 to W21, the first word line corresponding to the memory row that needs to be erased is set to an erase level that is approximately equal to the power supply voltage VCC so that the memory row that does not need to be erased. The corresponding first word line is brought to a non-erased level such as the ground potential of the circuit. Of the second word lines W12 to W22, the second word line corresponding to the first word line set to the erase level is set to the erase level substantially equal to the negative voltage -Vpp and set to the non-erase level. The second word line corresponding to the first word line corresponding to the first word line is set to a non-erasing level which is almost equal to the power supply voltage VCC.

According to this embodiment, each MN is applied by applying the power supply voltage VCC to the well region WELL1, that is, the body gate of the MNOS transistor as described above.
A configuration is adopted in which the information stored in the OS transistor is erased. On the other hand, N-channel MOS forming a CMOS circuit
The body gate of the FET needs to be at a potential such as 0 volts, independent of the body gate of the MNOS transistor. Therefore, as described above, the substrate gate of each memory cell, that is, the memory array M-ARY.
Is formed in the semiconductor region WELL1.
N-channel MOSF constituting peripheral circuits such as decoder
It is electrically isolated from the semiconductor region (well region) where ET is formed.

To enable partial erasing of the memory array M-ARY, individual memory cells are formed in independent well regions, or memory cells arranged in the same row or column are formed in a common well region. Can be formed. In this embodiment, as described above, the entire memory cell, that is, the memory array M-ARY is formed in one common well region WELL1.

The first and second word lines W11 and W2
1 and W12 to W22 are X decoder X-
Driven by DCR. The X decoder X-DCR is
Although not particularly limited, the memory array M-ARY is composed of a plurality of unit decoder circuits that are in one-to-one correspondence with the memory rows. One unit decoder circuit is, for example,
NOR gate circuit NOR that receives an address signal
1, a gate circuit G and a level conversion circuit LVC.

The gate circuit G transmits the output of the corresponding NOR gate circuit to the corresponding first word line at least during the read operation, and in the write operation regardless of the output of the corresponding NOR gate circuit. The word line is set to a level substantially equal to the ground potential of the circuit. According to this embodiment, in order to enable the selective erase operation described above, the gate circuit G outputs the output of the corresponding NOR gate circuit to the corresponding first word line not only during the read operation but also during the erase operation. Configured to communicate.

When the output of the NOR gate circuit corresponding to the level conversion circuit LVC is at the high level selection level during the write operation, the level conversion circuit LVC accordingly sets the second word line to the selection level approximately equal to the power supply voltage VCC, and the NOR gate. If the output of the circuit is a low level non-selection level, the second word line is correspondingly brought to a non-selection level substantially equal to the negative voltage -Vpp. In the erase operation, the level conversion circuit LVC also causes the second word line to have an erase selection level equal to approximately negative voltage −Vpp if the output of the NOR gate circuit corresponding thereto is at the high level selection level.
If the output of the NOR gate circuit is the low level non-selection level, the second word line is set to the erase non-selection level substantially equal to the power supply voltage VCC accordingly.

The gates of the separation MOSFET Q3 and the like have the control voltage Vig formed by the control voltage generation circuit Vig-G.
Are commonly coupled to the control lines supplied to the. The sources of the isolation MOSFET Q3 and the like are coupled to the ground potential of the circuit, although not particularly limited. MOSF for separation
The control voltage Vig supplied to the gate of ETQ3 is MNO
In a write operation to be described later to the S-transistor, the word line of the second word lines W21 to W22 to which the memory cell to be selected is coupled is set to the high level (5V), and the well region WEL as the body gate is formed.
L is set to about -12V and a data line such as D1
Is set to about -10V, it is set to a low potential such as about -10V so as to turn off the MOSFET Q3. As a result, even if the data line D2 is set to a high level such as + 5V, it is possible to prevent a current from flowing from the data line D2 to the memory cell side to which the writing is to be performed.

In the well region WELL1 in which the memory array M-ARY is formed, the control voltage generating circuit Vw-G is provided.
The control voltage Vw-G formed by is supplied. This voltage Vw is set to a negative high voltage such as about -12V during the write operation, set to a potential of about + 5V during the erase operation, and set to about 0V in other cases.

In this embodiment, the column switch MOSFETs Q12, Q12, etc. for selecting the data lines D1, D2 of the memory array M-ARY are not particularly limited in order to speed up the read operation, but are not particularly limited. , N-channel type. In this case, the data lines D1 and D2 and their N-channel MOSFET Q1
N-channel MOS that is electrically separated from 2, Q13, etc.
FETs Q10 and Q11 are provided. That is, between the data lines D1, D2, etc. and the common data line CD,
N-channel MOSF as the Y gate (column switch) circuit C-SW and the MOSFETs Q10, Q11, etc.
ETQ12, Q13 and the like are provided in series. MOSFET Q10, Q11 for separating the data line
Are formed in the same P-type well region WELL1 as the MNOS transistor.

The control voltage Vc formed by the control voltage generation circuit Vc-G is supplied to the gates of these MOSFETs Q10 and Q11. The control voltage Vc is set to a negative high voltage such as -12 V only in the write operation state, and is set to a high level like the power supply voltage VCC in the other read and erase operation states. As a result, the MOSFETs Q10 and Q11 are turned off in the write operation state. In addition, the MO
The SFETs Q10 and Q11 are turned off by setting the well region WELL1 to a high level like the power supply voltage VCC in the erase operation state. Therefore, the MOSFETs Q10 and Q11 are turned on only in the read operation state. As a result, during the write operation, the MOSFETs Q10, Q11, etc. are turned off, so that the column switch MOSFETs Q12, Q1 to be described later even if the potential of the data line is set to a negative high voltage.
The connection point with 3 is set in a floating state. Therefore, a switch MOSFET coupled to the interconnection point
It is possible to prevent the sources and drains of Q12 and Q13 and the well region in which they are formed from being forward biased.

The output signals of the Y decoder Y-DCR are supplied to the gates of the MOSFETs Q12 and Q13 which form the column switch circuit C-SW. Y decoder Y-
Each output of the DCR is brought to a selection level which is approximately equal to the power supply voltage VCC or a non-selection level which is approximately equal to 0 volt during a read operation.

The common data line CD is connected to the input / output circuit IO.
It is coupled to the output terminal of the data input circuit DIB forming B and the input terminal of the data output circuit DOB including the sense amplifier SA and the output buffer circuit OBC. The input terminal of the data input circuit and the output terminal of the data output circuit forming the input / output circuit IOB are coupled to the external terminal I / O.

According to this embodiment, each data line D1, D
2 is provided with a latch circuit FF for holding the previous storage information prior to erasing / writing, and selectively sets the potential of the data line to a negative high voltage in accordance with the storage information of the latch circuit FF during the write operation. A level conversion circuit LVC for setting -Vpp is provided. With these, it becomes possible to perform an automatic rewriting operation as will be described later and simultaneous writing of data to a plurality of memory cells coupled to one selected word line.

The control circuit CONT has external terminals CEB, W.
By receiving a chip enable signal, a write enable signal, an output enable signal supplied to EB and OEB, and a write voltage supplied to the external terminal -Vpp, various operation modes are discriminated, and a gate circuit G and a level conversion circuit are determined. It outputs various control signals for controlling the operation of circuits such as the LVC, the control voltage generation circuit Vig-G, the data input circuit DIB, and the data output circuit DOB.

The read operation mode is not particularly limited, but signals in the external terminals CEB, WEB and OEB (hereinafter,
Signal CEB, WEB, OEB), and the standby operation mode is instructed by the high level of the signal CE. The first write operation mode for writing data in the latch circuit FF of FIG. 2 is the signals CEB and WE.
The second write operation mode for writing the data in the memory cell is instructed by the low level, low level, high level and low level of B, OEB and Vpp.
It is instructed by the low level, low level, high level and high level of the signals CEB, WEB, OEB and Vpp. The erase operation mode is instructed only for a predetermined period when the second write operation mode is instructed.

According to this embodiment, various control signals output from the control circuit CONT are output in time series. The oscillator circuit OSC of FIG. 2 is operated by a power supply voltage VCC, such as +5 volts, applied between the external terminals VCC and GND of the EEPROM device. The oscillator circuit OSC may be controlled to operate only when a write voltage is applied to the terminal -Vpp, if necessary for low power consumption of the circuit.

When rewriting data, the first write mode is executed prior to the second write mode. That is, in the first write mode, the stored information of all the memory cells coupled to the addressed word line is once read and held in each latch circuit FF shown in FIG. Then, the data signal supplied from the external terminal is taken in by the latch circuit corresponding to the data line of the memory cell to be written. For example, if you want to rewrite all bits to the memory cells connected to the word line,
By sequentially switching the Y addresses, the write signals of a plurality of bits supplied from the external terminals are sequentially fetched by the corresponding latch circuits.

After that, the second write mode is carried out. The erasing operation of the MNOS transistors coupled to the word line is performed, and then the writing operation is simultaneously performed on the memory cells of one word line according to the information of the latch circuit FF. By the above operation, the write operation similar to that of the static RAM can be performed from the outside.

The dummy cell forming the reference voltage is a well region WELL in which the memory array M-ARY is formed.
1. An address selection MOSFET, a MNOS transistor and an isolation MOSFET and a switch MOSFET, which are formed in a well region different from that of 1 and are similar to the memory cell
It is composed of a series MOSFET circuit composed of switch MOSFETs corresponding to column switches. Above MNOS
The transistor is set to have the same size as the MNOS transistor of the memory cell and has the initial threshold voltage (virgin level). The gate of this MNOS transistor is coupled to the ground potential of the circuit. In addition, the gates of the other MOSFETs are supplied with the power supply voltage V as in the case where the memory cell is in the read state.
CC is supplied.

FIG. 1 shows a circuit diagram of an embodiment of the sense amplifier and a preamplifier provided at its input. The memory array M-ARY exemplarily shows an equivalent circuit when one memory cell is selected. That is, the isolation MOS that constitutes the memory cell as described above.
FET, MNOS transistor and MO for address selection
SFETs, switch MOSFETs, MOSFETs forming column switches, and the like are shown in series. The gates of these MOSFETs are supplied with a high level such as the power supply voltage VCC corresponding to the address selection operation.

On the other hand, the dummy cell is also composed of a circuit similar to the above memory cell. However, the MNOS corresponding to the memory cell is made to have an initial threshold voltage, and the ground potential of the circuit is constantly supplied to its gate.

The read signal of the common data line CD of the memory array M-ARY is input to the preamplifier A and the amplification operation is performed. The preamplifier A is provided with a limiter function for limiting the signal amplitude of the selected data line in addition to supplying the read current and amplifying the read signal.

If the MNOS transistor of the selected memory cell in the memory array M-ARY has a positive threshold voltage, no DC current path is formed between the common data line CD and the circuit ground. In this case, the common data line CD includes the MOSFET Q6 and the amplification MOSFET Q1.
And a relatively high level by the current supply from the load MOSFET Q2. The bias current is supplied from the bias circuit by turning on the MOSFET Q3 when the common data line CD reaches a predetermined potential and turning off the MOSFET Q6 by the drain output thereof.
The output voltage level-shifted by the ETQ4 also substantially turns off the amplification MOSFET Q1, so that it is substantially stopped. Therefore, the high level of the common data line CD is limited to a relatively low potential.

On the other hand, when the MNOS transistor of the selected memory cell in the memory array M-ARY has a negative threshold voltage, the column switch MOSFET is connected between the common data line CD and the circuit ground point. , A data line and a selected memory cell form a direct current path. Therefore, the common data line CD tends to become a low level such as the ground potential of the circuit due to the above DC current path. However, if the potential of the common data line CD drops below the threshold voltage of the MOSFET Q3,
The MOSFET Q3 is turned off and the drain side voltage is increased to increase the gate voltage of the MOSFET Q6 and the amplification MOSFET Q1. As a result, the low level of the common data line CD is limited to a relatively high potential.

Such MOSFETs Q3, Q4 and Q
5, an inverting amplifier circuit, a bias current supply MOSFET Q6 controlled by an output signal thereof, and an amplifier M
The amplitude limitation between the high level and the low level of the common data line CD by the OSFET Q1 brings the following advantages. That is, it is possible to increase the reading speed regardless of whether the common data line CD or the like has a capacitance such as a stray capacitance that limits the signal change speed. In other words, in the case where data from a plurality of memory cells are sequentially read, it is possible to shorten the time until one level of the common data line CD is changed to the other level.

The preamplifier B that forms the reference voltage Vref is also composed of the same circuit as described above. However, the threshold voltage of the MNOS transistor as described above secures a margin with the reference voltage due to a current decrease due to a long time left on the erasing side with the passage of time, and the reference voltage side due to the decrease of the power supply voltage VCC. In order to secure a margin on the low level side due to the deterioration of the amplification characteristic of the preamplifier, the drain side of the amplification MOSFET Q7 acts as a level shift means and a P-channel type MOS as a variable resistance element.
An FET Q8 is provided.

MOSF acting as the variable resistance element
The ground potential of the circuit is constantly applied to the gate of the ETQ8, and the power supply voltage VCC is supplied to the source side via the load MOSFET Q9. Therefore, the power supply voltage VCC
When is relatively high, it has a relatively large conductance, so the level shift amount due to the voltage drop is small. On the other hand, as the power supply voltage VCC decreases, the voltage between the gate and the source decreases, so that the conductance changes. As a result, the level shift amount due to the voltage drop increases.

FIG. 3 is a characteristic diagram showing the relationship between the power supply voltage of the preamplifier B and the output level. When the MOSFET Q8 as the variable resistance element as described above is inserted, the deviation amount of the reference voltage Vref increases as the power supply voltage decreases, and the high level H from the preamplifier A is increased.
With this, it is possible to secure a sufficient margin for the read signal of the low level L. That is, the MO as described above
When the SFET Q8 is not inserted, it is possible to prevent the potential from becoming the same as the low level L due to the decrease in the amplification factor accompanying the decrease in the power supply voltage VCC like the reference voltage Vref 'shown by the solid line in the figure.

In the above preamplifiers A and B,
The signal PAC is a timing signal for activating the preamplifier. When the signal PAC is set to the low level, the P-channel MOSFETs Q5 and Q12 are turned on and the N-channel MOSFETs Q7 and Q14 are turned off to activate the preamplifier. Done. Also, the signal PAC
Is high level, the P-channel type MOSF
When the ETQ5 and Q12 are turned off to cut off the operating current of the inverting amplifier circuit, the N-channel MOSF
Depending on the ON state of ETQ7 and Q14, amplification MOSFE
Each of TQ1 and Q7 is turned off.

The functions and effects obtained from the above embodiment are as follows. That is, (1) the nonvolatile memory element in the initial state is included as a reference voltage of a read signal from a memory array configured by arranging memory cells including a nonvolatile memory element capable of electrically writing and erasing. By providing a variable resistance element whose resistance value is changed in inverse proportion to the power supply voltage between the drain of the amplification MOSFET receiving the read signal from the dummy cell at its source and the load means, the high level of the reference voltage is biased. Moreover, since the level deviation amount is increased corresponding to the decrease in the power supply voltage, it is possible to secure a level margin for the read voltage on the low level side when the threshold voltage of the storage element changes due to the number of rewrites and the power supply voltage decreases. The effect is obtained.

(2) By the above (1), it is possible to obtain an effect that an EEPROM device having a highly reliable data holding characteristic can be obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example,
In the preamplifier B, the size of the load MOSFET Q9 may be set to be relatively large, and the output level as the reference voltage Vref may be biased to the high level side in relation to the amplification MOSFET Q7. Further, in the memory cell, the isolation MOSFET Q3 is omitted, and
The source of the OS transistor may be connected to the reference potential line. In this case, the reference potential line is set to a floating state at the time of write operation, and the ground potential of the circuit is given at the time of read and erase operations. For example, the control line can be written / erased as described above. It is said that The write / erase method for the MNOS transistor may be any method as long as the well potential and the potential relationship between the data line and the word line are relatively changed as described above.

The electrically writable / erasable memory element may be of the FLOTOX (floating gate tunnel oxide) type. When such a memory element is used, a control voltage according to the write / erase operation is supplied. The EEPROM device may be incorporated in a semiconductor integrated circuit device such as a one-chip microcomputer.

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the read signal from the dummy cell including the nonvolatile memory element in the initial state is used as the reference voltage of the read signal from the memory array in which the memory cells including the electrically writable and erasable nonvolatile memory elements are arranged in a matrix. Amplified MO that receives at the source
By providing a variable resistance element whose resistance value is changed in inverse proportion to the power supply voltage between the drain of the SFET and the load means, the high level of the reference voltage is biased, and moreover the power supply voltage is reduced. Since the amount of level deviation becomes large, it is possible to secure a level margin for the read voltage on the low level side when the threshold voltage of the memory element changes due to the number of rewrites and the power supply voltage drops.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a preamplifier according to the present invention.

FIG. 2 is a main part circuit diagram showing an embodiment of an EEPROM device according to the present invention.

FIG. 3 is a characteristic diagram for explaining the operation of the preamplifier according to the present invention.

[Explanation of symbols]

M-ARY ... Memory array, X-DCR ... X decoder,
Y-DCR ... Y decoder, C-SW ... column switch,
LVC ... Level conversion circuit, FF ... Latch circuit, G ... Gate circuit, Vig-G, Vw-G, Vc-G ... Control voltage generation circuit, SA ... Sense amplifier, OBC ... Output circuit, DOB
... Data output circuit, DIB ... Data input circuit, WELL
1, WELL2, WELL3 ... Well region, OSC ... Oscillation circuit, TG ... Timing generation circuit, COUNT ... Count unit, MNOS ... Storage circuit, FF0-FF1 ... Flip-flop circuit, RWC ... Control circuit, VG1, VG2 ... Voltage generation circuit

Front Page Continuation (72) Inventor Yasunori Ikeda 5-201-1, Josui Honcho, Kodaira-shi, Tokyo Within Hitate Cho-LS Engineering Co., Ltd. (72) Inventor Yoshikazu Nagai, Josui, Kodaira-shi, Tokyo 5-20-1 Honcho Super RLS Engineering Co., Ltd. (72) Inventor Shigeru Nakajima 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Super CLS Engineering Co., Ltd. Incorporated (72) Inventor Kazunori Furusawa 5-201-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Incorporated company Hitachi Ltd. Semiconductor Division

Claims (3)

[Claims] 1. A memory array configured by arranging memory cells including nonvolatile memory elements that can be electrically written and erased in a matrix, a dummy cell including nonvolatile memory elements in an initial state, and a dummy cell from the dummy cells. From a memory array, a reference voltage preamplifier including a variable resistance element whose resistance value is inversely proportional to the power supply voltage between load means or load means provided on the drain side of an amplification MOSFET receiving a read signal at its source, An amplifier MOSFET that receives the read signal of the above at its source and a read preamplifier including load means provided at its drain,
An EEPROM device comprising a differential type sense amplifier that receives the output signals of the reference and read preamplifiers. 2. The reference voltage preamplifier and the read preamplifier are such that the output signals of the inverting amplifier circuits that receive the respective input signals are supplied to the gates of the corresponding amplification MOSFETs. Item 1. An EEPROM device. 3. The variable resistance element is a P-channel type MOSFE whose gate is constantly supplied with the ground potential of the circuit.
An EEPROM device according to claim 1 or 2, characterized in that it comprises a T.