JPS6329397A - Eeprom device - Google Patents

Abstract

PURPOSE:To prevent the reduction in the level margin by switching a reference voltage fed to a differential type sense amplifier to a level according to a read signal level changed in response to number of times of writing to a memory cell. CONSTITUTION:A sense amplifier SA discriminates a high/low level for a read signal outputted to a common data line CD by the addressing of a memory array M-ARY while referencing the reference voltage of a voltage generating circuit. In case of lots of rewriting number of times to a MNOS transistor, a voltage generating circuit forming two reference voltages where a threshold voltage is shifted toward the high level is provided. One is used for a reference voltage forming when number of times of rewriting is comparatively less and the other is used to form a reference voltage when number of times of rewriting exceeds a prescribed number of times, and a switching signal S is supplied to a gate of a switch MOSFETQ17 corresponding to a column switch from the counter circuit. Thus, the reference voltage attended with the rewriting number of times is switched and the operating margin is improved and the desired data storage characteristic is obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to EEPROM (Electrically Erasable Programmable Read Only Memory)
The present invention relates to devices, and relates to techniques that are effective for use in devices that use MNOS transistors, for example.

[Conventional technology]

Semiconductor non-volatile memory elements, such as MNOS (Metal Nitride Oxide Semiconductor), in which data can be written and erased electrically, consist of a relatively thin silicon oxide film and a relatively thick silicon nitride film formed thereon. Insulated gate field effect transistor (hereinafter simply referred to as MNO) has a two-layer gate insulation/film structure with
(referred to as an S transistor), and can electrically write and erase stored information. The MNO3 technology is based on, for example, Japanese Patent Application Laid-Open No. 156370/1983.

In an erased state or a state in which no stored information is written, the threshold voltage of the N-channel MNO3 transistor is a negative voltage. In order to write or erase stored information, a high electric field is applied to the gate insulating film so that carrier injection occurs due to a tunneling phenomenon.

According to the above publication, the MNOS transistor is formed in a P-type well region formed in an N-type semiconductor substrate. Furthermore, MOSFETs constituting the peripheral circuit are formed in a well region that is independent of the well region for the MNOS transistor.

In a write operation, for example, a ground potential O■ of a digging circuit is applied to the well region serving as the base gate of the MNoS transistor, and a high voltage for writing is applied to the gate. Depending on the information to be written, a low voltage of 0.0 cm or a high voltage of the write level is applied to the source region and the drain region. At this time, a channel is induced in the channel forming region of the MNoS transistor, that is, on the surface of the silicon region between the source region and the drain region, in response to the positive high voltage of the gate. The potential of this channel becomes equal to the potential of the source and drain regions. When a voltage of 0 is applied to the source region and the drain region as described above, a high electric field corresponding to the high voltage of the gate acts on the gate insulating film. As a result, electrons as carriers are injected from the channel into the gate insulating film due to a tunneling phenomenon. This allows MNoS
The threshold voltage changes, for example, from a negative voltage to a positive voltage.

When a high voltage at a write level is applied to the source region and the drain region, the potential difference between the gate and the channel is reduced to a small value. Such a small voltage difference is insufficient to cause electron injection by tunneling. Therefore, the threshold voltage of MNO3 does not change.

In addition, in the case of erasing, a positive high voltage is applied to the well region serving as the substrate gate while applying 0 to the gate of the MNoS transistor to cause a tunneling phenomenon in the reverse direction and transfer electrons as carriers to the substrate. This is done by returning it to the gate.

[Problem that the invention seeks to solve]

In the MNoS transistor as described above, data is repeatedly rewritten. By repeating such data rewriting, the threshold voltage vth shifts to the high level side after about 10 seconds, as shown in the characteristic diagram shown in FIG. Also, MNO3I
- For transistors, their data retention characteristics are
As shown in the figure, as time T passes, a point IN appears in the same figure.
As shown by the line, it approaches the initial threshold voltage (virgin level). Therefore, due to the rewriting characteristics shown in Figure 3 above, the written information becomes high level as shown by the dotted line in Figure 4. If we consider the case where the voltage is erected, the level margin on the low level side may be reduced and malfunction may occur.

An object of the present invention is to provide an EEFROM device that has high reliability with respect to the number of rewrites.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the read reference voltage of a memory array constituted by a matrix arrangement of memory cells each including a semi-destructive non-volatile memory element capable of writing and erasing and a MOSFET for address selection is set to the threshold value of the memory element. When the number of rewrites that cause the voltage to change reaches a predetermined number, the level is switched to a corresponding level.

[For production]

According to the above-described means, the read reference voltage is switched according to the threshold voltage of the storage element depending on the number of rewrites, so that a desired level margin can be ensured.

〔Example〕

FIG. 1 shows a circuit diagram of a main part of an embodiment of an EEPROM device according to the present invention.

The EEPROM device of this embodiment includes an address buffer (not shown), an X decoder X-DCR, and a Y decoder Y-D.
It includes an address selection circuit consisting of a CR, a circuit for forming voltages for write/erase operations in response to output signals and control signals of the address selection circuit, and a control circuit C0NT for forming the control signals.

Although not particularly limited, the EEFROM device has a relatively low power supply voltage Vcc, such as +5■ supplied from the outside, and
It is operated by a high negative voltage -vpp, such as -12v. X7 dress decoder X- that constitutes the above selection circuit
The DCR and the like are composed of CMO3 circuits. CMO3
The circuit operates by being supplied with a relatively low power supply voltage Vcc, such as +5V. therefore,
The level of the selection/non-selection signal formed by address decoders X-DCR and Y-DCR is set to +5V, and the low level is set to 0, which is the ground potential of the circuit.

Although the element structure itself constituting the illustrated EEPROM device is not shown because it is not directly related to the present invention, its outline is as follows.

That is, the entire device shown is formed on a semi-quartet substrate, such as one made of N-type single crystal silicon.

The MNOS transistor is an N-channel type, and is formed on a P-type well region or a P-type semiconductor region formed on the surface of the semiconductor substrate. An N-channel MO3FET is similarly formed on the P-type semiconductor region.

A P-channel type MOS FET is formed on the semi-dedicated substrate.

One memory cell can be one MN, although it is not particularly limited.
OS transistor and two MOs connected in series with it
It is composed of SFET. In one memory cell, one MNOS transistor and two MOS F
ET has a so-called stacked gate structure in which, for example, a part of the gate electrode of each of the two MOS FETs is overlamped with respect to the gate electrode of the MNOS transistor. As a result, the size of the memory cell is reduced to one MNOS transistor and two
The two MOS FETs are substantially integrated into one structure, resulting in miniaturization.

Although not particularly limited, each memory cell is formed in a common well region. CM like X decoder, Y decoder
N-channel MOS F E for configuring the O3 circuit
T is formed in an independent P-type well region with respect to a common P-type well region for each memory cell.

In this structure, the N-type semiconductor substrate constitutes a common base gate for a plurality of P-channel MO3FETs formed thereon, and is set to the power supply voltage Vcc level of the circuit. N-channel MO for configuring CMO3 circuit
The well region as the base gate of S F E T is maintained at circuit ground potential of 0 volts.

In FIG. 1, memory array M-ARY includes a plurality of memory cells arranged in a matrix. One memory cell consists of an MNOS transistor Q2 and an address selection MO3F provided between its drain and data vA (bit line or digital shift vA) DI.
ETQI, and an isolation MO3FET Q3 provided between the source of the MNO3 transistor Q2 and the common source line, although this is not particularly limited. Note that when the stacked gate structure as described above is adopted, MN
MOSF in the channel formation region of OS transistor Q2
The channel forming regions of ETQI and Q3 are directly adjacent to each other. Therefore, MNOS transistor Q2
The drain and source of are understood to be terms of convenience.

The gates of the address selection MOSFETQ1, etc. of the memory cells arranged in the same row are connected to the first word &1.
The gates of the MNOS transistors Q2 and the like which are commonly connected to W11 and correspond to it are commonly connected to the second word 6gtv12. Similarly, other memory cell address selection MOS FETs and MNOs arranged in the same row
The gates of the S transistors are connected to the first word line W2, respectively.
1. Commonly connected to W22.

MO for selecting addresses of memory cells arranged in the same column
The drains of the 3FETQ1 and the like are commonly connected to the data line iD1. Similarly, the drains of the address selection MO3FETs of other memory cells arranged in the same column are commonly connected to the data line D2. The source of isolation MOSFET Q3 in each memory cell is made common.

The memory play M-ARY of this embodiment is operated by the following potential.

First, in a read operation, memory array M-ARY
The potential Vw of the well region WELLI where is formed is set to a low level equal to the ground potential of the circuit, 0 volts.
The control line (Vig) coupled to the gate of the isolation MO3FETQ:M is set to a high level equal to the power supply voltage Vcc to turn on these MO3FETQ3. second word lines W12 to W22 each coupled to the gate electrode of the MNOS transistor;
is a potential such that is equal to the ground potential, that is, MNO
The voltage is between the high threshold voltage (positive) and the low threshold voltage (negative) of the S transistor. The word line to be selected among the first word lines Wll to W21 is set to a selection level or high level equal to the power supply voltage Vcc, and the remaining word lines, that is, unselected word lines, are
is set to a non-select level or low level equal to y' ground potential. A sense current is supplied from a sense amplifier SA, which will be described later, to the data line to be selected from among the data line wires D2. If the MNOS transistor in the memory cell selected by the first word line has a low threshold voltage, then that memory cell: forms a current path to the data line to which it is coupled; If the MNOS transistor in a selected memory cell has a high threshold voltage, that memory cell forms substantially no current path. Therefore, reading data from a memory cell is performed by detecting a sense current.

The sense amplifier SA determines whether the read signal outputted to the common data line CD by addressing the memory array M-ARY is high level or low level by referring to a reference voltage Vref formed by a voltage generation circuit as described later. I do.

In a write operation, the well region WELLI is
'-Vpp, and the separating M
The control line (Vi
g) are brought to a negative high potential to turn off their MO3FETs Q3.

The first word lines W11 to W21 are set to a non-select level or low level equal to the ground potential.

One of the second word lines W12 to W22 is connected to a solenoid if! The remaining second word glands are brought to a selection level equal to the voltage Vcc, and the voltage -VI'lp
A negative high voltage close to . Depending on the data to be written into the memory cell, the data line is connected to the power supply voltage VC.
High level or negative voltage equal to C -V11+
) is set to a low level with a negative high voltage close to .

In the erase operation, well region WELLI is set to an erase level equal to N' power supply voltage VCC or to a high level. The first word lines Wll to W21 and the second words 1W12 to W22 are basically brought to a level approximately equal to the power supply voltage Vcc of the circuit and to a level substantially equal to the voltage -vpp, respectively, for erasing.

However, according to this embodiment, the levels of the first and second word lines are determined so that erasing of memory cells in each memory row is possible, although this is not particularly limited. Among the first word lines Wll to W21, the first word line corresponding to the memory row that needs to be erased is set to an erase level equal to X' power supply voltage VCC, and the memory row that does not need to be erased The first word line corresponding to is set to a non-erasing level, such as the ground potential of the circuit. The second word line of the second words KW L 2 to W22 corresponding to the first word line set to the erase level is set to an erase level equal to the negative voltage - pp, and the second word line corresponding to the first word line set to the erase level is set to the erase level equal to The second word line corresponding to the first word line which is to be erased is set to a non-erasing level such that y' is equal to the power supply voltage Vcc.

According to this embodiment, as described above, the well region WELL
A configuration is adopted in which information stored in each MNO3 transistor is erased by applying a power supply voltage Vcc to I, that is, to the base gate of the MNOS transistor. On the other hand, 0M0
N-chi that makes up 3 circuits? The body gate of the channel MO8FET is required to be brought to a potential, such as O volts, independently of the body gate of the MNOS transistor.

Therefore, as described above, the semiconductor region WELLI in which the base gate of each memory cell, that is, the memory array M-ARY is formed, is a semiconductor region in which N-channel MO3FETs constituting peripheral circuits such as an X decoder and a Y decoder are formed. electrically isolated from the well region.

If you want to enable partial erasure of the memory array M-ARY, you can form each memory cell in an independent well region, or form memory cells arranged in the same row or column in a common well region. You can do it. In this embodiment, the entire memory cell, ie, the memory array M-ARY, is formed in one common well region WELL1, as described above.

The first and second word lines Wll to W21 and W12
to W22 are each driven by an X decoder X-0CR. Although not particularly limited, the X-decoder X-DCR consists of a plurality of unit decoder circuits in one-to-one correspondence with the memory rows of the memory array M-ARY. One unit decoder circuit is composed of, for example, a NOR gate circuit N0R1 that receives an address signal, a gate circuit G, and a level conversion circuit LVC as shown in the figure.

The gate circuit G has a small
The output of the corresponding NOR gate circuit is
The first word line is transmitted to the word line, and the first word line is made to have a level substantially equal to the ground potential of the circuit in a write operation, regardless of the output of the corresponding NOR gate circuit. According to this embodiment, in order to enable the selective erase operation described above, the gate circuit G connects the output of the corresponding NOR gate circuit to the corresponding first word line during the read operation as well as during the erase operation. configured to transmit.

During a write operation, if the output of the corresponding NOR gate circuit is at a high selection level, the level conversion circuit LVC changes the second word line to a selection level equal to the source voltage VCC in response to the output of the NOR gate circuit. If the output of the circuit is a low non-selection level, the second
The word line is brought to a non-select level equal to a negative voltage -Vpp. During the erase operation, the level conversion circuit LVC also changes the second word line to Y if the output of the corresponding NOR gate circuit is at a high selection level.
゛Negative voltage - Vl) Set to an erase selection level equal to Gl,
If the output of the NOR gate circuit is at a low non-selection level, the second word line is accordingly brought to an erase non-selection level equal to the power supply voltage Vcc.

The gates of the isolation MO3FETQ3 and the like are commonly coupled to a control line to which a control voltage ig generated by a control voltage generation circuit Vil-G is supplied. These separation MOS
Sources such as F ETQ 3 are not particularly limited, but
Coupled to circuit ground potential.

Control voltage Vi supplied to the separation MO3FETQ3
(H means that in the write operation of the MNOS transistor as described later, the word line to which the memory cell to be selected among the second word lines W21 and W22 is connected is set to high level (5■), and the base gate is When the well region WELL of the MO3FE is set to about -12 Å and the data line Dl is set to about -10 Å, the MO3FE
A low potential, such as about -10V, is applied to turn TQ3 off. As a result, even if the data line D2 is +5
Even if it is set to a high level as shown in (2), current is prevented from flowing from the data line D2 to the memory cell to which the above writing is to be performed.

Well region WE where the memory array MARY is formed
The LLI is supplied with a control voltage Vw-G generated by a control B'H voltage generation circuit Vw-G. This voltage Vw is a negative high voltage such as about -12V during a write operation. It is set to a potential of about +5V during an erase operation, and set to a potential of about 0V at other times.

In this embodiment, in order to speed up the read operation,
Although not particularly limited, each data %iD1. of the memory array M-ARY. Column switch MO3FE to select D2
TQI 2. Ql 2 etc. are of N-channel type.

In this case, N-channel MOSFETs QIO, Ql 1 are provided to electrically isolate each of the data lines Di, D2 and these N-channel MO3FETs Q12, Ql3, etc.

That is, the MO3FET QI O is provided between each of the data lines DI, D2, etc. and the common data line CD.

Qll, etc. and an N-channel MO5FET QI2°Q13 as a Y gate (column switch) circuit C-5W are provided in series, respectively. The data line isolation MOSFETs QI O and Ql 1 are formed in the same P-type well region W E L L as the MNO3 transistor. The gates of these MOSFETs QIO and Qll are connected to a control circuit formed by a control voltage generation circuit Vc-G.
A 4B voltage Vc is supplied. This control voltage Vc is set to a negative high voltage such as -12V only in the write operation state, and is set to a high level such as the 1its voltage Vcc during other read and erase operation states.

As a result, the above MOS FET Q 10
, Q11 are turned off during the write operation state. Furthermore, the MO3FETs QI O and Ql 1 are turned off when the well region W E L L is set to a high level such as the power supply voltage Vcc during the erase operation state. Therefore, &10SFETQ1 above
0, Qll is turned on only during the read operation state. As a result, during a write operation, the above M
Since OS FET Q10, Q11, etc. are turned off, even if the potential of the data line is set to a negative high voltage, the column switch MOS FETQ1, which will be described later,
2. The connection point with Ql3 is placed in a floating state.

This allows the switch MO coupled to the above interconnection point to
3FETQI 2. It is possible to prevent the source and drain of Ql 3 and the well region in which they are formed from being forward biased.

MOSFE constituting the above column switch circuit C-5W
TQI 2. , Ql 3 has a Y-decoder Y-
The output signal of the DCR is supplied. Y-decoder Y-DCR
During the read operation, each output of y゛power supply voltage V
The selection level is made equal to cc or the non-selection level is made equal to y□volts.

The common data line CD is connected to the output terminal of the data input circuit DIB constituting the input/output circuit IOB and the sense amplifier SA.
and an output sofa circuit OBC.
It is coupled to the input terminal of OB. This input/output circuit I
The input terminal of the data input circuit and the output terminal of the data output circuit constituting OB are coupled to external terminal I10.

According to this embodiment, each data line Di, D2 is provided with a latch circuit FF for holding previous storage information prior to erasing/writing, and selection is made according to the storage information of the latch circuit FF during write operation. A level converter circuit LVC is provided which changes the potential of the data line to a negative high voltage -Vl)P. These enable an automatic rewriting operation as described below and simultaneous writing of data into a plurality of memory cells coupled to one selected word line.

The control circuit C0NT receives a chip enable signal, a write enable signal, and a write enable signal supplied to external terminals CE, WE, and OE.
Various operation modes are determined by receiving the output enable signal and the input voltage supplied to the external terminal vpp, and the gate circuit G and level conversion circuit LVC
1 control l voltage generation circuit Vig-G, data input circuit DI
B. Various controls for controlling the operation of circuits such as the data output circuit DOB? Output No. 118.

Although not particularly limited, the read operation mode is indicated by a low level and a high level, and the standby operation mode is indicated by a high level of the signal CE. The first write operation mode for writing data into the latch circuit FF shown in FIG.
It is indicated by the low level, low level, high level, and high level of WE, OE, and Vpp.

The erase operation mode is instructed for a predetermined period when the second write operation mode is instructed.

According to this embodiment, various control signals output from the control circuit C0NT are output in time series. The oscillator circuit OSC of FIG. 1 is operated by a power supply voltage Vcc, such as +5 volts, applied between the external terminal Vcc of the EEPROM device and GND. In addition, the oscillation circuit ○SC is
If necessary for low power consumption of the circuit, for example terminal vpp
It may be controlled so that it operates only when a write voltage is applied to it.

When rewriting data, the first write mode is executed prior to the second write mode. That is,
In the first write mode, the stored information of all the memory cells coupled to the addressed word line is once read out and held in each launch circuit FF shown in FIG. 1.

Then, the data signal supplied from the external terminal is taken into the launch circuit corresponding to the data line of the memory cell to be written. For example, when rewriting all bits of a memory cell connected to a word line, the Y address is sequentially switched, so that a write signal consisting of multiple bits supplied from an external terminal is sent to each corresponding latch. sequentially incorporated into the circuit.

After this, the second write mode is implemented.

An erase operation of the MNOS transistor coupled to the word line is performed, and then a write operation is performed on the memory cells for one word line all at once according to the information of the launch circuit FF. By operation, a write operation similar to that of a static RAM can be performed from the outside.

In this embodiment, when the MNO3 transistor is rewritten many times, the threshold voltage shifts to the high level side, so a voltage generation circuit is provided to generate the following two reference voltages.

One circuit for forming the above-mentioned reference voltage is for forming a reference voltage when the number of rewrites is relatively small, and is provided in the well region W where the memory array M-ARY is formed.
MO3FETQ4, M for address selection similar to a memory cell is formed in a well region WELL2 different from ELLI.
Nos transistor Q5 and isolation MOS FETQ
6, switch MO3FETQ14, and switch MOS FETQ l corresponding to the column switch.
Consists of 6. The MNOS transistor Q5 is set to the same size as the MNOS transistor Q2 of the memory cell, and is made to have the above-mentioned initial threshold voltage. The gate of this MNOS I-transistor Q5 is coupled to circuit ground potential. Further, the power supply voltage Vcc is supplied to the gates of MO3FETQ4 and Q6 and MO3FETQI4, respectively, in the same manner as when the memory cell is in the read state. In addition, the above switch M
The gate of the O3FET QI 6 is supplied with an output signal of an inverter circuit N1 that receives a switching signal S from a counting circuit, which will be described later.

Another circuit for forming the reference voltage is for forming a reference voltage when the number of rewrites exceeds a predetermined number, and is formed in the well region WELL2,
MO3FETQ for address selection similar to the above memory cell
7, MNOS) U7 resistor Q8 and isolation MO3FET
Q9, a switch MO3FETI 5, and a switch MO3FET Q17 corresponding to a column switch. Since the MNO3 transistor Q8 forms a reference voltage shifted to the high level side, it is set to have a smaller size (smaller conductance) than the MNOs transistor Q2 of the memory cell, although it is not particularly limited. It is made to have a threshold voltage.

The gate of this MNOS transistor Q8 is coupled to the ground potential of the circuit. Also, MO3FETQ? The power supply voltage Vcc is supplied to the gates of Q9, MO3F, and ETQ15, respectively, in the same way as when the memory cells are in the read state. In addition, the above switch MO3FE
A switching signal S from a counting circuit, which will be described later, is supplied to the gate of TQ17.

The counting circuit includes a counting section C0UNT and a memory section MNO8, and the output signal of the most significant bit of the counting section is sent out as the signal S. The counting section 0UNT is composed of a binary counting circuit as described later, and is an 18-bit binary counter circuit in order to perform counting operations, for example, about 10' times.

When the counting circuit is powered on, the memory circuit M
The count storage information of No. 3 is read into the number section C0UNT as an initial value. Then, when a write operation is started in which the write enable signal WE is set to a low level, it is counted and the counting result is written into the memory circuit MNO3 again.

As a result, when rewriting is performed approximately 130,000 times (2"), the final focus output S changes from low level to high level, switch MO8FETQ16 turns off, switch FviO3FETQ17 turns on, and MNO
The reference voltage shifted to the high level side formed by the S transistor Q8 is supplied to the sense amplifier SA.

As a result, MNO of the memory array M-ARY is
Since the reference voltage can be switched in accordance with the shift of the threshold voltage due to the number of times of rewriting (erasing/writing) to the S transistor, it is possible to improve the operating margin and obtain desired data retention characteristics.

FIG. 2 shows a circuit diagram of a specific embodiment of the counting circuit.

The memory circuit MNOS and the counting unit C0UNT are basically the same as the latch FF circuits coupled to the memory array M-ARY and its data line. However, the flip-flop circuits FFO or FFI constituting the counting section C0UNT are different from mere launch circuits, and are composed of, for example, master slice type flip-flop circuits.
are connected in cascade to perform the binary counting operation described above.

The memory cells constituting the memory circuit MNO3 are formed in an independent well region WELL3, and instead of the decoder circuit XDCR, a control signal is generated by a control circuit RWC, and a voltage Vcg is generated by voltage generation circuits VG1 and VO2. , Vcw controls reading, writing, and erasing.

When the voltage XS is supplied to the EEPROM device, the control circuit RWC and the voltage generation circuits VGI and VO2 operate as follows.
The same voltage as in the read mode of the memory array M-ARY as described above is supplied to the memory cells. As a result, the previous count storage information is stored in the flip-flop circuits FFO and FFO.
It is taken into FI and its initial value is set. Thereafter, when the write enable Lt signal W E is set to a low level, the counting unit COUNT performs a +1 counting operation, and at the same time, the control circuit RWC instructs the storage circuit to enter the erase mode. At the end of this erase mode, the memory circuit MNO3 is put into the write mode and the +
A write operation of the count output that has been set to 1 is performed. Such a write operation to the memory circuit is performed only in the first write operation mode after power is turned on. After this, even if the write enable signal WE is set to low level again, the above-mentioned counting contents are not rewritten. This is because data is rarely rewritten multiple times to the same memory cell. It is.

The effects obtained from the above examples are as follows. That is, (1) The read reference voltage of a memory array constituted by a matrix arrangement of memory cells including writeable and erasable semiconductor non-volatile memory elements and address selection MOSFETs is determined by setting the read reference voltage to the threshold value of the memory element. When the number of rewrites that cause the voltage to change reaches a predetermined number, a desired level margin can be ensured by switching the level accordingly.

(2) The above +1) provides the effect that an EEPROM device having highly reliable data retention characteristics can be obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. In the above memory cell, the isolation MOSFET Q3 may be omitted and the source of the MNOS transistor may be connected to the reference potential line. In this case, the reference potential line is set in a floating state during a write operation, and is given the ground potential of the circuit during read and erase operations, so that the above-mentioned write/erase is possible. considered to be a line. Also, write/write to the above MNO3 transistor
The erasing method may be one in which the relationship between the well potential and the potentials of the data line and the word V line is relatively changed as described above.The specific configuration of the counting circuit and the reference voltage generation circuit may be varied. Embodiments can be adopted.

Further, the electrically writable/erasable memory element may be of the FLOTOX (floating gate tunnel oxide) type.

When using such a memory element, its writing/
A control voltage corresponding to the erase operation is supplied. The EEPROM device may be built into a semiconductor integrated circuit device such as a one-chip microcomputer.

〔Effect of the invention〕

A simple explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, the read reference voltage of a memory array configured by a matrix arrangement of memory cells including semiconductor nonvolatile memory elements that can be written and erased and MOS FETs for address selection is determined by the threshold voltage of the memory element. When the number of rewrites that cause a change reaches a predetermined number, the level is switched to a level corresponding to the number of rewrites, thereby making it possible to obtain highly reliable data retention characteristics with respect to the number of rewrites.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the main part of an EEFROM device according to the present invention. FIG. 2 is a circuit diagram of an embodiment of the counting circuit. FIG. A characteristic diagram showing the relationship between value and voltage, Figure 4, shows the MNO
FIG. 3 is a data retention characteristic diagram of an S transistor. M-ARY...Memory array, X-DCR...X decoder, Y-OCR...Y decoder, C-3W...Column switch, LVC...Level conversion circuit, FF...Latch circuit, G...Gate circuit , ■ig-G, Vw-G, V
c-G...control'4B voltage generation circuit, SA...sense amplifier, OBC...output circuit, DOB...data output circuit,
DIB...Data input circuit, WELL1, WELL2.
WELL3...well area, ○SC...oscillation circuit, TG
・・Timing generation circuit, C0UNT・・Counting section, MN
OS: Memory circuit, FF0-FFI: Flip-flop circuit, RW C: Control circuit, VGI, Vc2: Voltage generation circuit

Claims (1)

[Scope of Claims] 1. A memory array consisting of a matrix arrangement of memory cells including semiconductor non-volatile memory elements that can be electrically written and erased; A counting circuit detects the number of writes, and the detection output of this counting circuit changes the reference voltage supplied to a differential sense amplifier that receives the read signal of the memory cell in accordance with the number of writes to the memory cell. An EEPROM device characterized in that the level is switched according to the read signal level. 2. The semiconductor nonvolatile memory element is an MNOS transistor, and the counting circuit has a counting section and a memory circuit using the MNOS transistor, and when an operating voltage is supplied to the semiconductor memory device, the counting memory of the memory circuit is Claim 1, characterized in that information is read into the counting section as an initial value, and when the writing operation mode is set, the counting section performs counting and writes the counting result to the storage circuit. EEPROM device as described.