WO1996004658A1 - Bit resolution optimising mechanism - Google Patents

Bit resolution optimising mechanism Download PDF

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Publication number
WO1996004658A1
WO1996004658A1 PCT/GB1995/001824 GB9501824W WO9604658A1 WO 1996004658 A1 WO1996004658 A1 WO 1996004658A1 GB 9501824 W GB9501824 W GB 9501824W WO 9604658 A1 WO9604658 A1 WO 9604658A1
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WO
WIPO (PCT)
Prior art keywords
cells
storage system
optimising
memory storage
memory
Prior art date
Application number
PCT/GB1995/001824
Other languages
French (fr)
Inventor
Alexander Roger Deas
Original Assignee
Memory Corporation Plc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Memory Corporation Plc filed Critical Memory Corporation Plc
Publication of WO1996004658A1 publication Critical patent/WO1996004658A1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563—Multilevel memory reading aspects
    • G11C2211/5634—Reference cells

Definitions

  • the present invention is applicable in particular, though not exclusively, to non-volatile memory cells that can be used as analogue memory stores.
  • These cells include devices such as FLASH EPROM (Erasable Programmable Read Only Memory) cells, EEPROM cells and chalcogenide semiconductor material memory cells.
  • FLASH EPROM Erasable Programmable Read Only Memory
  • EEPROM Electrically Erasable Programmable Read Only Memory
  • chalcogenide semiconductor material memory cells In the semiconductor industry, EPROM cells are frequently used for memory applications because they can be read very quickly, erased and reprogrammed within a few seconds, and have the advantage of non-volatility, i.e. they retain the information stored on them after power is removed. These advantages ensure that Flash memories are ideal for storing programs for embedded controllers, and for use as solid state disk drives. EPROM cells are programmed by successively adding charge to the floating gate of the device.
  • an EPROM can store variable amounts of charge on its floating gate means that it is ideal for use in a multi- valued logic system (an analogue storage system).
  • a multi-valued logic system is a system where each cell stores information which represents a number of binary digits.
  • analogue storage cells are required for multi- state storage to be operable.
  • serious problems have been encountered when memory cells are used as analogue storage devices, i.e. when each cell stores information equivalent to more than one binary digit. These problems arise as a result of charge leakage.
  • the amount of charge stored on the floating gate of the device diminishes with time, thus the value stored on the memory cell changes with time. This means that when a location is read some time after the cell was charged the voltage value read may be lower than that originally stored. This has proved to be a major cause of concern. The problem becomes more acute as more bits of information are stored on each cell because the charge separation between voltage levels decreases.
  • Analogue to digital converters have been used in memory systems incorporating multi-state logic devices. The analogue to digital converter must have additional bits to resolve the decay in charge stored and recover the original value. For example, a signal drooping from IV to 0.9V read at 8 bits accuracy would require another bit to track the decay. Using analogue to digital converters which have a higher resolution than is necessary is not very economical.
  • Analogue to digital converters are expensive so any reduction in the number of bits required in the analogue to digital converter to perform accurate conversion of the signal represents a major saving in cost and is therefore highly desirable.
  • One proposed solution to the problem of charge leakage is to use reference cells to monitor the decay in voltage level. This solution does not fully address the problem however.
  • the invention therefore provides a method of optimising the storage capacity of non-volatile cells in a memory storage system wherein that method consists of determining the linear range of each said non-volatile cell in the said memory storage system, using calibrated reference sites to store the values of the maximum and minimum gate voltages for the linear region of the said cells, applying an offset derived from the said calibrated reference sites to ensure that the gate voltages stored on each of the said cells is within the said linear range, followed or preceded by applying a scaling voltage to expand the said linear range.
  • the reference sites may be standard cells in the memory storage system or they may be specifically designed for the purpose. A number of reference sites or even just one may be used.
  • the memory system may contain reference sites at different areas which would be used for a particular local area of the memory system. This would be useful if there was any areal variation in the transfer characteristics of the cells. Reference sites may be used for an entire row or an entire column in the memory storage system.
  • Figure 1 shows a graph of the drain current (I D ) versus gate-source voltage (Vgs) for three different FETs (Field Effect Transistor);
  • Figure 2 shows an analogue storage cell with the drain of the FET 6 connected to a power supply 8 via a current source 10 that delivers a known current.
  • the drain of the FET 6 also connects to a buffer 12.
  • the output of the buffer 12 connects to a circuit 14 for producing an output signal that equals the input signal minus a reference value 16, the reference value being the 00 level in this case.
  • the output from this circuit 14 is scaled using a scaling circuit 18 and the second reference level 20, in this case the FF level.
  • Figure 1 shows the variation in both off current and saturation current for different FETs.
  • the linear region marked on the graph refers to the region between the knees of all three FET responses.
  • the graph clearly demonstrates the fact that although each memory cell in an array may contain the same logic level, for example 00, the actual voltage value stored on each cell may differ between cells. This occurs as a result of a number of factors, including different transistor threshold values.
  • the system of Figure 2 shows one embodiment of the present invention which is designed to overcome the problems associated with differing voltage values representing the same logic level. It is a system for normalising the maximum and minimum values of gate voltage to ensure that the response curves (transfer characteristics) are standardised. For simplicity the row and column select circuitry has been omitted from this diagram. The circuit provides a means of reducing the dynamic range of each cell such that only voltage values which lie in the linear range for all cells are used. However, increased dynamic range is possible if reference sites hold the lowest and highest levels for a sector of cells (which could be the minimum number of cells which can be erased) and the normalising circuit shifts the incoming level to compensate for these differences.
  • the reference cells may need to be refreshed periodically: i.e. they may need to have the original voltage value reapplied periodically.
  • the frequency with which this re-application of the original voltage has to be made will depend on the rate of decay of the cell voltage. If only a few bits (perhaps two) are stored on each cell and the decay rate is low then a refresh cycle may not be needed. If, however, many bits (more than three) are stored on each cell then a refresh cycle will probably be needed unless the decay rate is minimal.
  • the memory system may contain the necessary timing and logic circuitry to enable this refresh procedure to be performed automatically. The refresh procedure may be triggered by the passing of a certain amount of time or by a certain level of decay in one or more of the cells.
  • Figure 1 shows a circuit that could be used for an analogue storage system which stores any one of 256 different logic levels on a single cell, this arrangement would be used for eight bit storage on each cell.
  • the 00 and FF reference values are obtained from the charging characteristic (transfer characteristic) curves for the cells in the particular sector of non- volatile memory that is being compensated.
  • the charge characteristic is determined using standard test apparatus which is available for that purpose.
  • the cells on a device may be characterised when the device is fabricated or the cells may be calibrated at some later time. Control means may be included to group cells which have similar transfer characteristics, thus the cells may be grouped according to electrical characteristics rather than physical location.
  • the 00 reference value is subtracted from the voltage stored on the memory cell. The resulting voltage is then scaled according to the FF reference value.
  • This scaling operation could be performed by an analogue multiplier, a variable gain amplifier, an attenuator, or by any other convenient means.
  • the operation may be performed in either the digital or the analogue domain.
  • the circuitry for determining the offset and scaling factor required may be connected to each row and each column of the device, or it may only be connected to either the rows or the columns.
  • only one reference site for either the maximum voltage level or the minimum voltage level
  • two reference sites for both the maximum and minimum voltage levels
  • inventions of the present invention may use current sources or other devices (for example a resistor load) that give a constant output rather than merely a current source that gives a known output.
  • Other embodiments of the present invention may use an additive offset rather than a subtractive offset, depending on whether the signal is negative or positive.
  • the offset may be subtracted after the scaling has been applied rather than before the scaling has been applied.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)

Abstract

A circuit for use in a multi-valued logic non-volatile storage system, where the circuit optimises the storage capacity of each of the cells in the storage system. The optimising process is performed by determining the linear range of the storage cells, applying an offset derived from calibrated reference sites containing maximum and minimum useful values of the gate voltage to ensure that operation is only within that linear range, followed or preceded by applying a scaling voltage to expand or attenuate the linear range.

Description

Bit Resolution Optimising Mechanism
The present invention is applicable in particular, though not exclusively, to non-volatile memory cells that can be used as analogue memory stores. These cells include devices such as FLASH EPROM (Erasable Programmable Read Only Memory) cells, EEPROM cells and chalcogenide semiconductor material memory cells. In the semiconductor industry, EPROM cells are frequently used for memory applications because they can be read very quickly, erased and reprogrammed within a few seconds, and have the advantage of non-volatility, i.e. they retain the information stored on them after power is removed. These advantages ensure that Flash memories are ideal for storing programs for embedded controllers, and for use as solid state disk drives. EPROM cells are programmed by successively adding charge to the floating gate of the device. The fact that an EPROM can store variable amounts of charge on its floating gate means that it is ideal for use in a multi- valued logic system (an analogue storage system). A multi-valued logic system is a system where each cell stores information which represents a number of binary digits. In an effort to increase the storage capacity of memory devices without further increases of their physical size much attention has been given to using multi-state storage. For multi- state storage to be operable, analogue storage cells are required. However, serious problems have been encountered when memory cells are used as analogue storage devices, i.e. when each cell stores information equivalent to more than one binary digit. These problems arise as a result of charge leakage. The amount of charge stored on the floating gate of the device diminishes with time, thus the value stored on the memory cell changes with time. This means that when a location is read some time after the cell was charged the voltage value read may be lower than that originally stored. This has proved to be a major cause of concern. The problem becomes more acute as more bits of information are stored on each cell because the charge separation between voltage levels decreases.
To overcome this problem, therefore, there must be some method of accounting for the decay and scaling the value accordingly, otherwise the cells will be storing incorrect values. A further problem with analogue storage devices is that the transfer characteristic of each memory cell is different. This problem will be considered again later. Analogue to digital converters have been used in memory systems incorporating multi-state logic devices. The analogue to digital converter must have additional bits to resolve the decay in charge stored and recover the original value. For example, a signal drooping from IV to 0.9V read at 8 bits accuracy would require another bit to track the decay. Using analogue to digital converters which have a higher resolution than is necessary is not very economical. Analogue to digital converters are expensive so any reduction in the number of bits required in the analogue to digital converter to perform accurate conversion of the signal represents a major saving in cost and is therefore highly desirable. One proposed solution to the problem of charge leakage is to use reference cells to monitor the decay in voltage level. This solution does not fully address the problem however.
A further aspect of the problem, particularly apparent when a large number of memory cells are used, is the spread in saturation current and off current for the devices. Since there are variations between cells, (i.e. each cell is slightly different electrically) each cell will have its own unique transfer characteristic. Statistically, when a large number of these cells are used in one device then there will be a spread of maximum and minimum values of saturation current and off current. This creates problems for the sense amplifier and conversion parts of the circuit (the parts of the circuit that sense the value stored in the cell and convert it to the correct bit sequence) because there will be a range of values for the same logic level throughout the memory system. This means that the effective range of voltages which can be stored on the device is restricted. The useful range is limited to between the highest off current value and the lowest saturation current value. Thus there is a narrowing of the useful window which can be used for storing voltage levels.
It is an object of the present invention to provide a method of compensating for the variations in the maximum and minimum signal values which can be stored on a cell. It is another object of the present invention to provide a method of improving the performance of multi-state storage memories.
It is a further object of the present invention to utilise the full dynamic range of a cell by scaling the linear portion of the dynamic range. The invention therefore provides a method of optimising the storage capacity of non-volatile cells in a memory storage system wherein that method consists of determining the linear range of each said non-volatile cell in the said memory storage system, using calibrated reference sites to store the values of the maximum and minimum gate voltages for the linear region of the said cells, applying an offset derived from the said calibrated reference sites to ensure that the gate voltages stored on each of the said cells is within the said linear range, followed or preceded by applying a scaling voltage to expand the said linear range.
The reference sites may be standard cells in the memory storage system or they may be specifically designed for the purpose. A number of reference sites or even just one may be used. The memory system may contain reference sites at different areas which would be used for a particular local area of the memory system. This would be useful if there was any areal variation in the transfer characteristics of the cells. Reference sites may be used for an entire row or an entire column in the memory storage system.
For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made, by way of example, without loss of generality, to the accompanying drawing, in which: Figure 1 shows a graph of the drain current (ID) versus gate-source voltage (Vgs) for three different FETs (Field Effect Transistor); and
Figure 2 shows an analogue storage cell with the drain of the FET 6 connected to a power supply 8 via a current source 10 that delivers a known current. The drain of the FET 6 also connects to a buffer 12. The output of the buffer 12 connects to a circuit 14 for producing an output signal that equals the input signal minus a reference value 16, the reference value being the 00 level in this case. The output from this circuit 14 is scaled using a scaling circuit 18 and the second reference level 20, in this case the FF level. Figure 1 shows the variation in both off current and saturation current for different FETs. The linear region marked on the graph refers to the region between the knees of all three FET responses. The graph clearly demonstrates the fact that although each memory cell in an array may contain the same logic level, for example 00, the actual voltage value stored on each cell may differ between cells. This occurs as a result of a number of factors, including different transistor threshold values. The system of Figure 2 shows one embodiment of the present invention which is designed to overcome the problems associated with differing voltage values representing the same logic level. It is a system for normalising the maximum and minimum values of gate voltage to ensure that the response curves (transfer characteristics) are standardised. For simplicity the row and column select circuitry has been omitted from this diagram. The circuit provides a means of reducing the dynamic range of each cell such that only voltage values which lie in the linear range for all cells are used. However, increased dynamic range is possible if reference sites hold the lowest and highest levels for a sector of cells (which could be the minimum number of cells which can be erased) and the normalising circuit shifts the incoming level to compensate for these differences.
With the ability to offset a FET response curve (such as the ones plotted in Figure 1) and to scale the linear region, a greater dynamic range can be stored.
Since there is always a decay with time in the voltage value stored in non-volatile cells the reference cells may need to be refreshed periodically: i.e. they may need to have the original voltage value reapplied periodically. The frequency with which this re-application of the original voltage has to be made will depend on the rate of decay of the cell voltage. If only a few bits (perhaps two) are stored on each cell and the decay rate is low then a refresh cycle may not be needed. If, however, many bits (more than three) are stored on each cell then a refresh cycle will probably be needed unless the decay rate is minimal. The memory system may contain the necessary timing and logic circuitry to enable this refresh procedure to be performed automatically. The refresh procedure may be triggered by the passing of a certain amount of time or by a certain level of decay in one or more of the cells.
Figure 1 shows a circuit that could be used for an analogue storage system which stores any one of 256 different logic levels on a single cell, this arrangement would be used for eight bit storage on each cell. The 00 and FF reference values are obtained from the charging characteristic (transfer characteristic) curves for the cells in the particular sector of non- volatile memory that is being compensated. The charge characteristic is determined using standard test apparatus which is available for that purpose. The cells on a device may be characterised when the device is fabricated or the cells may be calibrated at some later time. Control means may be included to group cells which have similar transfer characteristics, thus the cells may be grouped according to electrical characteristics rather than physical location. The 00 reference value is subtracted from the voltage stored on the memory cell. The resulting voltage is then scaled according to the FF reference value. This scaling operation could be performed by an analogue multiplier, a variable gain amplifier, an attenuator, or by any other convenient means. The operation may be performed in either the digital or the analogue domain. The circuitry for determining the offset and scaling factor required may be connected to each row and each column of the device, or it may only be connected to either the rows or the columns.
In other embodiments of the present invention only one reference site (for either the maximum voltage level or the minimum voltage level) may be used rather than two (for both the maximum and minimum voltage levels).
Other embodiments of the present invention may use current sources or other devices (for example a resistor load) that give a constant output rather than merely a current source that gives a known output. Other embodiments of the present invention may use an additive offset rather than a subtractive offset, depending on whether the signal is negative or positive.
It will be appreciated that various modifications may be made to the above described embodiment within the scope of the present invention. For example the offset may be subtracted after the scaling has been applied rather than before the scaling has been applied.

Claims

Claims
1. A method for optimising the storage capacity of non-volatile cells in a memory storage system wherein that method consists in determining the linear range of each said non¬ volatile cell in the said memory storage system, using calibrated reference sites to store the values of the maximum and minimum gate voltages for the linear region of the said cells, applying an offset derived from the said calibrated reference sites to ensure that the gate voltages stored on each of the said cells is within the said linear range, followed or preceded by applying a scaling voltage to expand or attenuate the said linear range.
2. A method for optimising the storage capacity of non- volatile cells in a memory storage system according to claim 1 wherein the calibrated reference sites are standard non- volatile cells.
3. A method for optimising the storage capacity of non- volatile cells in a memory storage system according to claim 1 or 2 wherein a plurality of calibrated reference sites are used and the said calibrated reference sites are disposed at different areas of the device.
4. A method for optimising the storage capacity of non- volatile cells in a memory storage system according to any preceding claim wherein the said memory storage system is an
EEPROM.
5. A method for optimising the storage capacity of non- volatile cells in a memory storage system according to any preceding claim wherein the said memory storage system is an EPROM.
PCT/GB1995/001824 1994-08-02 1995-08-02 Bit resolution optimising mechanism WO1996004658A1 (en)

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GB9415539A GB9415539D0 (en) 1994-08-02 1994-08-02 Bit resolution optimising mechanism
GB9415539.7 1994-08-02

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0896763A1 (en) * 1996-04-30 1999-02-17 Agate Semiconductor, Inc. Stabilization circuits for multiple digital bits
US6282145B1 (en) 1999-01-14 2001-08-28 Silicon Storage Technology, Inc. Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system
US6285598B1 (en) 1997-03-06 2001-09-04 Silicon Storage Technology, Inc. Precision programming of nonvolatile memory cells
US6396742B1 (en) 2000-07-28 2002-05-28 Silicon Storage Technology, Inc. Testing of multilevel semiconductor memory
US6462986B1 (en) 1995-10-06 2002-10-08 Silicon Storage Technology, Inc. Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell
US8899463B2 (en) 2010-09-30 2014-12-02 Ethicon Endo-Surgery, Inc. Surgical staple cartridges supporting non-linearly arranged staples and surgical stapling instruments with common staple-forming pockets

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JPS62201367A (en) * 1986-02-28 1987-09-05 Sony Tektronix Corp Display reference signal generating device
JPS6329397A (en) * 1986-07-23 1988-02-08 Hitachi Vlsi Eng Corp Eeprom device
JPS63274201A (en) * 1987-05-04 1988-11-11 Rohm Co Ltd Drive circuit

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JPS5671898A (en) * 1979-11-15 1981-06-15 Nippon Texas Instr Kk Nonvolatile semiconductor memory device and its testing method
US4593203A (en) * 1982-02-10 1986-06-03 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor integrated circuit which allows adjustment of circuit characteristics in accordance with storage data of nonvolatile memory element
JPS62201367A (en) * 1986-02-28 1987-09-05 Sony Tektronix Corp Display reference signal generating device
JPS6329397A (en) * 1986-07-23 1988-02-08 Hitachi Vlsi Eng Corp Eeprom device
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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6462986B1 (en) 1995-10-06 2002-10-08 Silicon Storage Technology, Inc. Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell
EP0896763A1 (en) * 1996-04-30 1999-02-17 Agate Semiconductor, Inc. Stabilization circuits for multiple digital bits
EP0896763A4 (en) * 1996-04-30 2000-08-16 Agate Semiconductor Inc Stabilization circuits for multiple digital bits
US6285598B1 (en) 1997-03-06 2001-09-04 Silicon Storage Technology, Inc. Precision programming of nonvolatile memory cells
US6282145B1 (en) 1999-01-14 2001-08-28 Silicon Storage Technology, Inc. Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system
US7471581B2 (en) 1999-01-14 2008-12-30 Silicon Storage Technology, Inc. Wide dynamic range and high speed voltage mode sensing for a multilevel digital non-volatile memory
US7848159B2 (en) 1999-01-14 2010-12-07 Silicon Storage Technology, Inc. Non-volatile memory systems and methods including page read and/or configuration features
US9640263B2 (en) 1999-01-14 2017-05-02 Silicon Storage Technology, Inc. Non-volatile memory systems and methods
US6396742B1 (en) 2000-07-28 2002-05-28 Silicon Storage Technology, Inc. Testing of multilevel semiconductor memory
US8899463B2 (en) 2010-09-30 2014-12-02 Ethicon Endo-Surgery, Inc. Surgical staple cartridges supporting non-linearly arranged staples and surgical stapling instruments with common staple-forming pockets

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