JPS62201367A - Display reference signal generating device - Google Patents

Abstract

PURPOSE:To confirm and accurately calibrate the gain and DC offset characteristics of a display device by supplying the output signal of a display reference signal generating device or the display device to display a graphic form which indicates a maximum and a minimum value, and comparing the graphic form with a scale. CONSTITUTION:A potentiometer 30a supplies a DC voltage corresponding to the maximum permissible amplitude based upon the scale on a display screen to a signal generating means 34 and a potential meter 32a supplies a DC voltage corresponding to the minimum permissible amplitude. The means 34 is equipped with inverting and noninverting amplifiers 10 and 12 whose input terminals are connected in common and DC voltages are selected alternately by electronic switches 14 and 16 at the input terminals and output terminals of the amplifiers 10 nd 12 to obtain pulse signals 36, i.e. maximum permissible value reference signal and minimum permissible value reference signal. Those reference signals are supplied to the deflecting circuit of the display device to display the maximum and minimum values on the display screen alternately, and the display graphic form is compared with the scale to easily and accurately know whether or not the calibration state of the display device is within the permissible value range.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a display reference signal suitable for calibrating or checking the gain and DC offset of a display device equipped with a cathode ray tube having a scale on a display screen. The present invention relates to a display reference signal generator.

[Prior Art] To calibrate or check the gain and DC offset of a display device (e.g. curve tracer, oscilloscope) equipped with a cathode ray tube with a scale on the display screen, it is necessary to use a constant voltage with a known voltage value or a constant voltage with a known amplitude and period. A known square wave etc.
It was used as a display reference signal. Then, by supplying a display reference signal to one of the vertical and horizontal deflection circuits of the display device and a sweep signal to the other, a straight line or square wave was displayed on the display screen. The gain and DC offset could be calibrated or confirmed by comparing this straight or square wave with the scale on the display screen.

[Problems to be Solved by the Invention] With the conventional display reference signal, only the reference value is displayed on the cathode ray tube display, so it is necessary to adjust the gain and DC offset of the cathode ray tube display and check whether they are perfect. However, it is troublesome to check whether the calibration is within a certain tolerance. That is, it was necessary to determine in advance to what extent the scale on the display screen and the displayed straight line or square wave deviate from the allowable value.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a display reference signal generating device that can easily confirm whether the gain and DC offset of a cathode ray tube display device are within tolerance values and is also suitable for calibration.

Means for Solving Problem E] The display reference signal generating device of the present invention includes a first means for outputting a maximum permissible amplitude based on a small amount of the display screen (both between two predetermined portions); a second means for outputting a minimum allowable value amplitude based on at least two predetermined portions; and a generating means for alternately generating maximum and minimum allowable value reference signals in accordance with the outputs of the first and second means. It is equipped with

[Operation] According to the present invention, the signal generating means alternately generates maximum and minimum allowable value reference signals corresponding to the maximum and minimum allowable value amplitudes output by the first and second means.

If the reference signal from this signal generating means is supplied to the deflection circuit of the cathode ray tube display device, the
The maximum and minimum allowed reference signals are displayed alternately. Therefore, by comparing this display with the large scale, it is possible to immediately, easily and accurately know whether the calibration state of the cathode ray tube display device is within the permissible value.

[Example] Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. 1st
The figure is a block diagram illustrating the invention in detail. The display reference signal generating device 35 includes a first means 30, a second means 32, and a signal generating means 34. These first and second
Means 30 and 32 output maximum and minimum allowable amplitudes, respectively, based on a predetermined value. The signal generating means 34
and generating alternating maximum and minimum allowed reference signals depending on the output values from the second means 30 and 32. The present invention
It is assumed that the output signal of the signal generating means 34 is supplied to a cathode ray tube display device, and that the first and second means 30
and 32 correspond to at least two predetermined portions of the scale of the display screen of the cathode ray tube display.

Therefore, when the tolerance reference signal from the signal generating means 34 is supplied to the display device, if the display device has been calibrated, the maximum and minimum tolerance reference signals will be displayed so as to sandwich a predetermined portion of the scale. That is, if these reference signal displays sandwich a predetermined portion of the scale on the display screen, the gain and DC offset of the display device are within the permissible values.

[First Embodiment] Next, a first embodiment of the present invention is shown in FIG. In this embodiment, the first means 30a is a potentiometer and supplies a DC voltage to the signal generating means 34a corresponding to the maximum permissible amplitude with respect to the scale on the display screen. Similarly, the second means 32a is also a potentiometer and supplies a DC voltage corresponding to the minimum permissible amplitude to the signal generating means 34a.

The signal generating means 34a includes an inverting amplifier 10 and a non-inverting amplifier 12 having the same gain and whose input terminals are commonly connected. The output signals of the potentiometers 30a and 32a are alternately supplied to the input terminals of these amplifiers 10 and 12 by an electronic switch 14, and the output signals of the amplifiers 10 and 12 are alternately selected by an electronic switch 16 and used as a reference signal. .

Note that the switch 16 is directly controlled by the clock signal from the clock oscillation circuit 20, and the switch 14 is controlled by the divided output signal of the frequency dividing circuit 18 that divides this clock signal, so the output signal of the switch 16 is A pulse as shown in waveform 36 in FIG. 3 is obtained. This pulse 36 is a maximum allowable value reference signal whose amplitude is determined by the potentiometer 30a during the period T1, and a minimum allowable value reference signal whose amplitude is determined by the potentiometer 32a during the period T2.

When the reference signal 36 and sweep signal from the display reference signal generator are supplied to the vertical deflection circuit and horizontal deflection circuit of the cathode ray tube display, respectively, the display on the display screen 22 becomes as shown in FIG. Note that the display device has been calibrated.

In FIG. 4, the predetermined portion of the scale 24 that the first and second means refer to is the outermost portion of the scale 24, and dotted lines 26 and 28 are indicated by the maximum and minimum allowable value reference signals, respectively. . The above explanation displays the vertical maximum and minimum allowable value reference signals on the display screen, but by swapping this reference signal and the sweep output, the horizontal maximum and minimum allowable values can be displayed on the display screen. Needless to say, it is possible to display

[Second Embodiment] FIG. 5 shows a second embodiment of the present invention. In this embodiment, a register (memory circuit) is used as the first and second means, and the register 30b stores digital data corresponding to the maximum allowable amplitude, and this digital data is used to generate a signal. input to the means 34b.Similarly, the register 3
2b stores digital data corresponding to the minimum allowable value amplitude, and transmits this digital data to the signal generating means 34b.
Enter. The multiplexer (
MUX) 40 alternately selects the output data from registers 30b and 32b, and D/A converter 42 converts the output data from multiplexer 40 to an analog output voltage. If registers 30b and 32b store the positive and negative values of each allowable amplitude, respectively, the analog output voltage of D/A converter 42 will have a waveform such as waveform 36, for example.

Furthermore, if this output voltage waveform 36 is provided to a display device,
The display screen is displayed as shown in FIG.

It goes without saying that a sweep signal is required as in the case of the first embodiment.

[Third Embodiment] FIG. 6 shows a third embodiment of the present invention. According to a program stored in a part of the read-only memo 1J46 (hereinafter referred to as ROM), a random access memory 48 (hereinafter referred to as RAM) is used to operate the central processing unit 44 (hereinafter referred to as CPU). Other areas in the ROM 46, for example, the waveform 50 in FIG.
Digital data corresponding to a pair of analog output waveforms such as and 52 are stored. The reason why there are two output systems for the display reference signal generator is that both the vertical and horizontal deflection circuits of the display device are considered. When the CPU 44 operates, it supplies digital data corresponding to waveforms 50 and 52 in the ROM 46 corresponding to the functions of the first and second means to the D/A converters 42a and 42b corresponding to the signal generating means, respectively. As a result, output waves 50 and 52 as shown in FIG. 7, for example, are obtained as reference signals. When these output waveforms 50 and 52 are supplied to the vertical and horizontal deflection circuits of a display device, they are displayed on the screen 54 as shown in FIG. In addition, in FIG. 8, 56 is a scale provided on the display screen 54, and the outer dotted line rectangle 58
The inner dotted line rectangle 60 is the display based on the minimum allowable value reference signal.

The gist of the invention is to graphically display the maximum and minimum allowed amplitudes on a display screen.

Therefore, this figure is not limited to a rectangle as shown in FIG. 8, but may be a figure as shown in FIGS. 9 and 10, for example. Further, when the scale is circular like the display screen of a vector scope, it is appropriate to display the display as shown in FIGS. 11A and 11B, for example. In order to display the figures in Figures 9-11 on the display screen, simply store the ROM 46
All you need to do is change the data to obtain the output waveform within.

In the case of FIG. 11B, it is sufficient to generate a sine wave whose phase is shifted by 90 degrees. Sine wave converts digital data into D/A
In addition to being added to a converter, it may also be generated by a combination of a sine wave generator and a phase shift circuit.

[First Application Example] FIG. 12 shows a first application example of the present invention. Display device 10
0 is an XY display device, which is composed of a vertical deflection circuit 64, a horizontal deflection circuit 66, and a cathode ray tube 102. The vertical deflection circuit 64 is basically composed of a differential amplifier, and includes a variable resistor 68 (hereinafter abbreviated as VR) for gain adjustment and a VR 70 for DC offset adjustment.

The configuration of the horizontal deflection circuit 66 is the same as that of the vertical deflection circuit 64. The interlocked switches 104 and 106 are connected to the display reference signal generating device (eg, the embodiment of FIG. 6) 3 of the present invention.
5 or the display signal generation circuit 62 to display the display bag M10.
Connect to 0. Note that the display signal generation circuit 62 is a measurement unit that generates, for example, X and Y signals indicating the characteristics of a semiconductor to be measured.

The output of the display reference signal generation circuit 35b is transmitted to the vertical deflection circuit 6.
4 and the horizontal deflection circuit 66, if a display like that shown in FIG. 8 is obtained on the cathode ray tube 100, the CRT
The characteristics of the display device are within acceptable limits. Now, if at least one of the gain and DC offset of the vertical deflection circuit 64 is defective, the display of the reference signal will be shifted in the vertical direction. In this case, VRs 68 and 70 of the vertical deflection circuit 64 may be adjusted appropriately so that the display shown in FIG. 8 is obtained.

Needless to say, the situation is exactly the same when the horizontal deflection circuit 66 is defective.

[Second Application Example] FIG. 13 shows a second application example of the present invention. This is a display device 100 that displays digital input signals as analog signals and also displays analog input signals, with a digital display reference signal generation circuit 72 and an analog display reference signal generation circuit 74 added. Digital display reference signal generation circuit 72 is connected to vertical deflection circuit 64 and horizontal deflection circuit 66 via switches 80 and 82, respectively. Note that these switches 80 and 82 are controlled by a control circuit 91. The analog display reference signal generation circuit 74 and the analog display signal generation circuit 78 are selected by switches 86 and 87, and are connected to the vertical deflection circuit 6 via switches 80 and 82.
4 and horizontal deflection circuit 66, respectively. Display signal generation circuits 76 and 78 generate display signals in digital and analog states. The display device 100 is the same as the display device portion in FIG. Further, the digital display reference signal generation circuit 72 has a configuration similar to that shown in FIG.
c are provided respectively.

Since the digital display signal generation circuit 76 is connected to the bus 88 in the digital display reference signal generation circuit 72, the CPU 44
, ROM 46 and RAM 48 also control the display signal generation circuit 76, and the D/A converters 42a and 42b also convert the digital signals from the display signal generation circuit 76 into analog signals. The analog display reference signal generation circuit 74 uses two sets of constant voltage power supplies (-Vl and +1 and +V2 and +V2) having the same absolute value and different signs. Under the control of the switching control circuit 90, the switch 96 sequentially selects 11.0 and 10V1, and the switch 98 selects -V2.0 and +V1.
Since V2 is sequentially selected, the output waveforms of switches 96 and 98 become, for example, waveforms 130 and 140 in FIG. 14. To display the output signal of analog display signal generation circuit 78, switches 86 and 87 select this circuit 78, and switch control circuit 91 selects switches 80 and 82.
selects switches 86 and 87, respectively. Further, in order to display the output signal of the digital display signal generation circuit 76, the switch control circuit 91 switches the switches 80 and 82 to
A converters 42a and 42b are selected, respectively, and the digital output signal of circuit 76 is transferred to these D/A converters 42a and 42b.
supply to.

In order to calibrate the gain and DC offset of the display device 100 shown in FIG. 72
and the output of the analog display reference signal generation circuit 74 are applied alternately. On the display screen of the cathode ray tube 102, the 15th
As shown in the figure, a double frame of nine dots and dotted lines is displayed. Here, out of the nine points, eight points excluding the center point 59 are
The VRs 68b, 68c, 70b and 70c are adjusted so that they fit within the double frame defined by dotted lines 58 and 60. Note that at this stage, the vertical deflection circuit 64 and the horizontal deflection circuit 6
6, the digital display reference signal generation circuit 72
It should be noted that the Dy/A converters 42a and 42b that make up the circuit are adjusted. Next, the VRs 68 and 70 are adjusted so that the outside/frame of the scale on the screen falls within the double frame formed by dotted lines 58 and 60. At the same time, it goes without saying that the gain and DC offset of the horizontal deflection circuit 66 are adjusted three times. Note that the adjustment at this stage is performed for the vertical and horizontal deflection circuits through which the outputs of the digital display reference signal generation circuit 72 and the analog display reference signal generation circuit 74 commonly pass, so dotted lines 58 and 60 are used to Please note that the nine points will automatically fit within the outer frame of the display screen after adjustment.

Although the above description has been made regarding preferred embodiments and application examples of the present invention, it will be easy for those skilled in the art to make various modifications and variations without departing from the gist of the present invention. For example, the maximum or minimum allowable value indicating figure may be a solid line. Further, digital data for obtaining another pair of vertical and horizontal reference waveforms may be stored in the ROM 46, and the tolerance reference waveforms for the two dishes may be displayed. Furthermore, D/D is provided at the input stage of the vertical and horizontal deflection circuits of the display device, respectively.
If the device is equipped with an A converter and receives a digital signal as an input signal, the maximum and minimum allowable value reference signals may be digital signals.

[Effect of the Invention] As described above, if the output signal of the display reference signal generator of the present invention is supplied to the display device, a figure indicating the maximum and minimum allowable values can be displayed on the display screen. By comparing the values, the gain and DC offset characteristics of the display device can be confirmed and calibrated easily and accurately within a short time. Further, according to the present invention, since the standard display has a range of maximum and minimum allowable values on the display screen, even if the display in the peripheral area of the display screen is distorted due to pincushion distortion of the cathode ray tube, the gain and DC offset can be adjusted. can be easily calibrated to within tolerance.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the principle of the present invention; FIGS. 2, 5, and 6 are book diagrams of preferred embodiments of the present invention; and FIGS.
and Fig. 14 is the output waveform diagram, 4th, 8th, 9th, 10th
, 11A1, 11B and 15 are diagrams showing the display on the display screen, and FIGS. 12 and 13 are block diagrams showing an example of application of the present invention. In the figure, 30, 30a and 30b represent first means;
32, 32a and 32b are second means, 34 and 34a
and 34b are signal generating means. Patent applicant: Sony Tektronix Corporation Figure 2 Figure 3 Figure 4 Figure 5 Figure 7

Claims (1)

[Scope of Claims] A display reference signal generating device for a display device equipped with a cathode ray tube having a scale on the display screen, wherein a maximum permissible amplitude with reference to at least two predetermined portions of the scale on the display screen. a first means for outputting a value of , a second means for outputting a value of a minimum allowable amplitude based on at least two predetermined portions of the scale of the display screen; A display reference signal generating device comprising signal generating means for alternately generating a maximum permissible value reference signal and a minimum permissible value reference signal according to the output.